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radv: add radv_pipeline_init_input_assembly_state()
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for AMD GCN */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "radv_util.h"
35
36 static void
37 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
38 struct radeon_cmdbuf *cs,
39 unsigned raster_config,
40 unsigned raster_config_1)
41 {
42 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
43 unsigned raster_config_se[4];
44 unsigned se;
45
46 ac_get_harvested_configs(&physical_device->rad_info,
47 raster_config,
48 &raster_config_1,
49 raster_config_se);
50
51 for (se = 0; se < num_se; se++) {
52 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
53 if (physical_device->rad_info.chip_class < GFX7)
54 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
55 S_00802C_SE_INDEX(se) |
56 S_00802C_SH_BROADCAST_WRITES(1) |
57 S_00802C_INSTANCE_BROADCAST_WRITES(1));
58 else
59 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
60 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
61 S_030800_INSTANCE_BROADCAST_WRITES(1));
62 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
63 }
64
65 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
66 if (physical_device->rad_info.chip_class < GFX7)
67 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
68 S_00802C_SE_BROADCAST_WRITES(1) |
69 S_00802C_SH_BROADCAST_WRITES(1) |
70 S_00802C_INSTANCE_BROADCAST_WRITES(1));
71 else
72 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
73 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
74 S_030800_INSTANCE_BROADCAST_WRITES(1));
75
76 if (physical_device->rad_info.chip_class >= GFX7)
77 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
78 }
79
80 void
81 si_emit_compute(struct radv_physical_device *physical_device,
82 struct radeon_cmdbuf *cs)
83 {
84 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
85 radeon_emit(cs, 0);
86 radeon_emit(cs, 0);
87 radeon_emit(cs, 0);
88
89 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
90 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
91 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
92 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
93 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
94
95 if (physical_device->rad_info.chip_class >= GFX7) {
96 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
97 radeon_set_sh_reg_seq(cs,
98 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
99 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
100 S_00B858_SH1_CU_EN(0xffff));
101 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
102 S_00B858_SH1_CU_EN(0xffff));
103 }
104
105 if (physical_device->rad_info.chip_class >= GFX10)
106 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
107
108 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
109 * and is now per pipe, so it should be handled in the
110 * kernel if we want to use something other than the default value,
111 * which is now 0x22f.
112 */
113 if (physical_device->rad_info.chip_class <= GFX6) {
114 /* XXX: This should be:
115 * (number of compute units) * 4 * (waves per simd) - 1 */
116
117 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
118 0x190 /* Default value */);
119 }
120 }
121
122 /* 12.4 fixed-point */
123 static unsigned radv_pack_float_12p4(float x)
124 {
125 return x <= 0 ? 0 :
126 x >= 4096 ? 0xffff : x * 16;
127 }
128
129 static void
130 si_set_raster_config(struct radv_physical_device *physical_device,
131 struct radeon_cmdbuf *cs)
132 {
133 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
134 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
135 unsigned raster_config, raster_config_1;
136
137 ac_get_raster_config(&physical_device->rad_info,
138 &raster_config,
139 &raster_config_1, NULL);
140
141 /* Always use the default config when all backends are enabled
142 * (or when we failed to determine the enabled backends).
143 */
144 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
145 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
146 raster_config);
147 if (physical_device->rad_info.chip_class >= GFX7)
148 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
149 raster_config_1);
150 } else {
151 si_write_harvested_raster_configs(physical_device, cs,
152 raster_config,
153 raster_config_1);
154 }
155 }
156
157 void
158 si_emit_graphics(struct radv_device *device,
159 struct radeon_cmdbuf *cs)
160 {
161 struct radv_physical_device *physical_device = device->physical_device;
162
163 bool has_clear_state = physical_device->rad_info.has_clear_state;
164 int i;
165
166 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
167 radeon_emit(cs, CC0_UPDATE_LOAD_ENABLES(1));
168 radeon_emit(cs, CC1_UPDATE_SHADOW_ENABLES(1));
169
170 if (has_clear_state) {
171 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
172 radeon_emit(cs, 0);
173 }
174
175 if (physical_device->rad_info.chip_class <= GFX8)
176 si_set_raster_config(physical_device, cs);
177
178 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
179 if (!has_clear_state)
180 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
181
182 /* FIXME calculate these values somehow ??? */
183 if (physical_device->rad_info.chip_class <= GFX8) {
184 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
185 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
186 }
187
188 if (!has_clear_state) {
189 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
190 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
191 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
192 }
193
194 if (physical_device->rad_info.chip_class <= GFX9)
195 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
196 if (!has_clear_state)
197 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
198 if (physical_device->rad_info.chip_class < GFX7)
199 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
200 S_008A14_CLIP_VTX_REORDER_ENA(1));
201
202 if (!has_clear_state)
203 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
204
205 /* CLEAR_STATE doesn't clear these correctly on certain generations.
206 * I don't know why. Deduced by trial and error.
207 */
208 if (physical_device->rad_info.chip_class <= GFX7 || !has_clear_state) {
209 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
210 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
211 S_028204_WINDOW_OFFSET_DISABLE(1));
212 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
213 S_028240_WINDOW_OFFSET_DISABLE(1));
214 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
215 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
216 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
217 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
218 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
219 }
220
221 if (!has_clear_state) {
222 for (i = 0; i < 16; i++) {
223 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
224 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
225 }
226 }
227
228 if (!has_clear_state) {
229 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
230 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
231 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on GFX6 */
232 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
233 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
234 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
235 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
236 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
237 }
238
239 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
240 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
241 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
242
243 if (physical_device->rad_info.chip_class >= GFX10) {
244 radeon_set_context_reg(cs, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0);
245 radeon_set_uconfig_reg(cs, R_030964_GE_MAX_VTX_INDX, ~0);
246 radeon_set_uconfig_reg(cs, R_030924_GE_MIN_VTX_INDX, 0);
247 radeon_set_uconfig_reg(cs, R_030928_GE_INDX_OFFSET, 0);
248 radeon_set_uconfig_reg(cs, R_03097C_GE_STEREO_CNTL, 0);
249 radeon_set_uconfig_reg(cs, R_030988_GE_USER_VGPR_EN, 0);
250 } else if (physical_device->rad_info.chip_class == GFX9) {
251 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
252 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
253 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
254 } else {
255 /* These registers, when written, also overwrite the
256 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
257 * them. It would be an issue if there was another UMD
258 * changing them.
259 */
260 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
261 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
262 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
263 }
264
265 if (physical_device->rad_info.chip_class >= GFX7) {
266 if (physical_device->rad_info.chip_class >= GFX10) {
267 /* Logical CUs 16 - 31 */
268 radeon_set_sh_reg_idx(physical_device, cs, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
269 3, S_00B404_CU_EN(0xffff));
270 radeon_set_sh_reg_idx(physical_device, cs, R_00B104_SPI_SHADER_PGM_RSRC4_VS,
271 3, S_00B104_CU_EN(0xffff));
272 radeon_set_sh_reg_idx(physical_device, cs, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
273 3, S_00B004_CU_EN(0xffff));
274 }
275
276 if (physical_device->rad_info.chip_class >= GFX9) {
277 radeon_set_sh_reg_idx(physical_device, cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
278 3, S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
279 } else {
280 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
281 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
282 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
283 S_00B41C_WAVE_LIMIT(0x3F));
284 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
285 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
286 /* If this is 0, Bonaire can hang even if GS isn't being used.
287 * Other chips are unaffected. These are suboptimal values,
288 * but we don't use on-chip GS.
289 */
290 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
291 S_028A44_ES_VERTS_PER_SUBGRP(64) |
292 S_028A44_GS_PRIMS_PER_SUBGRP(4));
293 }
294
295 /* Compute LATE_ALLOC_VS.LIMIT. */
296 unsigned num_cu_per_sh = physical_device->rad_info.min_good_cu_per_sa;
297 unsigned late_alloc_wave64 = 0; /* The limit is per SA. */
298 unsigned late_alloc_wave64_gs = 0;
299 unsigned cu_mask_vs = 0xffff;
300 unsigned cu_mask_gs = 0xffff;
301
302 if (physical_device->rad_info.chip_class >= GFX10) {
303 /* For Wave32, the hw will launch twice the number of late
304 * alloc waves, so 1 == 2x wave32.
305 */
306 if (!physical_device->rad_info.use_late_alloc) {
307 late_alloc_wave64 = 0;
308 } else if (num_cu_per_sh <= 6) {
309 late_alloc_wave64 = num_cu_per_sh - 2;
310 } else {
311 late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
312
313 /* CU2 & CU3 disabled because of the dual CU design */
314 cu_mask_vs = 0xfff3;
315 cu_mask_gs = 0xfff3; /* NGG only */
316 }
317
318 late_alloc_wave64_gs = late_alloc_wave64;
319
320 /* Don't use late alloc for NGG on Navi14 due to a hw
321 * bug. If NGG is never used, enable all CUs.
322 */
323 if (!physical_device->use_ngg ||
324 physical_device->rad_info.family == CHIP_NAVI14) {
325 late_alloc_wave64_gs = 0;
326 cu_mask_gs = 0xffff;
327 }
328 } else {
329 if (!physical_device->rad_info.use_late_alloc) {
330 late_alloc_wave64 = 0;
331 } else if (num_cu_per_sh <= 4) {
332 /* Too few available compute units per SA.
333 * Disallowing VS to run on one CU could hurt
334 * us more than late VS allocation would help.
335 *
336 * 2 is the highest safe number that allows us
337 * to keep all CUs enabled.
338 */
339 late_alloc_wave64 = 2;
340 } else {
341 /* This is a good initial value, allowing 1
342 * late_alloc wave per SIMD on num_cu - 2.
343 */
344 late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
345 }
346
347 if (late_alloc_wave64 > 2)
348 cu_mask_vs = 0xfffe; /* 1 CU disabled */
349 }
350
351 radeon_set_sh_reg_idx(physical_device, cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
352 3, S_00B118_CU_EN(cu_mask_vs) |
353 S_00B118_WAVE_LIMIT(0x3F));
354 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
355 S_00B11C_LIMIT(late_alloc_wave64));
356
357 radeon_set_sh_reg_idx(physical_device, cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
358 3, S_00B21C_CU_EN(cu_mask_gs) | S_00B21C_WAVE_LIMIT(0x3F));
359
360 if (physical_device->rad_info.chip_class >= GFX10) {
361 radeon_set_sh_reg_idx(physical_device, cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
362 3, S_00B204_CU_EN(0xffff) |
363 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64_gs));
364 }
365
366 radeon_set_sh_reg_idx(physical_device, cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
367 3, S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
368 }
369
370 if (physical_device->rad_info.chip_class >= GFX10) {
371 /* Break up a pixel wave if it contains deallocs for more than
372 * half the parameter cache.
373 *
374 * To avoid a deadlock where pixel waves aren't launched
375 * because they're waiting for more pixels while the frontend
376 * is stuck waiting for PC space, the maximum allowed value is
377 * the size of the PC minus the largest possible allocation for
378 * a single primitive shader subgroup.
379 */
380 radeon_set_context_reg(cs, R_028C50_PA_SC_NGG_MODE_CNTL,
381 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
382 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
383
384 /* Enable CMASK/FMASK/HTILE/DCC caching in L2 for small chips. */
385 unsigned meta_write_policy, meta_read_policy;
386
387 /* TODO: investigate whether LRU improves performance on other chips too */
388 if (physical_device->rad_info.num_render_backends <= 4) {
389 meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */
390 meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */
391 } else {
392 meta_write_policy = V_02807C_CACHE_STREAM_WR; /* write combine */
393 meta_read_policy = V_02807C_CACHE_NOA_RD; /* don't cache reads */
394 }
395
396 radeon_set_context_reg(cs, R_02807C_DB_RMI_L2_CACHE_CONTROL,
397 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
398 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
399 S_02807C_HTILE_WR_POLICY(meta_write_policy) |
400 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
401 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
402 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
403 S_02807C_HTILE_RD_POLICY(meta_read_policy));
404
405 radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
406 S_028410_CMASK_WR_POLICY(meta_write_policy) |
407 S_028410_FMASK_WR_POLICY(meta_write_policy) |
408 S_028410_DCC_WR_POLICY(meta_write_policy) |
409 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
410 S_028410_CMASK_RD_POLICY(meta_read_policy) |
411 S_028410_FMASK_RD_POLICY(meta_read_policy) |
412 S_028410_DCC_RD_POLICY(meta_read_policy) |
413 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
414 radeon_set_context_reg(cs, R_028428_CB_COVERAGE_OUT_CONTROL, 0);
415
416 radeon_set_sh_reg(cs, R_00B0C0_SPI_SHADER_REQ_CTRL_PS,
417 S_00B0C0_SOFT_GROUPING_EN(1) |
418 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
419 radeon_set_sh_reg(cs, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
420
421 if (physical_device->rad_info.chip_class >= GFX10_3) {
422 radeon_set_context_reg(cs, R_028750_SX_PS_DOWNCONVERT_CONTROL_GFX103, 0xff);
423 }
424
425 if (physical_device->rad_info.chip_class == GFX10) {
426 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
427 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
428 radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
429 }
430
431 /* TODO: For culling, replace 128 with 256. */
432 radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC,
433 S_030980_OVERSUB_EN(physical_device->rad_info.use_late_alloc) |
434 S_030980_NUM_PC_LINES(128 * physical_device->rad_info.max_se - 1));
435 }
436
437 if (physical_device->rad_info.chip_class >= GFX9) {
438 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
439 S_028B50_ACCUM_ISOLINE(40) |
440 S_028B50_ACCUM_TRI(30) |
441 S_028B50_ACCUM_QUAD(24) |
442 S_028B50_DONUT_SPLIT(24) |
443 S_028B50_TRAP_SPLIT(6));
444 } else if (physical_device->rad_info.chip_class >= GFX8) {
445 uint32_t vgt_tess_distribution;
446
447 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
448 S_028B50_ACCUM_TRI(11) |
449 S_028B50_ACCUM_QUAD(11) |
450 S_028B50_DONUT_SPLIT(16);
451
452 if (physical_device->rad_info.family == CHIP_FIJI ||
453 physical_device->rad_info.family >= CHIP_POLARIS10)
454 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
455
456 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
457 vgt_tess_distribution);
458 } else if (!has_clear_state) {
459 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
460 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
461 }
462
463 if (device->border_color_data.bo) {
464 uint64_t border_color_va = radv_buffer_get_va(device->border_color_data.bo);
465
466 radeon_set_context_reg(cs, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
467 if (physical_device->rad_info.chip_class >= GFX7) {
468 radeon_set_context_reg(cs, R_028084_TA_BC_BASE_ADDR_HI,
469 S_028084_ADDRESS(border_color_va >> 40));
470 }
471 }
472
473 if (physical_device->rad_info.chip_class >= GFX9) {
474 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
475 S_028C48_MAX_ALLOC_COUNT(physical_device->rad_info.pbb_max_alloc_count - 1) |
476 S_028C48_MAX_PRIM_PER_BATCH(1023));
477 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
478 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
479 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
480 }
481
482 unsigned tmp = (unsigned)(1.0 * 8.0);
483 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
484 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
485 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
486 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
487 S_028A04_MAX_SIZE(radv_pack_float_12p4(8191.875/2)));
488
489 if (!has_clear_state) {
490 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
491 S_028004_ZPASS_INCREMENT_DISABLE(1));
492 }
493
494 /* Enable the Polaris small primitive filter control.
495 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
496 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
497 * and AMDVLK doesn't have a workaround as well.
498 */
499 if (physical_device->rad_info.family >= CHIP_POLARIS10) {
500 unsigned small_prim_filter_cntl =
501 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
502 /* Workaround for a hw line bug. */
503 S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12);
504
505 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
506 small_prim_filter_cntl);
507 }
508
509 radeon_set_context_reg(cs, R_0286D4_SPI_INTERP_CONTROL_0,
510 S_0286D4_FLAT_SHADE_ENA(1) |
511 S_0286D4_PNT_SPRITE_ENA(1) |
512 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
513 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
514 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
515 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
516 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
517
518 radeon_set_context_reg(cs, R_028BE4_PA_SU_VTX_CNTL,
519 S_028BE4_PIX_CENTER(1) |
520 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
521 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
522
523 radeon_set_context_reg(cs, R_028818_PA_CL_VTE_CNTL,
524 S_028818_VTX_W0_FMT(1) |
525 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
526 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
527 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
528
529 si_emit_compute(physical_device, cs);
530 }
531
532 void
533 cik_create_gfx_config(struct radv_device *device)
534 {
535 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX);
536 if (!cs)
537 return;
538
539 si_emit_graphics(device, cs);
540
541 while (cs->cdw & 7) {
542 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
543 radeon_emit(cs, PKT2_NOP_PAD);
544 else
545 radeon_emit(cs, PKT3_NOP_PAD);
546 }
547
548 device->gfx_init = device->ws->buffer_create(device->ws,
549 cs->cdw * 4, 4096,
550 RADEON_DOMAIN_GTT,
551 RADEON_FLAG_CPU_ACCESS|
552 RADEON_FLAG_NO_INTERPROCESS_SHARING |
553 RADEON_FLAG_READ_ONLY |
554 RADEON_FLAG_GTT_WC,
555 RADV_BO_PRIORITY_CS);
556 if (!device->gfx_init)
557 goto fail;
558
559 void *map = device->ws->buffer_map(device->gfx_init);
560 if (!map) {
561 device->ws->buffer_destroy(device->gfx_init);
562 device->gfx_init = NULL;
563 goto fail;
564 }
565 memcpy(map, cs->buf, cs->cdw * 4);
566
567 device->ws->buffer_unmap(device->gfx_init);
568 device->gfx_init_size_dw = cs->cdw;
569 fail:
570 device->ws->cs_destroy(cs);
571 }
572
573 static void
574 get_viewport_xform(const VkViewport *viewport,
575 float scale[3], float translate[3])
576 {
577 float x = viewport->x;
578 float y = viewport->y;
579 float half_width = 0.5f * viewport->width;
580 float half_height = 0.5f * viewport->height;
581 double n = viewport->minDepth;
582 double f = viewport->maxDepth;
583
584 scale[0] = half_width;
585 translate[0] = half_width + x;
586 scale[1] = half_height;
587 translate[1] = half_height + y;
588
589 scale[2] = (f - n);
590 translate[2] = n;
591 }
592
593 void
594 si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
595 int count, const VkViewport *viewports)
596 {
597 int i;
598
599 assert(count);
600 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
601 first_vp * 4 * 6, count * 6);
602
603 for (i = 0; i < count; i++) {
604 float scale[3], translate[3];
605
606
607 get_viewport_xform(&viewports[i], scale, translate);
608 radeon_emit(cs, fui(scale[0]));
609 radeon_emit(cs, fui(translate[0]));
610 radeon_emit(cs, fui(scale[1]));
611 radeon_emit(cs, fui(translate[1]));
612 radeon_emit(cs, fui(scale[2]));
613 radeon_emit(cs, fui(translate[2]));
614 }
615
616 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
617 first_vp * 4 * 2, count * 2);
618 for (i = 0; i < count; i++) {
619 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
620 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
621 radeon_emit(cs, fui(zmin));
622 radeon_emit(cs, fui(zmax));
623 }
624 }
625
626 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
627 {
628 float scale[3], translate[3];
629 VkRect2D rect;
630
631 get_viewport_xform(viewport, scale, translate);
632
633 rect.offset.x = translate[0] - fabsf(scale[0]);
634 rect.offset.y = translate[1] - fabsf(scale[1]);
635 rect.extent.width = ceilf(translate[0] + fabsf(scale[0])) - rect.offset.x;
636 rect.extent.height = ceilf(translate[1] + fabsf(scale[1])) - rect.offset.y;
637
638 return rect;
639 }
640
641 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
642 VkRect2D ret;
643 ret.offset.x = MAX2(a->offset.x, b->offset.x);
644 ret.offset.y = MAX2(a->offset.y, b->offset.y);
645 ret.extent.width = MIN2(a->offset.x + a->extent.width,
646 b->offset.x + b->extent.width) - ret.offset.x;
647 ret.extent.height = MIN2(a->offset.y + a->extent.height,
648 b->offset.y + b->extent.height) - ret.offset.y;
649 return ret;
650 }
651
652 void
653 si_write_scissors(struct radeon_cmdbuf *cs, int first,
654 int count, const VkRect2D *scissors,
655 const VkViewport *viewports, bool can_use_guardband)
656 {
657 int i;
658 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
659 const float max_range = 32767.0f;
660 if (!count)
661 return;
662
663 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
664 for (i = 0; i < count; i++) {
665 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
666 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
667
668 get_viewport_xform(viewports + i, scale, translate);
669 scale[0] = fabsf(scale[0]);
670 scale[1] = fabsf(scale[1]);
671
672 if (scale[0] < 0.5)
673 scale[0] = 0.5;
674 if (scale[1] < 0.5)
675 scale[1] = 0.5;
676
677 guardband_x = MIN2(guardband_x, (max_range - fabsf(translate[0])) / scale[0]);
678 guardband_y = MIN2(guardband_y, (max_range - fabsf(translate[1])) / scale[1]);
679
680 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
681 S_028250_TL_Y(scissor.offset.y) |
682 S_028250_WINDOW_OFFSET_DISABLE(1));
683 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
684 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
685 }
686 if (!can_use_guardband) {
687 guardband_x = 1.0;
688 guardband_y = 1.0;
689 }
690
691 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
692 radeon_emit(cs, fui(guardband_y));
693 radeon_emit(cs, fui(1.0));
694 radeon_emit(cs, fui(guardband_x));
695 radeon_emit(cs, fui(1.0));
696 }
697
698 static inline unsigned
699 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
700 {
701 if (num == 0)
702 return 0;
703
704 if (info->incr == 0)
705 return 0;
706
707 if (num < info->min)
708 return 0;
709
710 return 1 + ((num - info->min) / info->incr);
711 }
712
713 static const struct radv_prim_vertex_count prim_size_table[] = {
714 [V_008958_DI_PT_NONE] = {0, 0},
715 [V_008958_DI_PT_POINTLIST] = {1, 1},
716 [V_008958_DI_PT_LINELIST] = {2, 2},
717 [V_008958_DI_PT_LINESTRIP] = {2, 1},
718 [V_008958_DI_PT_TRILIST] = {3, 3},
719 [V_008958_DI_PT_TRIFAN] = {3, 1},
720 [V_008958_DI_PT_TRISTRIP] = {3, 1},
721 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
722 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
723 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
724 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
725 [V_008958_DI_PT_RECTLIST] = {3, 3},
726 [V_008958_DI_PT_LINELOOP] = {2, 1},
727 [V_008958_DI_PT_POLYGON] = {3, 1},
728 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
729 };
730
731 uint32_t
732 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
733 bool instanced_draw, bool indirect_draw,
734 bool count_from_stream_output,
735 uint32_t draw_vertex_count,
736 unsigned topology)
737 {
738 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
739 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
740 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
741 const unsigned max_primgroup_in_wave = 2;
742 /* SWITCH_ON_EOP(0) is always preferable. */
743 bool wd_switch_on_eop = false;
744 bool ia_switch_on_eop = false;
745 bool ia_switch_on_eoi = false;
746 bool partial_vs_wave = false;
747 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave;
748 bool multi_instances_smaller_than_primgroup;
749 struct radv_prim_vertex_count prim_vertex_count = prim_size_table[topology];
750
751 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline)) {
752 if (topology == V_008958_DI_PT_PATCH) {
753 prim_vertex_count.min = cmd_buffer->state.pipeline->graphics.tess_patch_control_points;
754 prim_vertex_count.incr = 1;
755 }
756 }
757
758 multi_instances_smaller_than_primgroup = indirect_draw;
759 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
760 uint32_t num_prims = radv_prims_for_vertices(&prim_vertex_count, draw_vertex_count);
761 if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size)
762 multi_instances_smaller_than_primgroup = true;
763 }
764
765 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
766 partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
767
768 if (chip_class >= GFX7) {
769 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
770 * 4 shader engines. Set 1 to pass the assertion below.
771 * The other cases are hardware requirements. */
772 if (cmd_buffer->device->physical_device->rad_info.max_se < 4 ||
773 topology == V_008958_DI_PT_POLYGON ||
774 topology == V_008958_DI_PT_LINELOOP ||
775 topology == V_008958_DI_PT_TRIFAN ||
776 topology == V_008958_DI_PT_TRISTRIP_ADJ ||
777 (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
778 (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
779 (topology != V_008958_DI_PT_POINTLIST &&
780 topology != V_008958_DI_PT_LINESTRIP))))
781 wd_switch_on_eop = true;
782
783 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
784 * We don't know that for indirect drawing, so treat it as
785 * always problematic. */
786 if (family == CHIP_HAWAII &&
787 (instanced_draw || indirect_draw))
788 wd_switch_on_eop = true;
789
790 /* Performance recommendation for 4 SE Gfx7-8 parts if
791 * instances are smaller than a primgroup.
792 * Assume indirect draws always use small instances.
793 * This is needed for good VS wave utilization.
794 */
795 if (chip_class <= GFX8 &&
796 info->max_se == 4 &&
797 multi_instances_smaller_than_primgroup)
798 wd_switch_on_eop = true;
799
800 /* Required on GFX7 and later. */
801 if (info->max_se > 2 && !wd_switch_on_eop)
802 ia_switch_on_eoi = true;
803
804 /* Required by Hawaii and, for some special cases, by GFX8. */
805 if (ia_switch_on_eoi &&
806 (family == CHIP_HAWAII ||
807 (chip_class == GFX8 &&
808 /* max primgroup in wave is always 2 - leave this for documentation */
809 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
810 partial_vs_wave = true;
811
812 /* Instancing bug on Bonaire. */
813 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
814 (instanced_draw || indirect_draw))
815 partial_vs_wave = true;
816
817 /* Hardware requirement when drawing primitives from a stream
818 * output buffer.
819 */
820 if (count_from_stream_output)
821 wd_switch_on_eop = true;
822
823 /* If the WD switch is false, the IA switch must be false too. */
824 assert(wd_switch_on_eop || !ia_switch_on_eop);
825 }
826 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
827 if (chip_class <= GFX8 && ia_switch_on_eoi)
828 partial_es_wave = true;
829
830 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
831 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
832 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
833 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
834 */
835 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
836 bool set_vgt_flush = indirect_draw;
837 if (!set_vgt_flush && instanced_draw) {
838 uint32_t num_prims = radv_prims_for_vertices(&prim_vertex_count, draw_vertex_count);
839 if (num_prims <= 1)
840 set_vgt_flush = true;
841 }
842 if (set_vgt_flush)
843 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
844 }
845 }
846
847 /* Workaround for a VGT hang when strip primitive types are used with
848 * primitive restart.
849 */
850 if (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
851 (topology == V_008958_DI_PT_LINESTRIP ||
852 topology == V_008958_DI_PT_TRISTRIP ||
853 topology == V_008958_DI_PT_LINESTRIP_ADJ ||
854 topology == V_008958_DI_PT_TRISTRIP_ADJ)) {
855 partial_vs_wave = true;
856 }
857
858 return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base |
859 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
860 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
861 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
862 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
863 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= GFX7 ? wd_switch_on_eop : 0);
864
865 }
866
867 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
868 enum chip_class chip_class,
869 bool is_mec,
870 unsigned event, unsigned event_flags,
871 unsigned dst_sel, unsigned data_sel,
872 uint64_t va,
873 uint32_t new_fence,
874 uint64_t gfx9_eop_bug_va)
875 {
876 unsigned op = EVENT_TYPE(event) |
877 EVENT_INDEX(event == V_028A90_CS_DONE ||
878 event == V_028A90_PS_DONE ? 6 : 5) |
879 event_flags;
880 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
881 unsigned sel = EOP_DST_SEL(dst_sel) |
882 EOP_DATA_SEL(data_sel);
883
884 /* Wait for write confirmation before writing data, but don't send
885 * an interrupt. */
886 if (data_sel != EOP_DATA_SEL_DISCARD)
887 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
888
889 if (chip_class >= GFX9 || is_gfx8_mec) {
890 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
891 * counters) must immediately precede every timestamp event to
892 * prevent a GPU hang on GFX9.
893 */
894 if (chip_class == GFX9 && !is_mec) {
895 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
896 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
897 radeon_emit(cs, gfx9_eop_bug_va);
898 radeon_emit(cs, gfx9_eop_bug_va >> 32);
899 }
900
901 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false));
902 radeon_emit(cs, op);
903 radeon_emit(cs, sel);
904 radeon_emit(cs, va); /* address lo */
905 radeon_emit(cs, va >> 32); /* address hi */
906 radeon_emit(cs, new_fence); /* immediate data lo */
907 radeon_emit(cs, 0); /* immediate data hi */
908 if (!is_gfx8_mec)
909 radeon_emit(cs, 0); /* unused */
910 } else {
911 if (chip_class == GFX7 ||
912 chip_class == GFX8) {
913 /* Two EOP events are required to make all engines go idle
914 * (and optional cache flushes executed) before the timestamp
915 * is written.
916 */
917 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
918 radeon_emit(cs, op);
919 radeon_emit(cs, va);
920 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
921 radeon_emit(cs, 0); /* immediate data */
922 radeon_emit(cs, 0); /* unused */
923 }
924
925 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
926 radeon_emit(cs, op);
927 radeon_emit(cs, va);
928 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
929 radeon_emit(cs, new_fence); /* immediate data */
930 radeon_emit(cs, 0); /* unused */
931 }
932 }
933
934 void
935 radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
936 uint32_t ref, uint32_t mask)
937 {
938 assert(op == WAIT_REG_MEM_EQUAL ||
939 op == WAIT_REG_MEM_NOT_EQUAL ||
940 op == WAIT_REG_MEM_GREATER_OR_EQUAL);
941
942 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false));
943 radeon_emit(cs, op | WAIT_REG_MEM_MEM_SPACE(1));
944 radeon_emit(cs, va);
945 radeon_emit(cs, va >> 32);
946 radeon_emit(cs, ref); /* reference value */
947 radeon_emit(cs, mask); /* mask */
948 radeon_emit(cs, 4); /* poll interval */
949 }
950
951 static void
952 si_emit_acquire_mem(struct radeon_cmdbuf *cs,
953 bool is_mec,
954 bool is_gfx9,
955 unsigned cp_coher_cntl)
956 {
957 if (is_mec || is_gfx9) {
958 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
959 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) |
960 PKT3_SHADER_TYPE_S(is_mec));
961 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
962 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
963 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
964 radeon_emit(cs, 0); /* CP_COHER_BASE */
965 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
966 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
967 } else {
968 /* ACQUIRE_MEM is only required on a compute ring. */
969 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false));
970 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
971 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
972 radeon_emit(cs, 0); /* CP_COHER_BASE */
973 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
974 }
975 }
976
977 static void
978 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
979 enum chip_class chip_class,
980 uint32_t *flush_cnt,
981 uint64_t flush_va,
982 bool is_mec,
983 enum radv_cmd_flush_bits flush_bits,
984 uint64_t gfx9_eop_bug_va)
985 {
986 uint32_t gcr_cntl = 0;
987 unsigned cb_db_event = 0;
988
989 /* We don't need these. */
990 assert(!(flush_bits & (RADV_CMD_FLAG_VGT_STREAMOUT_SYNC)));
991
992 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
993 gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
994 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE) {
995 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
996 * to FORWARD when both L1 and L2 are written out (WB or INV).
997 */
998 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
999 }
1000 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE)
1001 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
1002 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
1003 /* Writeback and invalidate everything in L2. */
1004 gcr_cntl |= S_586_GL2_INV(1) | S_586_GL2_WB(1) |
1005 S_586_GLM_INV(1) | S_586_GLM_WB(1);
1006 } else if (flush_bits & RADV_CMD_FLAG_WB_L2) {
1007 /* Writeback but do not invalidate.
1008 * GLM doesn't support WB alone. If WB is set, INV must be set too.
1009 */
1010 gcr_cntl |= S_586_GL2_WB(1) |
1011 S_586_GLM_WB(1) | S_586_GLM_INV(1);
1012 }
1013
1014 /* TODO: Implement this new flag for GFX9+.
1015 else if (flush_bits & RADV_CMD_FLAG_INV_L2_METADATA)
1016 gcr_cntl |= S_586_GLM_INV(1) | S_586_GLM_WB(1);
1017 */
1018
1019 if (flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
1020 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_CB_META */
1021 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
1022 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
1023 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1024 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
1025 EVENT_INDEX(0));
1026 }
1027
1028 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_DB_META ? */
1029 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
1030 /* Flush HTILE. Will wait for idle later. */
1031 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1032 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) |
1033 EVENT_INDEX(0));
1034 }
1035
1036 /* First flush CB/DB, then L1/L2. */
1037 gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
1038
1039 if ((flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) ==
1040 (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
1041 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1042 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
1043 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1044 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
1045 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1046 } else {
1047 assert(0);
1048 }
1049 } else {
1050 /* Wait for graphics shaders to go idle if requested. */
1051 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
1052 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1053 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1054 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
1055 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1056 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1057 }
1058 }
1059
1060 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
1061 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1062 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
1063 }
1064
1065 if (cb_db_event) {
1066 /* CB/DB flush and invalidate (or possibly just a wait for a
1067 * meta flush) via RELEASE_MEM.
1068 *
1069 * Combine this with other cache flushes when possible; this
1070 * requires affected shaders to be idle, so do it after the
1071 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
1072 * implied).
1073 */
1074 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
1075 unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
1076 unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
1077 unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
1078 unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
1079 assert(G_586_GL2_US(gcr_cntl) == 0);
1080 assert(G_586_GL2_RANGE(gcr_cntl) == 0);
1081 assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
1082 unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
1083 unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
1084 unsigned gcr_seq = G_586_SEQ(gcr_cntl);
1085
1086 gcr_cntl &= C_586_GLM_WB &
1087 C_586_GLM_INV &
1088 C_586_GLV_INV &
1089 C_586_GL1_INV &
1090 C_586_GL2_INV &
1091 C_586_GL2_WB; /* keep SEQ */
1092
1093 assert(flush_cnt);
1094 (*flush_cnt)++;
1095
1096 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event,
1097 S_490_GLM_WB(glm_wb) |
1098 S_490_GLM_INV(glm_inv) |
1099 S_490_GLV_INV(glv_inv) |
1100 S_490_GL1_INV(gl1_inv) |
1101 S_490_GL2_INV(gl2_inv) |
1102 S_490_GL2_WB(gl2_wb) |
1103 S_490_SEQ(gcr_seq),
1104 EOP_DST_SEL_MEM,
1105 EOP_DATA_SEL_VALUE_32BIT,
1106 flush_va, *flush_cnt,
1107 gfx9_eop_bug_va);
1108
1109 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
1110 *flush_cnt, 0xffffffff);
1111 }
1112
1113 /* VGT state sync */
1114 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1115 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1116 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1117 }
1118
1119 /* Ignore fields that only modify the behavior of other fields. */
1120 if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
1121 /* Flush caches and wait for the caches to assert idle.
1122 * The cache flush is executed in the ME, but the PFP waits
1123 * for completion.
1124 */
1125 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
1126 radeon_emit(cs, 0); /* CP_COHER_CNTL */
1127 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1128 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1129 radeon_emit(cs, 0); /* CP_COHER_BASE */
1130 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1131 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1132 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
1133 } else if ((cb_db_event ||
1134 (flush_bits & (RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1135 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1136 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)))
1137 && !is_mec) {
1138 /* We need to ensure that PFP waits as well. */
1139 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1140 radeon_emit(cs, 0);
1141 }
1142
1143 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1144 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1145 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1146 EVENT_INDEX(0));
1147 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1148 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1149 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1150 EVENT_INDEX(0));
1151 }
1152 }
1153
1154 void
1155 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1156 enum chip_class chip_class,
1157 uint32_t *flush_cnt,
1158 uint64_t flush_va,
1159 bool is_mec,
1160 enum radv_cmd_flush_bits flush_bits,
1161 uint64_t gfx9_eop_bug_va)
1162 {
1163 unsigned cp_coher_cntl = 0;
1164 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1165 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
1166
1167 if (chip_class >= GFX10) {
1168 /* GFX10 cache flush handling is quite different. */
1169 gfx10_cs_emit_cache_flush(cs, chip_class, flush_cnt, flush_va,
1170 is_mec, flush_bits, gfx9_eop_bug_va);
1171 return;
1172 }
1173
1174 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
1175 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1176 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE)
1177 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1178
1179 if (chip_class <= GFX8) {
1180 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
1181 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
1182 S_0085F0_CB0_DEST_BASE_ENA(1) |
1183 S_0085F0_CB1_DEST_BASE_ENA(1) |
1184 S_0085F0_CB2_DEST_BASE_ENA(1) |
1185 S_0085F0_CB3_DEST_BASE_ENA(1) |
1186 S_0085F0_CB4_DEST_BASE_ENA(1) |
1187 S_0085F0_CB5_DEST_BASE_ENA(1) |
1188 S_0085F0_CB6_DEST_BASE_ENA(1) |
1189 S_0085F0_CB7_DEST_BASE_ENA(1);
1190
1191 /* Necessary for DCC */
1192 if (chip_class >= GFX8) {
1193 si_cs_emit_write_event_eop(cs,
1194 chip_class,
1195 is_mec,
1196 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
1197 0,
1198 EOP_DST_SEL_MEM,
1199 EOP_DATA_SEL_DISCARD,
1200 0, 0,
1201 gfx9_eop_bug_va);
1202 }
1203 }
1204 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
1205 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
1206 S_0085F0_DB_DEST_BASE_ENA(1);
1207 }
1208 }
1209
1210 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
1211 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1212 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1213 }
1214
1215 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
1216 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1217 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1218 }
1219
1220 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
1221 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1222 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1223 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
1224 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1225 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1226 }
1227
1228 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
1229 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1230 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1231 }
1232
1233 if (chip_class == GFX9 && flush_cb_db) {
1234 unsigned cb_db_event, tc_flags;
1235
1236 /* Set the CB/DB flush event. */
1237 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1238
1239 /* These are the only allowed combinations. If you need to
1240 * do multiple operations at once, do them separately.
1241 * All operations that invalidate L2 also seem to invalidate
1242 * metadata. Volatile (VOL) and WC flushes are not listed here.
1243 *
1244 * TC | TC_WB = writeback & invalidate L2 & L1
1245 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1246 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1247 * TC | TC_NC = invalidate L2 for MTYPE == NC
1248 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1249 * TCL1 = invalidate L1
1250 */
1251 tc_flags = EVENT_TC_ACTION_ENA |
1252 EVENT_TC_MD_ACTION_ENA;
1253
1254 /* Ideally flush TC together with CB/DB. */
1255 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
1256 /* Writeback and invalidate everything in L2 & L1. */
1257 tc_flags = EVENT_TC_ACTION_ENA |
1258 EVENT_TC_WB_ACTION_ENA;
1259
1260
1261 /* Clear the flags. */
1262 flush_bits &= ~(RADV_CMD_FLAG_INV_L2 |
1263 RADV_CMD_FLAG_WB_L2 |
1264 RADV_CMD_FLAG_INV_VCACHE);
1265 }
1266 assert(flush_cnt);
1267 (*flush_cnt)++;
1268
1269 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags,
1270 EOP_DST_SEL_MEM,
1271 EOP_DATA_SEL_VALUE_32BIT,
1272 flush_va, *flush_cnt,
1273 gfx9_eop_bug_va);
1274 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
1275 *flush_cnt, 0xffffffff);
1276 }
1277
1278 /* VGT state sync */
1279 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1280 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1281 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1282 }
1283
1284 /* VGT streamout state sync */
1285 if (flush_bits & RADV_CMD_FLAG_VGT_STREAMOUT_SYNC) {
1286 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1287 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1288 }
1289
1290 /* Make sure ME is idle (it executes most packets) before continuing.
1291 * This prevents read-after-write hazards between PFP and ME.
1292 */
1293 if ((cp_coher_cntl ||
1294 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1295 RADV_CMD_FLAG_INV_VCACHE |
1296 RADV_CMD_FLAG_INV_L2 |
1297 RADV_CMD_FLAG_WB_L2))) &&
1298 !is_mec) {
1299 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1300 radeon_emit(cs, 0);
1301 }
1302
1303 if ((flush_bits & RADV_CMD_FLAG_INV_L2) ||
1304 (chip_class <= GFX7 && (flush_bits & RADV_CMD_FLAG_WB_L2))) {
1305 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9,
1306 cp_coher_cntl |
1307 S_0085F0_TC_ACTION_ENA(1) |
1308 S_0085F0_TCL1_ACTION_ENA(1) |
1309 S_0301F0_TC_WB_ACTION_ENA(chip_class >= GFX8));
1310 cp_coher_cntl = 0;
1311 } else {
1312 if(flush_bits & RADV_CMD_FLAG_WB_L2) {
1313 /* WB = write-back
1314 * NC = apply to non-coherent MTYPEs
1315 * (i.e. MTYPE <= 1, which is what we use everywhere)
1316 *
1317 * WB doesn't work without NC.
1318 */
1319 si_emit_acquire_mem(cs, is_mec,
1320 chip_class == GFX9,
1321 cp_coher_cntl |
1322 S_0301F0_TC_WB_ACTION_ENA(1) |
1323 S_0301F0_TC_NC_ACTION_ENA(1));
1324 cp_coher_cntl = 0;
1325 }
1326 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE) {
1327 si_emit_acquire_mem(cs, is_mec,
1328 chip_class == GFX9,
1329 cp_coher_cntl |
1330 S_0085F0_TCL1_ACTION_ENA(1));
1331 cp_coher_cntl = 0;
1332 }
1333 }
1334
1335 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1336 * Therefore, it should be last. Done in PFP.
1337 */
1338 if (cp_coher_cntl)
1339 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9, cp_coher_cntl);
1340
1341 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1342 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1343 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1344 EVENT_INDEX(0));
1345 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1346 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1347 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1348 EVENT_INDEX(0));
1349 }
1350 }
1351
1352 void
1353 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
1354 {
1355 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1356
1357 if (is_compute)
1358 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1359 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1360 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1361 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1362 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1363 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1364 RADV_CMD_FLAG_VGT_FLUSH |
1365 RADV_CMD_FLAG_START_PIPELINE_STATS |
1366 RADV_CMD_FLAG_STOP_PIPELINE_STATS);
1367
1368 if (!cmd_buffer->state.flush_bits)
1369 return;
1370
1371 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1372
1373 si_cs_emit_cache_flush(cmd_buffer->cs,
1374 cmd_buffer->device->physical_device->rad_info.chip_class,
1375 &cmd_buffer->gfx9_fence_idx,
1376 cmd_buffer->gfx9_fence_va,
1377 radv_cmd_buffer_uses_mec(cmd_buffer),
1378 cmd_buffer->state.flush_bits,
1379 cmd_buffer->gfx9_eop_bug_va);
1380
1381
1382 if (unlikely(cmd_buffer->device->trace_bo))
1383 radv_cmd_buffer_trace_emit(cmd_buffer);
1384
1385 /* Clear the caches that have been flushed to avoid syncing too much
1386 * when there is some pending active queries.
1387 */
1388 cmd_buffer->active_query_flush_bits &= ~cmd_buffer->state.flush_bits;
1389
1390 cmd_buffer->state.flush_bits = 0;
1391
1392 /* If the driver used a compute shader for resetting a query pool, it
1393 * should be finished at this point.
1394 */
1395 cmd_buffer->pending_reset_query = false;
1396 }
1397
1398 /* sets the CP predication state using a boolean stored at va */
1399 void
1400 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1401 bool draw_visible, uint64_t va)
1402 {
1403 uint32_t op = 0;
1404
1405 if (va) {
1406 op = PRED_OP(PREDICATION_OP_BOOL64);
1407
1408 /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
1409 * zero, all rendering commands are discarded. Otherwise, they
1410 * are discarded if the value is non zero.
1411 */
1412 op |= draw_visible ? PREDICATION_DRAW_VISIBLE :
1413 PREDICATION_DRAW_NOT_VISIBLE;
1414 }
1415 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1416 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1417 radeon_emit(cmd_buffer->cs, op);
1418 radeon_emit(cmd_buffer->cs, va);
1419 radeon_emit(cmd_buffer->cs, va >> 32);
1420 } else {
1421 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1422 radeon_emit(cmd_buffer->cs, va);
1423 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1424 }
1425 }
1426
1427 /* Set this if you want the 3D engine to wait until CP DMA is done.
1428 * It should be set on the last CP DMA packet. */
1429 #define CP_DMA_SYNC (1 << 0)
1430
1431 /* Set this if the source data was used as a destination in a previous CP DMA
1432 * packet. It's for preventing a read-after-write (RAW) hazard between two
1433 * CP DMA packets. */
1434 #define CP_DMA_RAW_WAIT (1 << 1)
1435 #define CP_DMA_USE_L2 (1 << 2)
1436 #define CP_DMA_CLEAR (1 << 3)
1437
1438 /* Alignment for optimal performance. */
1439 #define SI_CPDMA_ALIGNMENT 32
1440
1441 /* The max number of bytes that can be copied per packet. */
1442 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1443 {
1444 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1445 S_414_BYTE_COUNT_GFX9(~0u) :
1446 S_414_BYTE_COUNT_GFX6(~0u);
1447
1448 /* make it aligned for optimal performance */
1449 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1450 }
1451
1452 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1453 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1454 * clear value.
1455 */
1456 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1457 uint64_t dst_va, uint64_t src_va,
1458 unsigned size, unsigned flags)
1459 {
1460 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1461 uint32_t header = 0, command = 0;
1462
1463 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1464
1465 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1466 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1467 command |= S_414_BYTE_COUNT_GFX9(size);
1468 else
1469 command |= S_414_BYTE_COUNT_GFX6(size);
1470
1471 /* Sync flags. */
1472 if (flags & CP_DMA_SYNC)
1473 header |= S_411_CP_SYNC(1);
1474 else {
1475 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1476 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1477 else
1478 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1479 }
1480
1481 if (flags & CP_DMA_RAW_WAIT)
1482 command |= S_414_RAW_WAIT(1);
1483
1484 /* Src and dst flags. */
1485 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1486 !(flags & CP_DMA_CLEAR) &&
1487 src_va == dst_va)
1488 header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
1489 else if (flags & CP_DMA_USE_L2)
1490 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
1491
1492 if (flags & CP_DMA_CLEAR)
1493 header |= S_411_SRC_SEL(V_411_DATA);
1494 else if (flags & CP_DMA_USE_L2)
1495 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1496
1497 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1498 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1499 radeon_emit(cs, header);
1500 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1501 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1502 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1503 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1504 radeon_emit(cs, command);
1505 } else {
1506 assert(!(flags & CP_DMA_USE_L2));
1507 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1508 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1509 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1510 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1511 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1512 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1513 radeon_emit(cs, command);
1514 }
1515
1516 /* CP DMA is executed in ME, but index buffers are read by PFP.
1517 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1518 * indices. If we wanted to execute CP DMA in PFP, this packet
1519 * should precede it.
1520 */
1521 if (flags & CP_DMA_SYNC) {
1522 if (cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1523 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1524 radeon_emit(cs, 0);
1525 }
1526
1527 /* CP will see the sync flag and wait for all DMAs to complete. */
1528 cmd_buffer->state.dma_is_busy = false;
1529 }
1530
1531 if (unlikely(cmd_buffer->device->trace_bo))
1532 radv_cmd_buffer_trace_emit(cmd_buffer);
1533 }
1534
1535 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1536 unsigned size)
1537 {
1538 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1539 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1540
1541 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1542 aligned_size, CP_DMA_USE_L2);
1543 }
1544
1545 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1546 uint64_t remaining_size, unsigned *flags)
1547 {
1548
1549 /* Flush the caches for the first copy only.
1550 * Also wait for the previous CP DMA operations.
1551 */
1552 if (cmd_buffer->state.flush_bits) {
1553 si_emit_cache_flush(cmd_buffer);
1554 *flags |= CP_DMA_RAW_WAIT;
1555 }
1556
1557 /* Do the synchronization after the last dma, so that all data
1558 * is written to memory.
1559 */
1560 if (byte_count == remaining_size)
1561 *flags |= CP_DMA_SYNC;
1562 }
1563
1564 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1565 {
1566 uint64_t va;
1567 uint32_t offset;
1568 unsigned dma_flags = 0;
1569 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1570 void *ptr;
1571
1572 assert(size < SI_CPDMA_ALIGNMENT);
1573
1574 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1575
1576 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1577 va += offset;
1578
1579 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1580
1581 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1582 dma_flags);
1583 }
1584
1585 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1586 uint64_t src_va, uint64_t dest_va,
1587 uint64_t size)
1588 {
1589 uint64_t main_src_va, main_dest_va;
1590 uint64_t skipped_size = 0, realign_size = 0;
1591
1592 /* Assume that we are not going to sync after the last DMA operation. */
1593 cmd_buffer->state.dma_is_busy = true;
1594
1595 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1596 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1597 /* If the size is not aligned, we must add a dummy copy at the end
1598 * just to align the internal counter. Otherwise, the DMA engine
1599 * would slow down by an order of magnitude for following copies.
1600 */
1601 if (size % SI_CPDMA_ALIGNMENT)
1602 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1603
1604 /* If the copy begins unaligned, we must start copying from the next
1605 * aligned block and the skipped part should be copied after everything
1606 * else has been copied. Only the src alignment matters, not dst.
1607 */
1608 if (src_va % SI_CPDMA_ALIGNMENT) {
1609 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1610 /* The main part will be skipped if the size is too small. */
1611 skipped_size = MIN2(skipped_size, size);
1612 size -= skipped_size;
1613 }
1614 }
1615 main_src_va = src_va + skipped_size;
1616 main_dest_va = dest_va + skipped_size;
1617
1618 while (size) {
1619 unsigned dma_flags = 0;
1620 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1621
1622 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1623 /* DMA operations via L2 are coherent and faster.
1624 * TODO: GFX7-GFX9 should also support this but it
1625 * requires tests/benchmarks.
1626 */
1627 dma_flags |= CP_DMA_USE_L2;
1628 }
1629
1630 si_cp_dma_prepare(cmd_buffer, byte_count,
1631 size + skipped_size + realign_size,
1632 &dma_flags);
1633
1634 dma_flags &= ~CP_DMA_SYNC;
1635
1636 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1637 byte_count, dma_flags);
1638
1639 size -= byte_count;
1640 main_src_va += byte_count;
1641 main_dest_va += byte_count;
1642 }
1643
1644 if (skipped_size) {
1645 unsigned dma_flags = 0;
1646
1647 si_cp_dma_prepare(cmd_buffer, skipped_size,
1648 size + skipped_size + realign_size,
1649 &dma_flags);
1650
1651 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1652 skipped_size, dma_flags);
1653 }
1654 if (realign_size)
1655 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1656 }
1657
1658 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1659 uint64_t size, unsigned value)
1660 {
1661
1662 if (!size)
1663 return;
1664
1665 assert(va % 4 == 0 && size % 4 == 0);
1666
1667 /* Assume that we are not going to sync after the last DMA operation. */
1668 cmd_buffer->state.dma_is_busy = true;
1669
1670 while (size) {
1671 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1672 unsigned dma_flags = CP_DMA_CLEAR;
1673
1674 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1675 /* DMA operations via L2 are coherent and faster.
1676 * TODO: GFX7-GFX9 should also support this but it
1677 * requires tests/benchmarks.
1678 */
1679 dma_flags |= CP_DMA_USE_L2;
1680 }
1681
1682 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1683
1684 /* Emit the clear packet. */
1685 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1686 dma_flags);
1687
1688 size -= byte_count;
1689 va += byte_count;
1690 }
1691 }
1692
1693 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
1694 {
1695 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX7)
1696 return;
1697
1698 if (!cmd_buffer->state.dma_is_busy)
1699 return;
1700
1701 /* Issue a dummy DMA that copies zero bytes.
1702 *
1703 * The DMA engine will see that there's no work to do and skip this
1704 * DMA request, however, the CP will see the sync flag and still wait
1705 * for all DMAs to complete.
1706 */
1707 si_emit_cp_dma(cmd_buffer, 0, 0, 0, CP_DMA_SYNC);
1708
1709 cmd_buffer->state.dma_is_busy = false;
1710 }
1711
1712 /* For MSAA sample positions. */
1713 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1714 ((((unsigned)(s0x) & 0xf) << 0) | (((unsigned)(s0y) & 0xf) << 4) | \
1715 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1716 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1717 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1718
1719 /* For obtaining location coordinates from registers */
1720 #define SEXT4(x) ((int)((x) | ((x) & 0x8 ? 0xfffffff0 : 0)))
1721 #define GET_SFIELD(reg, index) SEXT4(((reg) >> ((index) * 4)) & 0xf)
1722 #define GET_SX(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2)
1723 #define GET_SY(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2 + 1)
1724
1725 /* 1x MSAA */
1726 static const uint32_t sample_locs_1x =
1727 FILL_SREG(0, 0, 0, 0, 0, 0, 0, 0);
1728 static const unsigned max_dist_1x = 0;
1729 static const uint64_t centroid_priority_1x = 0x0000000000000000ull;
1730
1731 /* 2xMSAA */
1732 static const uint32_t sample_locs_2x =
1733 FILL_SREG(4,4, -4, -4, 0, 0, 0, 0);
1734 static const unsigned max_dist_2x = 4;
1735 static const uint64_t centroid_priority_2x = 0x1010101010101010ull;
1736
1737 /* 4xMSAA */
1738 static const uint32_t sample_locs_4x =
1739 FILL_SREG(-2,-6, 6, -2, -6, 2, 2, 6);
1740 static const unsigned max_dist_4x = 6;
1741 static const uint64_t centroid_priority_4x = 0x3210321032103210ull;
1742
1743 /* 8xMSAA */
1744 static const uint32_t sample_locs_8x[] = {
1745 FILL_SREG( 1,-3, -1, 3, 5, 1, -3,-5),
1746 FILL_SREG(-5, 5, -7,-1, 3, 7, 7,-7),
1747 /* The following are unused by hardware, but we emit them to IBs
1748 * instead of multiple SET_CONTEXT_REG packets. */
1749 0,
1750 0,
1751 };
1752 static const unsigned max_dist_8x = 7;
1753 static const uint64_t centroid_priority_8x = 0x7654321076543210ull;
1754
1755 unsigned radv_get_default_max_sample_dist(int log_samples)
1756 {
1757 unsigned max_dist[] = {
1758 max_dist_1x,
1759 max_dist_2x,
1760 max_dist_4x,
1761 max_dist_8x,
1762 };
1763 return max_dist[log_samples];
1764 }
1765
1766 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples)
1767 {
1768 switch (nr_samples) {
1769 default:
1770 case 1:
1771 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1772 radeon_emit(cs, (uint32_t)centroid_priority_1x);
1773 radeon_emit(cs, centroid_priority_1x >> 32);
1774 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_1x);
1775 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_1x);
1776 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_1x);
1777 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_1x);
1778 break;
1779 case 2:
1780 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1781 radeon_emit(cs, (uint32_t)centroid_priority_2x);
1782 radeon_emit(cs, centroid_priority_2x >> 32);
1783 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x);
1784 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x);
1785 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x);
1786 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x);
1787 break;
1788 case 4:
1789 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1790 radeon_emit(cs, (uint32_t)centroid_priority_4x);
1791 radeon_emit(cs, centroid_priority_4x >> 32);
1792 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x);
1793 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x);
1794 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x);
1795 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x);
1796 break;
1797 case 8:
1798 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1799 radeon_emit(cs, (uint32_t)centroid_priority_8x);
1800 radeon_emit(cs, centroid_priority_8x >> 32);
1801 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1802 radeon_emit_array(cs, sample_locs_8x, 4);
1803 radeon_emit_array(cs, sample_locs_8x, 4);
1804 radeon_emit_array(cs, sample_locs_8x, 4);
1805 radeon_emit_array(cs, sample_locs_8x, 2);
1806 break;
1807 }
1808 }
1809
1810 static void radv_get_sample_position(struct radv_device *device,
1811 unsigned sample_count,
1812 unsigned sample_index, float *out_value)
1813 {
1814 const uint32_t *sample_locs;
1815
1816 switch (sample_count) {
1817 case 1:
1818 default:
1819 sample_locs = &sample_locs_1x;
1820 break;
1821 case 2:
1822 sample_locs = &sample_locs_2x;
1823 break;
1824 case 4:
1825 sample_locs = &sample_locs_4x;
1826 break;
1827 case 8:
1828 sample_locs = sample_locs_8x;
1829 break;
1830 }
1831
1832 out_value[0] = (GET_SX(sample_locs, sample_index) + 8) / 16.0f;
1833 out_value[1] = (GET_SY(sample_locs, sample_index) + 8) / 16.0f;
1834 }
1835
1836 void radv_device_init_msaa(struct radv_device *device)
1837 {
1838 int i;
1839
1840 radv_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1841
1842 for (i = 0; i < 2; i++)
1843 radv_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1844 for (i = 0; i < 4; i++)
1845 radv_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1846 for (i = 0; i < 8; i++)
1847 radv_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1848 }