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radv: Add Vega M support.
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for SI */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "gfx9d.h"
35 #include "radv_util.h"
36 #include "main/macros.h"
37
38 static void
39 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
40 struct radeon_winsys_cs *cs,
41 unsigned raster_config,
42 unsigned raster_config_1)
43 {
44 unsigned sh_per_se = MAX2(physical_device->rad_info.max_sh_per_se, 1);
45 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
46 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
47 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
48 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
49 unsigned rb_per_se = num_rb / num_se;
50 unsigned se_mask[4];
51 unsigned se;
52
53 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
54 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
55 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
56 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
57
58 assert(num_se == 1 || num_se == 2 || num_se == 4);
59 assert(sh_per_se == 1 || sh_per_se == 2);
60 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
61
62 /* XXX: I can't figure out what the *_XSEL and *_YSEL
63 * fields are for, so I'm leaving them as their default
64 * values. */
65
66 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
67 (!se_mask[2] && !se_mask[3]))) {
68 raster_config_1 &= C_028354_SE_PAIR_MAP;
69
70 if (!se_mask[0] && !se_mask[1]) {
71 raster_config_1 |=
72 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
73 } else {
74 raster_config_1 |=
75 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
76 }
77 }
78
79 for (se = 0; se < num_se; se++) {
80 unsigned raster_config_se = raster_config;
81 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
82 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
83 int idx = (se / 2) * 2;
84
85 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
86 raster_config_se &= C_028350_SE_MAP;
87
88 if (!se_mask[idx]) {
89 raster_config_se |=
90 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
91 } else {
92 raster_config_se |=
93 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
94 }
95 }
96
97 pkr0_mask &= rb_mask;
98 pkr1_mask &= rb_mask;
99 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
100 raster_config_se &= C_028350_PKR_MAP;
101
102 if (!pkr0_mask) {
103 raster_config_se |=
104 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
105 } else {
106 raster_config_se |=
107 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
108 }
109 }
110
111 if (rb_per_se >= 2) {
112 unsigned rb0_mask = 1 << (se * rb_per_se);
113 unsigned rb1_mask = rb0_mask << 1;
114
115 rb0_mask &= rb_mask;
116 rb1_mask &= rb_mask;
117 if (!rb0_mask || !rb1_mask) {
118 raster_config_se &= C_028350_RB_MAP_PKR0;
119
120 if (!rb0_mask) {
121 raster_config_se |=
122 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
123 } else {
124 raster_config_se |=
125 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
126 }
127 }
128
129 if (rb_per_se > 2) {
130 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
131 rb1_mask = rb0_mask << 1;
132 rb0_mask &= rb_mask;
133 rb1_mask &= rb_mask;
134 if (!rb0_mask || !rb1_mask) {
135 raster_config_se &= C_028350_RB_MAP_PKR1;
136
137 if (!rb0_mask) {
138 raster_config_se |=
139 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
140 } else {
141 raster_config_se |=
142 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
143 }
144 }
145 }
146 }
147
148 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
149 if (physical_device->rad_info.chip_class < CIK)
150 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
151 S_00802C_SE_INDEX(se) |
152 S_00802C_SH_BROADCAST_WRITES(1) |
153 S_00802C_INSTANCE_BROADCAST_WRITES(1));
154 else
155 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
156 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
157 S_030800_INSTANCE_BROADCAST_WRITES(1));
158 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
159 if (physical_device->rad_info.chip_class >= CIK)
160 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
161 }
162
163 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
164 if (physical_device->rad_info.chip_class < CIK)
165 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
166 S_00802C_SE_BROADCAST_WRITES(1) |
167 S_00802C_SH_BROADCAST_WRITES(1) |
168 S_00802C_INSTANCE_BROADCAST_WRITES(1));
169 else
170 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
171 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
172 S_030800_INSTANCE_BROADCAST_WRITES(1));
173 }
174
175 static void
176 si_emit_compute(struct radv_physical_device *physical_device,
177 struct radeon_winsys_cs *cs)
178 {
179 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
180 radeon_emit(cs, 0);
181 radeon_emit(cs, 0);
182 radeon_emit(cs, 0);
183
184 radeon_set_sh_reg_seq(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
185 S_00B854_WAVES_PER_SH(0x3));
186 radeon_emit(cs, 0);
187 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
188 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
189 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
190
191 if (physical_device->rad_info.chip_class >= CIK) {
192 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
193 radeon_set_sh_reg_seq(cs,
194 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
195 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
196 S_00B864_SH1_CU_EN(0xffff));
197 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
198 S_00B868_SH1_CU_EN(0xffff));
199 }
200
201 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
202 * and is now per pipe, so it should be handled in the
203 * kernel if we want to use something other than the default value,
204 * which is now 0x22f.
205 */
206 if (physical_device->rad_info.chip_class <= SI) {
207 /* XXX: This should be:
208 * (number of compute units) * 4 * (waves per simd) - 1 */
209
210 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
211 0x190 /* Default value */);
212 }
213 }
214
215 void
216 si_init_compute(struct radv_cmd_buffer *cmd_buffer)
217 {
218 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
219 si_emit_compute(physical_device, cmd_buffer->cs);
220 }
221
222 /* 12.4 fixed-point */
223 static unsigned radv_pack_float_12p4(float x)
224 {
225 return x <= 0 ? 0 :
226 x >= 4096 ? 0xffff : x * 16;
227 }
228
229 static void
230 si_set_raster_config(struct radv_physical_device *physical_device,
231 struct radeon_winsys_cs *cs)
232 {
233 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
234 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
235 unsigned raster_config, raster_config_1;
236
237 switch (physical_device->rad_info.family) {
238 case CHIP_TAHITI:
239 case CHIP_PITCAIRN:
240 raster_config = 0x2a00126a;
241 raster_config_1 = 0x00000000;
242 break;
243 case CHIP_VERDE:
244 raster_config = 0x0000124a;
245 raster_config_1 = 0x00000000;
246 break;
247 case CHIP_OLAND:
248 raster_config = 0x00000082;
249 raster_config_1 = 0x00000000;
250 break;
251 case CHIP_HAINAN:
252 raster_config = 0x00000000;
253 raster_config_1 = 0x00000000;
254 break;
255 case CHIP_BONAIRE:
256 raster_config = 0x16000012;
257 raster_config_1 = 0x00000000;
258 break;
259 case CHIP_HAWAII:
260 raster_config = 0x3a00161a;
261 raster_config_1 = 0x0000002e;
262 break;
263 case CHIP_FIJI:
264 if (physical_device->rad_info.cik_macrotile_mode_array[0] == 0x000000e8) {
265 /* old kernels with old tiling config */
266 raster_config = 0x16000012;
267 raster_config_1 = 0x0000002a;
268 } else {
269 raster_config = 0x3a00161a;
270 raster_config_1 = 0x0000002e;
271 }
272 break;
273 case CHIP_POLARIS10:
274 raster_config = 0x16000012;
275 raster_config_1 = 0x0000002a;
276 break;
277 case CHIP_POLARIS11:
278 case CHIP_POLARIS12:
279 raster_config = 0x16000012;
280 raster_config_1 = 0x00000000;
281 break;
282 case CHIP_VEGAM:
283 raster_config = 0x3a00161a;
284 raster_config_1 = 0x0000002e;
285 break;
286 case CHIP_TONGA:
287 raster_config = 0x16000012;
288 raster_config_1 = 0x0000002a;
289 break;
290 case CHIP_ICELAND:
291 if (num_rb == 1)
292 raster_config = 0x00000000;
293 else
294 raster_config = 0x00000002;
295 raster_config_1 = 0x00000000;
296 break;
297 case CHIP_CARRIZO:
298 raster_config = 0x00000002;
299 raster_config_1 = 0x00000000;
300 break;
301 case CHIP_KAVERI:
302 /* KV should be 0x00000002, but that causes problems with radeon */
303 raster_config = 0x00000000; /* 0x00000002 */
304 raster_config_1 = 0x00000000;
305 break;
306 case CHIP_KABINI:
307 case CHIP_MULLINS:
308 case CHIP_STONEY:
309 raster_config = 0x00000000;
310 raster_config_1 = 0x00000000;
311 break;
312 default:
313 fprintf(stderr,
314 "radv: Unknown GPU, using 0 for raster_config\n");
315 raster_config = 0x00000000;
316 raster_config_1 = 0x00000000;
317 break;
318 }
319
320 /* Always use the default config when all backends are enabled
321 * (or when we failed to determine the enabled backends).
322 */
323 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
324 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
325 raster_config);
326 if (physical_device->rad_info.chip_class >= CIK)
327 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
328 raster_config_1);
329 } else {
330 si_write_harvested_raster_configs(physical_device, cs,
331 raster_config,
332 raster_config_1);
333 }
334 }
335
336 static void
337 si_emit_config(struct radv_physical_device *physical_device,
338 struct radeon_winsys_cs *cs)
339 {
340 int i;
341
342 /* Only SI can disable CLEAR_STATE for now. */
343 assert(physical_device->has_clear_state ||
344 physical_device->rad_info.chip_class == SI);
345
346 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
347 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
348 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
349
350 if (physical_device->has_clear_state) {
351 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
352 radeon_emit(cs, 0);
353 }
354
355 if (physical_device->rad_info.chip_class <= VI)
356 si_set_raster_config(physical_device, cs);
357
358 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
359 if (!physical_device->has_clear_state)
360 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
361
362 /* FIXME calculate these values somehow ??? */
363 if (physical_device->rad_info.chip_class <= VI) {
364 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
365 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
366 }
367
368 if (!physical_device->has_clear_state) {
369 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
370 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
371 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
372 }
373
374 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
375 if (!physical_device->has_clear_state)
376 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
377 if (physical_device->rad_info.chip_class < CIK)
378 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
379 S_008A14_CLIP_VTX_REORDER_ENA(1));
380
381 radeon_set_context_reg(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
382 radeon_set_context_reg(cs, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
383
384 if (!physical_device->has_clear_state)
385 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
386
387 /* CLEAR_STATE doesn't clear these correctly on certain generations.
388 * I don't know why. Deduced by trial and error.
389 */
390 if (physical_device->rad_info.chip_class <= CIK) {
391 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
392 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
393 S_028204_WINDOW_OFFSET_DISABLE(1));
394 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
395 S_028240_WINDOW_OFFSET_DISABLE(1));
396 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
397 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
398 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
399 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
400 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
401 }
402
403 if (!physical_device->has_clear_state) {
404 for (i = 0; i < 16; i++) {
405 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
406 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
407 }
408 }
409
410 if (!physical_device->has_clear_state) {
411 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
412 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
413 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
414 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
415 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
416 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
417 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
418 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
419 }
420
421 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
422 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
423 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
424
425 if (physical_device->rad_info.chip_class >= GFX9) {
426 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
427 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
428 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
429 } else {
430 /* These registers, when written, also overwrite the
431 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
432 * them. It would be an issue if there was another UMD
433 * changing them.
434 */
435 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
436 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
437 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
438 }
439
440 if (physical_device->rad_info.chip_class >= CIK) {
441 if (physical_device->rad_info.chip_class >= GFX9) {
442 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
443 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
444 } else {
445 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
446 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
447 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
448 S_00B41C_WAVE_LIMIT(0x3F));
449 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
450 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
451 /* If this is 0, Bonaire can hang even if GS isn't being used.
452 * Other chips are unaffected. These are suboptimal values,
453 * but we don't use on-chip GS.
454 */
455 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
456 S_028A44_ES_VERTS_PER_SUBGRP(64) |
457 S_028A44_GS_PRIMS_PER_SUBGRP(4));
458 }
459 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
460 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
461
462 if (physical_device->rad_info.num_good_compute_units /
463 (physical_device->rad_info.max_se * physical_device->rad_info.max_sh_per_se) <= 4) {
464 /* Too few available compute units per SH. Disallowing
465 * VS to run on CU0 could hurt us more than late VS
466 * allocation would help.
467 *
468 * LATE_ALLOC_VS = 2 is the highest safe number.
469 */
470 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
471 S_00B118_CU_EN(0xffff) | S_00B118_WAVE_LIMIT(0x3F) );
472 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
473 } else {
474 /* Set LATE_ALLOC_VS == 31. It should be less than
475 * the number of scratch waves. Limitations:
476 * - VS can't execute on CU0.
477 * - If HS writes outputs to LDS, LS can't execute on CU0.
478 */
479 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
480 S_00B118_CU_EN(0xfffe) | S_00B118_WAVE_LIMIT(0x3F));
481 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
482 }
483
484 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
485 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
486 }
487
488 if (physical_device->rad_info.chip_class >= VI) {
489 uint32_t vgt_tess_distribution;
490 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
491 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
492 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
493
494 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
495 S_028B50_ACCUM_TRI(11) |
496 S_028B50_ACCUM_QUAD(11) |
497 S_028B50_DONUT_SPLIT(16);
498
499 if (physical_device->rad_info.family == CHIP_FIJI ||
500 physical_device->rad_info.family >= CHIP_POLARIS10)
501 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
502
503 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
504 vgt_tess_distribution);
505 } else if (!physical_device->has_clear_state) {
506 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
507 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
508 }
509
510 if (physical_device->rad_info.chip_class >= GFX9) {
511 unsigned num_se = physical_device->rad_info.max_se;
512 unsigned pc_lines = 0;
513
514 switch (physical_device->rad_info.family) {
515 case CHIP_VEGA10:
516 case CHIP_VEGA12:
517 pc_lines = 4096;
518 break;
519 case CHIP_RAVEN:
520 pc_lines = 1024;
521 break;
522 default:
523 assert(0);
524 }
525
526 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
527 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
528 S_028C48_MAX_PRIM_PER_BATCH(1023));
529 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
530 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
531 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
532 }
533
534 unsigned tmp = (unsigned)(1.0 * 8.0);
535 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
536 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
537 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
538 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
539 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
540
541 if (!physical_device->has_clear_state) {
542 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
543 S_028004_ZPASS_INCREMENT_DISABLE(1));
544 }
545
546 /* Enable the Polaris small primitive filter control.
547 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
548 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
549 * and AMDVLK doesn't have a workaround as well.
550 */
551 if (physical_device->rad_info.family >= CHIP_POLARIS10) {
552 unsigned small_prim_filter_cntl =
553 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
554 /* Workaround for a hw line bug. */
555 S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12);
556
557 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
558 small_prim_filter_cntl);
559 }
560
561 si_emit_compute(physical_device, cs);
562 }
563
564 void si_init_config(struct radv_cmd_buffer *cmd_buffer)
565 {
566 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
567
568 si_emit_config(physical_device, cmd_buffer->cs);
569 }
570
571 void
572 cik_create_gfx_config(struct radv_device *device)
573 {
574 struct radeon_winsys_cs *cs = device->ws->cs_create(device->ws, RING_GFX);
575 if (!cs)
576 return;
577
578 si_emit_config(device->physical_device, cs);
579
580 while (cs->cdw & 7) {
581 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
582 radeon_emit(cs, 0x80000000);
583 else
584 radeon_emit(cs, 0xffff1000);
585 }
586
587 device->gfx_init = device->ws->buffer_create(device->ws,
588 cs->cdw * 4, 4096,
589 RADEON_DOMAIN_GTT,
590 RADEON_FLAG_CPU_ACCESS|
591 RADEON_FLAG_NO_INTERPROCESS_SHARING |
592 RADEON_FLAG_READ_ONLY);
593 if (!device->gfx_init)
594 goto fail;
595
596 void *map = device->ws->buffer_map(device->gfx_init);
597 if (!map) {
598 device->ws->buffer_destroy(device->gfx_init);
599 device->gfx_init = NULL;
600 goto fail;
601 }
602 memcpy(map, cs->buf, cs->cdw * 4);
603
604 device->ws->buffer_unmap(device->gfx_init);
605 device->gfx_init_size_dw = cs->cdw;
606 fail:
607 device->ws->cs_destroy(cs);
608 }
609
610 static void
611 get_viewport_xform(const VkViewport *viewport,
612 float scale[3], float translate[3])
613 {
614 float x = viewport->x;
615 float y = viewport->y;
616 float half_width = 0.5f * viewport->width;
617 float half_height = 0.5f * viewport->height;
618 double n = viewport->minDepth;
619 double f = viewport->maxDepth;
620
621 scale[0] = half_width;
622 translate[0] = half_width + x;
623 scale[1] = half_height;
624 translate[1] = half_height + y;
625
626 scale[2] = (f - n);
627 translate[2] = n;
628 }
629
630 void
631 si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
632 int count, const VkViewport *viewports)
633 {
634 int i;
635
636 assert(count);
637 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
638 first_vp * 4 * 6, count * 6);
639
640 for (i = 0; i < count; i++) {
641 float scale[3], translate[3];
642
643
644 get_viewport_xform(&viewports[i], scale, translate);
645 radeon_emit(cs, fui(scale[0]));
646 radeon_emit(cs, fui(translate[0]));
647 radeon_emit(cs, fui(scale[1]));
648 radeon_emit(cs, fui(translate[1]));
649 radeon_emit(cs, fui(scale[2]));
650 radeon_emit(cs, fui(translate[2]));
651 }
652
653 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
654 first_vp * 4 * 2, count * 2);
655 for (i = 0; i < count; i++) {
656 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
657 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
658 radeon_emit(cs, fui(zmin));
659 radeon_emit(cs, fui(zmax));
660 }
661 }
662
663 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
664 {
665 float scale[3], translate[3];
666 VkRect2D rect;
667
668 get_viewport_xform(viewport, scale, translate);
669
670 rect.offset.x = translate[0] - fabs(scale[0]);
671 rect.offset.y = translate[1] - fabs(scale[1]);
672 rect.extent.width = ceilf(translate[0] + fabs(scale[0])) - rect.offset.x;
673 rect.extent.height = ceilf(translate[1] + fabs(scale[1])) - rect.offset.y;
674
675 return rect;
676 }
677
678 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
679 VkRect2D ret;
680 ret.offset.x = MAX2(a->offset.x, b->offset.x);
681 ret.offset.y = MAX2(a->offset.y, b->offset.y);
682 ret.extent.width = MIN2(a->offset.x + a->extent.width,
683 b->offset.x + b->extent.width) - ret.offset.x;
684 ret.extent.height = MIN2(a->offset.y + a->extent.height,
685 b->offset.y + b->extent.height) - ret.offset.y;
686 return ret;
687 }
688
689 void
690 si_write_scissors(struct radeon_winsys_cs *cs, int first,
691 int count, const VkRect2D *scissors,
692 const VkViewport *viewports, bool can_use_guardband)
693 {
694 int i;
695 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
696 const float max_range = 32767.0f;
697 if (!count)
698 return;
699
700 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
701 for (i = 0; i < count; i++) {
702 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
703 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
704
705 get_viewport_xform(viewports + i, scale, translate);
706 scale[0] = abs(scale[0]);
707 scale[1] = abs(scale[1]);
708
709 if (scale[0] < 0.5)
710 scale[0] = 0.5;
711 if (scale[1] < 0.5)
712 scale[1] = 0.5;
713
714 guardband_x = MIN2(guardband_x, (max_range - abs(translate[0])) / scale[0]);
715 guardband_y = MIN2(guardband_y, (max_range - abs(translate[1])) / scale[1]);
716
717 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
718 S_028250_TL_Y(scissor.offset.y) |
719 S_028250_WINDOW_OFFSET_DISABLE(1));
720 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
721 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
722 }
723 if (!can_use_guardband) {
724 guardband_x = 1.0;
725 guardband_y = 1.0;
726 }
727
728 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
729 radeon_emit(cs, fui(guardband_y));
730 radeon_emit(cs, fui(1.0));
731 radeon_emit(cs, fui(guardband_x));
732 radeon_emit(cs, fui(1.0));
733 }
734
735 static inline unsigned
736 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
737 {
738 if (num == 0)
739 return 0;
740
741 if (info->incr == 0)
742 return 0;
743
744 if (num < info->min)
745 return 0;
746
747 return 1 + ((num - info->min) / info->incr);
748 }
749
750 uint32_t
751 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
752 bool instanced_draw, bool indirect_draw,
753 uint32_t draw_vertex_count)
754 {
755 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
756 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
757 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
758 const unsigned max_primgroup_in_wave = 2;
759 /* SWITCH_ON_EOP(0) is always preferable. */
760 bool wd_switch_on_eop = false;
761 bool ia_switch_on_eop = false;
762 bool ia_switch_on_eoi = false;
763 bool partial_vs_wave = false;
764 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave;
765 bool multi_instances_smaller_than_primgroup;
766
767 multi_instances_smaller_than_primgroup = indirect_draw;
768 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
769 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
770 if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size)
771 multi_instances_smaller_than_primgroup = true;
772 }
773
774 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
775 partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
776
777 if (chip_class >= CIK) {
778 wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.wd_switch_on_eop;
779
780 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
781 * We don't know that for indirect drawing, so treat it as
782 * always problematic. */
783 if (family == CHIP_HAWAII &&
784 (instanced_draw || indirect_draw))
785 wd_switch_on_eop = true;
786
787 /* Performance recommendation for 4 SE Gfx7-8 parts if
788 * instances are smaller than a primgroup.
789 * Assume indirect draws always use small instances.
790 * This is needed for good VS wave utilization.
791 */
792 if (chip_class <= VI &&
793 info->max_se == 4 &&
794 multi_instances_smaller_than_primgroup)
795 wd_switch_on_eop = true;
796
797 /* Required on CIK and later. */
798 if (info->max_se > 2 && !wd_switch_on_eop)
799 ia_switch_on_eoi = true;
800
801 /* Required by Hawaii and, for some special cases, by VI. */
802 if (ia_switch_on_eoi &&
803 (family == CHIP_HAWAII ||
804 (chip_class == VI &&
805 /* max primgroup in wave is always 2 - leave this for documentation */
806 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
807 partial_vs_wave = true;
808
809 /* Instancing bug on Bonaire. */
810 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
811 (instanced_draw || indirect_draw))
812 partial_vs_wave = true;
813
814 /* If the WD switch is false, the IA switch must be false too. */
815 assert(wd_switch_on_eop || !ia_switch_on_eop);
816 }
817 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
818 if (chip_class <= VI && ia_switch_on_eoi)
819 partial_es_wave = true;
820
821 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
822 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
823 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
824 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
825 */
826 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
827 bool set_vgt_flush = indirect_draw;
828 if (!set_vgt_flush && instanced_draw) {
829 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
830 if (num_prims <= 1)
831 set_vgt_flush = true;
832 }
833 if (set_vgt_flush)
834 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
835 }
836 }
837
838 return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base |
839 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
840 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
841 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
842 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
843 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop : 0);
844
845 }
846
847 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
848 bool predicated,
849 enum chip_class chip_class,
850 bool is_mec,
851 unsigned event, unsigned event_flags,
852 unsigned data_sel,
853 uint64_t va,
854 uint32_t old_fence,
855 uint32_t new_fence)
856 {
857 unsigned op = EVENT_TYPE(event) |
858 EVENT_INDEX(5) |
859 event_flags;
860 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
861
862 if (chip_class >= GFX9 || is_gfx8_mec) {
863 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, predicated));
864 radeon_emit(cs, op);
865 radeon_emit(cs, EOP_DATA_SEL(data_sel));
866 radeon_emit(cs, va); /* address lo */
867 radeon_emit(cs, va >> 32); /* address hi */
868 radeon_emit(cs, new_fence); /* immediate data lo */
869 radeon_emit(cs, 0); /* immediate data hi */
870 if (!is_gfx8_mec)
871 radeon_emit(cs, 0); /* unused */
872 } else {
873 if (chip_class == CIK ||
874 chip_class == VI) {
875 /* Two EOP events are required to make all engines go idle
876 * (and optional cache flushes executed) before the timestamp
877 * is written.
878 */
879 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated));
880 radeon_emit(cs, op);
881 radeon_emit(cs, va);
882 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
883 radeon_emit(cs, old_fence); /* immediate data */
884 radeon_emit(cs, 0); /* unused */
885 }
886
887 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated));
888 radeon_emit(cs, op);
889 radeon_emit(cs, va);
890 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
891 radeon_emit(cs, new_fence); /* immediate data */
892 radeon_emit(cs, 0); /* unused */
893 }
894 }
895
896 void
897 si_emit_wait_fence(struct radeon_winsys_cs *cs,
898 bool predicated,
899 uint64_t va, uint32_t ref,
900 uint32_t mask)
901 {
902 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, predicated));
903 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
904 radeon_emit(cs, va);
905 radeon_emit(cs, va >> 32);
906 radeon_emit(cs, ref); /* reference value */
907 radeon_emit(cs, mask); /* mask */
908 radeon_emit(cs, 4); /* poll interval */
909 }
910
911 static void
912 si_emit_acquire_mem(struct radeon_winsys_cs *cs,
913 bool is_mec,
914 bool predicated,
915 bool is_gfx9,
916 unsigned cp_coher_cntl)
917 {
918 if (is_mec || is_gfx9) {
919 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
920 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, predicated) |
921 PKT3_SHADER_TYPE_S(is_mec));
922 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
923 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
924 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
925 radeon_emit(cs, 0); /* CP_COHER_BASE */
926 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
927 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
928 } else {
929 /* ACQUIRE_MEM is only required on a compute ring. */
930 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, predicated));
931 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
932 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
933 radeon_emit(cs, 0); /* CP_COHER_BASE */
934 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
935 }
936 }
937
938 void
939 si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
940 enum chip_class chip_class,
941 uint32_t *flush_cnt,
942 uint64_t flush_va,
943 bool is_mec,
944 enum radv_cmd_flush_bits flush_bits)
945 {
946 unsigned cp_coher_cntl = 0;
947 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
948 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
949
950 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
951 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
952 if (flush_bits & RADV_CMD_FLAG_INV_SMEM_L1)
953 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
954
955 if (chip_class <= VI) {
956 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
957 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
958 S_0085F0_CB0_DEST_BASE_ENA(1) |
959 S_0085F0_CB1_DEST_BASE_ENA(1) |
960 S_0085F0_CB2_DEST_BASE_ENA(1) |
961 S_0085F0_CB3_DEST_BASE_ENA(1) |
962 S_0085F0_CB4_DEST_BASE_ENA(1) |
963 S_0085F0_CB5_DEST_BASE_ENA(1) |
964 S_0085F0_CB6_DEST_BASE_ENA(1) |
965 S_0085F0_CB7_DEST_BASE_ENA(1);
966
967 /* Necessary for DCC */
968 if (chip_class >= VI) {
969 si_cs_emit_write_event_eop(cs,
970 false,
971 chip_class,
972 is_mec,
973 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
974 0, 0, 0, 0, 0);
975 }
976 }
977 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
978 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
979 S_0085F0_DB_DEST_BASE_ENA(1);
980 }
981 }
982
983 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
984 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
985 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
986 }
987
988 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
989 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
990 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
991 }
992
993 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
994 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
995 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
996 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
997 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
998 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
999 }
1000
1001 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
1002 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1003 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1004 }
1005
1006 if (chip_class >= GFX9 && flush_cb_db) {
1007 unsigned cb_db_event, tc_flags;
1008
1009 #if 0
1010 /* This breaks a bunch of:
1011 dEQP-VK.renderpass.dedicated_allocation.formats.d32_sfloat_s8_uint.input*.
1012 use the big hammer always.
1013 */
1014 /* Set the CB/DB flush event. */
1015 switch (flush_cb_db) {
1016 case RADV_CMD_FLAG_FLUSH_AND_INV_CB:
1017 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1018 break;
1019 case RADV_CMD_FLAG_FLUSH_AND_INV_DB:
1020 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1021 break;
1022 default:
1023 /* both CB & DB */
1024 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1025 }
1026 #else
1027 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1028 #endif
1029 /* These are the only allowed combinations. If you need to
1030 * do multiple operations at once, do them separately.
1031 * All operations that invalidate L2 also seem to invalidate
1032 * metadata. Volatile (VOL) and WC flushes are not listed here.
1033 *
1034 * TC | TC_WB = writeback & invalidate L2 & L1
1035 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1036 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1037 * TC | TC_NC = invalidate L2 for MTYPE == NC
1038 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1039 * TCL1 = invalidate L1
1040 */
1041 tc_flags = EVENT_TC_ACTION_ENA |
1042 EVENT_TC_MD_ACTION_ENA;
1043
1044 /* Ideally flush TC together with CB/DB. */
1045 if (flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) {
1046 /* Writeback and invalidate everything in L2 & L1. */
1047 tc_flags = EVENT_TC_ACTION_ENA |
1048 EVENT_TC_WB_ACTION_ENA;
1049
1050
1051 /* Clear the flags. */
1052 flush_bits &= ~(RADV_CMD_FLAG_INV_GLOBAL_L2 |
1053 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 |
1054 RADV_CMD_FLAG_INV_VMEM_L1);
1055 }
1056 assert(flush_cnt);
1057 uint32_t old_fence = (*flush_cnt)++;
1058
1059 si_cs_emit_write_event_eop(cs, false, chip_class, false, cb_db_event, tc_flags, 1,
1060 flush_va, old_fence, *flush_cnt);
1061 si_emit_wait_fence(cs, false, flush_va, *flush_cnt, 0xffffffff);
1062 }
1063
1064 /* VGT state sync */
1065 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1066 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1067 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1068 }
1069
1070 /* Make sure ME is idle (it executes most packets) before continuing.
1071 * This prevents read-after-write hazards between PFP and ME.
1072 */
1073 if ((cp_coher_cntl ||
1074 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1075 RADV_CMD_FLAG_INV_VMEM_L1 |
1076 RADV_CMD_FLAG_INV_GLOBAL_L2 |
1077 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) &&
1078 !is_mec) {
1079 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1080 radeon_emit(cs, 0);
1081 }
1082
1083 if ((flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) ||
1084 (chip_class <= CIK && (flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) {
1085 si_emit_acquire_mem(cs, is_mec, false, chip_class >= GFX9,
1086 cp_coher_cntl |
1087 S_0085F0_TC_ACTION_ENA(1) |
1088 S_0085F0_TCL1_ACTION_ENA(1) |
1089 S_0301F0_TC_WB_ACTION_ENA(chip_class >= VI));
1090 cp_coher_cntl = 0;
1091 } else {
1092 if(flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2) {
1093 /* WB = write-back
1094 * NC = apply to non-coherent MTYPEs
1095 * (i.e. MTYPE <= 1, which is what we use everywhere)
1096 *
1097 * WB doesn't work without NC.
1098 */
1099 si_emit_acquire_mem(cs, is_mec, false,
1100 chip_class >= GFX9,
1101 cp_coher_cntl |
1102 S_0301F0_TC_WB_ACTION_ENA(1) |
1103 S_0301F0_TC_NC_ACTION_ENA(1));
1104 cp_coher_cntl = 0;
1105 }
1106 if (flush_bits & RADV_CMD_FLAG_INV_VMEM_L1) {
1107 si_emit_acquire_mem(cs, is_mec,
1108 false, chip_class >= GFX9,
1109 cp_coher_cntl |
1110 S_0085F0_TCL1_ACTION_ENA(1));
1111 cp_coher_cntl = 0;
1112 }
1113 }
1114
1115 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1116 * Therefore, it should be last. Done in PFP.
1117 */
1118 if (cp_coher_cntl)
1119 si_emit_acquire_mem(cs, is_mec, false, chip_class >= GFX9, cp_coher_cntl);
1120 }
1121
1122 void
1123 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
1124 {
1125 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1126
1127 if (is_compute)
1128 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1129 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1130 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1131 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1132 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1133 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1134 RADV_CMD_FLAG_VGT_FLUSH);
1135
1136 if (!cmd_buffer->state.flush_bits)
1137 return;
1138
1139 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
1140 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1141
1142 uint32_t *ptr = NULL;
1143 uint64_t va = 0;
1144 if (chip_class == GFX9) {
1145 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) + cmd_buffer->gfx9_fence_offset;
1146 ptr = &cmd_buffer->gfx9_fence_idx;
1147 }
1148 si_cs_emit_cache_flush(cmd_buffer->cs,
1149 cmd_buffer->device->physical_device->rad_info.chip_class,
1150 ptr, va,
1151 radv_cmd_buffer_uses_mec(cmd_buffer),
1152 cmd_buffer->state.flush_bits);
1153
1154
1155 if (unlikely(cmd_buffer->device->trace_bo))
1156 radv_cmd_buffer_trace_emit(cmd_buffer);
1157
1158 cmd_buffer->state.flush_bits = 0;
1159 }
1160
1161 /* sets the CP predication state using a boolean stored at va */
1162 void
1163 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
1164 {
1165 uint32_t op = 0;
1166
1167 if (va)
1168 op = PRED_OP(PREDICATION_OP_BOOL64) | PREDICATION_DRAW_VISIBLE;
1169 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1170 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1171 radeon_emit(cmd_buffer->cs, op);
1172 radeon_emit(cmd_buffer->cs, va);
1173 radeon_emit(cmd_buffer->cs, va >> 32);
1174 } else {
1175 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1176 radeon_emit(cmd_buffer->cs, va);
1177 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1178 }
1179 }
1180
1181 /* Set this if you want the 3D engine to wait until CP DMA is done.
1182 * It should be set on the last CP DMA packet. */
1183 #define CP_DMA_SYNC (1 << 0)
1184
1185 /* Set this if the source data was used as a destination in a previous CP DMA
1186 * packet. It's for preventing a read-after-write (RAW) hazard between two
1187 * CP DMA packets. */
1188 #define CP_DMA_RAW_WAIT (1 << 1)
1189 #define CP_DMA_USE_L2 (1 << 2)
1190 #define CP_DMA_CLEAR (1 << 3)
1191
1192 /* Alignment for optimal performance. */
1193 #define SI_CPDMA_ALIGNMENT 32
1194
1195 /* The max number of bytes that can be copied per packet. */
1196 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1197 {
1198 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1199 S_414_BYTE_COUNT_GFX9(~0u) :
1200 S_414_BYTE_COUNT_GFX6(~0u);
1201
1202 /* make it aligned for optimal performance */
1203 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1204 }
1205
1206 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1207 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1208 * clear value.
1209 */
1210 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1211 uint64_t dst_va, uint64_t src_va,
1212 unsigned size, unsigned flags)
1213 {
1214 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1215 uint32_t header = 0, command = 0;
1216
1217 assert(size);
1218 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1219
1220 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1221 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1222 command |= S_414_BYTE_COUNT_GFX9(size);
1223 else
1224 command |= S_414_BYTE_COUNT_GFX6(size);
1225
1226 /* Sync flags. */
1227 if (flags & CP_DMA_SYNC)
1228 header |= S_411_CP_SYNC(1);
1229 else {
1230 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1231 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1232 else
1233 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1234 }
1235
1236 if (flags & CP_DMA_RAW_WAIT)
1237 command |= S_414_RAW_WAIT(1);
1238
1239 /* Src and dst flags. */
1240 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1241 !(flags & CP_DMA_CLEAR) &&
1242 src_va == dst_va)
1243 header |= S_411_DSL_SEL(V_411_NOWHERE); /* prefetch only */
1244 else if (flags & CP_DMA_USE_L2)
1245 header |= S_411_DSL_SEL(V_411_DST_ADDR_TC_L2);
1246
1247 if (flags & CP_DMA_CLEAR)
1248 header |= S_411_SRC_SEL(V_411_DATA);
1249 else if (flags & CP_DMA_USE_L2)
1250 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1251
1252 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1253 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1254 radeon_emit(cs, header);
1255 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1256 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1257 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1258 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1259 radeon_emit(cs, command);
1260 } else {
1261 assert(!(flags & CP_DMA_USE_L2));
1262 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1263 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1264 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1265 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1266 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1267 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1268 radeon_emit(cs, command);
1269 }
1270
1271 /* CP DMA is executed in ME, but index buffers are read by PFP.
1272 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1273 * indices. If we wanted to execute CP DMA in PFP, this packet
1274 * should precede it.
1275 */
1276 if ((flags & CP_DMA_SYNC) && cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1277 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1278 radeon_emit(cs, 0);
1279 }
1280
1281 if (unlikely(cmd_buffer->device->trace_bo))
1282 radv_cmd_buffer_trace_emit(cmd_buffer);
1283 }
1284
1285 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1286 unsigned size)
1287 {
1288 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1289 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1290
1291 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1292 aligned_size, CP_DMA_USE_L2);
1293 }
1294
1295 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1296 uint64_t remaining_size, unsigned *flags)
1297 {
1298
1299 /* Flush the caches for the first copy only.
1300 * Also wait for the previous CP DMA operations.
1301 */
1302 if (cmd_buffer->state.flush_bits) {
1303 si_emit_cache_flush(cmd_buffer);
1304 *flags |= CP_DMA_RAW_WAIT;
1305 }
1306
1307 /* Do the synchronization after the last dma, so that all data
1308 * is written to memory.
1309 */
1310 if (byte_count == remaining_size)
1311 *flags |= CP_DMA_SYNC;
1312 }
1313
1314 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1315 {
1316 uint64_t va;
1317 uint32_t offset;
1318 unsigned dma_flags = 0;
1319 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1320 void *ptr;
1321
1322 assert(size < SI_CPDMA_ALIGNMENT);
1323
1324 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1325
1326 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1327 va += offset;
1328
1329 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1330
1331 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1332 dma_flags);
1333 }
1334
1335 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1336 uint64_t src_va, uint64_t dest_va,
1337 uint64_t size)
1338 {
1339 uint64_t main_src_va, main_dest_va;
1340 uint64_t skipped_size = 0, realign_size = 0;
1341
1342
1343 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1344 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1345 /* If the size is not aligned, we must add a dummy copy at the end
1346 * just to align the internal counter. Otherwise, the DMA engine
1347 * would slow down by an order of magnitude for following copies.
1348 */
1349 if (size % SI_CPDMA_ALIGNMENT)
1350 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1351
1352 /* If the copy begins unaligned, we must start copying from the next
1353 * aligned block and the skipped part should be copied after everything
1354 * else has been copied. Only the src alignment matters, not dst.
1355 */
1356 if (src_va % SI_CPDMA_ALIGNMENT) {
1357 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1358 /* The main part will be skipped if the size is too small. */
1359 skipped_size = MIN2(skipped_size, size);
1360 size -= skipped_size;
1361 }
1362 }
1363 main_src_va = src_va + skipped_size;
1364 main_dest_va = dest_va + skipped_size;
1365
1366 while (size) {
1367 unsigned dma_flags = 0;
1368 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1369
1370 si_cp_dma_prepare(cmd_buffer, byte_count,
1371 size + skipped_size + realign_size,
1372 &dma_flags);
1373
1374 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1375 byte_count, dma_flags);
1376
1377 size -= byte_count;
1378 main_src_va += byte_count;
1379 main_dest_va += byte_count;
1380 }
1381
1382 if (skipped_size) {
1383 unsigned dma_flags = 0;
1384
1385 si_cp_dma_prepare(cmd_buffer, skipped_size,
1386 size + skipped_size + realign_size,
1387 &dma_flags);
1388
1389 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1390 skipped_size, dma_flags);
1391 }
1392 if (realign_size)
1393 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1394 }
1395
1396 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1397 uint64_t size, unsigned value)
1398 {
1399
1400 if (!size)
1401 return;
1402
1403 assert(va % 4 == 0 && size % 4 == 0);
1404
1405 while (size) {
1406 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1407 unsigned dma_flags = CP_DMA_CLEAR;
1408
1409 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1410
1411 /* Emit the clear packet. */
1412 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1413 dma_flags);
1414
1415 size -= byte_count;
1416 va += byte_count;
1417 }
1418 }
1419
1420 /* For MSAA sample positions. */
1421 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1422 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
1423 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1424 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1425 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1426
1427
1428 /* 2xMSAA
1429 * There are two locations (4, 4), (-4, -4). */
1430 const uint32_t eg_sample_locs_2x[4] = {
1431 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1432 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1433 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1434 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1435 };
1436 const unsigned eg_max_dist_2x = 4;
1437 /* 4xMSAA
1438 * There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
1439 const uint32_t eg_sample_locs_4x[4] = {
1440 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1441 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1442 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1443 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1444 };
1445 const unsigned eg_max_dist_4x = 6;
1446
1447 /* Cayman 8xMSAA */
1448 static const uint32_t cm_sample_locs_8x[] = {
1449 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1450 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1451 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1452 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1453 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1454 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1455 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1456 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1457 };
1458 static const unsigned cm_max_dist_8x = 8;
1459 /* Cayman 16xMSAA */
1460 static const uint32_t cm_sample_locs_16x[] = {
1461 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1462 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1463 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1464 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1465 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1466 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1467 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1468 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1469 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1470 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1471 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1472 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1473 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1474 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1475 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1476 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1477 };
1478 static const unsigned cm_max_dist_16x = 8;
1479
1480 unsigned radv_cayman_get_maxdist(int log_samples)
1481 {
1482 unsigned max_dist[] = {
1483 0,
1484 eg_max_dist_2x,
1485 eg_max_dist_4x,
1486 cm_max_dist_8x,
1487 cm_max_dist_16x
1488 };
1489 return max_dist[log_samples];
1490 }
1491
1492 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples)
1493 {
1494 switch (nr_samples) {
1495 default:
1496 case 1:
1497 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
1498 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
1499 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
1500 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
1501 break;
1502 case 2:
1503 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
1504 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
1505 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
1506 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
1507 break;
1508 case 4:
1509 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
1510 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
1511 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
1512 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
1513 break;
1514 case 8:
1515 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1516 radeon_emit(cs, cm_sample_locs_8x[0]);
1517 radeon_emit(cs, cm_sample_locs_8x[4]);
1518 radeon_emit(cs, 0);
1519 radeon_emit(cs, 0);
1520 radeon_emit(cs, cm_sample_locs_8x[1]);
1521 radeon_emit(cs, cm_sample_locs_8x[5]);
1522 radeon_emit(cs, 0);
1523 radeon_emit(cs, 0);
1524 radeon_emit(cs, cm_sample_locs_8x[2]);
1525 radeon_emit(cs, cm_sample_locs_8x[6]);
1526 radeon_emit(cs, 0);
1527 radeon_emit(cs, 0);
1528 radeon_emit(cs, cm_sample_locs_8x[3]);
1529 radeon_emit(cs, cm_sample_locs_8x[7]);
1530 break;
1531 case 16:
1532 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
1533 radeon_emit(cs, cm_sample_locs_16x[0]);
1534 radeon_emit(cs, cm_sample_locs_16x[4]);
1535 radeon_emit(cs, cm_sample_locs_16x[8]);
1536 radeon_emit(cs, cm_sample_locs_16x[12]);
1537 radeon_emit(cs, cm_sample_locs_16x[1]);
1538 radeon_emit(cs, cm_sample_locs_16x[5]);
1539 radeon_emit(cs, cm_sample_locs_16x[9]);
1540 radeon_emit(cs, cm_sample_locs_16x[13]);
1541 radeon_emit(cs, cm_sample_locs_16x[2]);
1542 radeon_emit(cs, cm_sample_locs_16x[6]);
1543 radeon_emit(cs, cm_sample_locs_16x[10]);
1544 radeon_emit(cs, cm_sample_locs_16x[14]);
1545 radeon_emit(cs, cm_sample_locs_16x[3]);
1546 radeon_emit(cs, cm_sample_locs_16x[7]);
1547 radeon_emit(cs, cm_sample_locs_16x[11]);
1548 radeon_emit(cs, cm_sample_locs_16x[15]);
1549 break;
1550 }
1551 }
1552
1553 static void radv_cayman_get_sample_position(struct radv_device *device,
1554 unsigned sample_count,
1555 unsigned sample_index, float *out_value)
1556 {
1557 int offset, index;
1558 struct {
1559 int idx:4;
1560 } val;
1561 switch (sample_count) {
1562 case 1:
1563 default:
1564 out_value[0] = out_value[1] = 0.5;
1565 break;
1566 case 2:
1567 offset = 4 * (sample_index * 2);
1568 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1569 out_value[0] = (float)(val.idx + 8) / 16.0f;
1570 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1571 out_value[1] = (float)(val.idx + 8) / 16.0f;
1572 break;
1573 case 4:
1574 offset = 4 * (sample_index * 2);
1575 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1576 out_value[0] = (float)(val.idx + 8) / 16.0f;
1577 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1578 out_value[1] = (float)(val.idx + 8) / 16.0f;
1579 break;
1580 case 8:
1581 offset = 4 * (sample_index % 4 * 2);
1582 index = (sample_index / 4) * 4;
1583 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1584 out_value[0] = (float)(val.idx + 8) / 16.0f;
1585 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1586 out_value[1] = (float)(val.idx + 8) / 16.0f;
1587 break;
1588 case 16:
1589 offset = 4 * (sample_index % 4 * 2);
1590 index = (sample_index / 4) * 4;
1591 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1592 out_value[0] = (float)(val.idx + 8) / 16.0f;
1593 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1594 out_value[1] = (float)(val.idx + 8) / 16.0f;
1595 break;
1596 }
1597 }
1598
1599 void radv_device_init_msaa(struct radv_device *device)
1600 {
1601 int i;
1602 radv_cayman_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1603
1604 for (i = 0; i < 2; i++)
1605 radv_cayman_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1606 for (i = 0; i < 4; i++)
1607 radv_cayman_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1608 for (i = 0; i < 8; i++)
1609 radv_cayman_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1610 for (i = 0; i < 16; i++)
1611 radv_cayman_get_sample_position(device, 16, i, device->sample_locations_16x[i]);
1612 }