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93f6b7a949da00606f19c99240c9cde56a774770
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for SI */
29
30 #include "radv_private.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "radv_util.h"
34 #include "main/macros.h"
35
36 #define SI_GS_PER_ES 128
37
38 static void
39 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
40 struct radeon_winsys_cs *cs,
41 unsigned raster_config,
42 unsigned raster_config_1)
43 {
44 unsigned sh_per_se = MAX2(physical_device->rad_info.max_sh_per_se, 1);
45 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
46 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
47 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
48 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
49 unsigned rb_per_se = num_rb / num_se;
50 unsigned se_mask[4];
51 unsigned se;
52
53 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
54 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
55 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
56 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
57
58 assert(num_se == 1 || num_se == 2 || num_se == 4);
59 assert(sh_per_se == 1 || sh_per_se == 2);
60 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
61
62 /* XXX: I can't figure out what the *_XSEL and *_YSEL
63 * fields are for, so I'm leaving them as their default
64 * values. */
65
66 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
67 (!se_mask[2] && !se_mask[3]))) {
68 raster_config_1 &= C_028354_SE_PAIR_MAP;
69
70 if (!se_mask[0] && !se_mask[1]) {
71 raster_config_1 |=
72 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
73 } else {
74 raster_config_1 |=
75 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
76 }
77 }
78
79 for (se = 0; se < num_se; se++) {
80 unsigned raster_config_se = raster_config;
81 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
82 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
83 int idx = (se / 2) * 2;
84
85 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
86 raster_config_se &= C_028350_SE_MAP;
87
88 if (!se_mask[idx]) {
89 raster_config_se |=
90 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
91 } else {
92 raster_config_se |=
93 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
94 }
95 }
96
97 pkr0_mask &= rb_mask;
98 pkr1_mask &= rb_mask;
99 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
100 raster_config_se &= C_028350_PKR_MAP;
101
102 if (!pkr0_mask) {
103 raster_config_se |=
104 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
105 } else {
106 raster_config_se |=
107 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
108 }
109 }
110
111 if (rb_per_se >= 2) {
112 unsigned rb0_mask = 1 << (se * rb_per_se);
113 unsigned rb1_mask = rb0_mask << 1;
114
115 rb0_mask &= rb_mask;
116 rb1_mask &= rb_mask;
117 if (!rb0_mask || !rb1_mask) {
118 raster_config_se &= C_028350_RB_MAP_PKR0;
119
120 if (!rb0_mask) {
121 raster_config_se |=
122 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
123 } else {
124 raster_config_se |=
125 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
126 }
127 }
128
129 if (rb_per_se > 2) {
130 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
131 rb1_mask = rb0_mask << 1;
132 rb0_mask &= rb_mask;
133 rb1_mask &= rb_mask;
134 if (!rb0_mask || !rb1_mask) {
135 raster_config_se &= C_028350_RB_MAP_PKR1;
136
137 if (!rb0_mask) {
138 raster_config_se |=
139 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
140 } else {
141 raster_config_se |=
142 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
143 }
144 }
145 }
146 }
147
148 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
149 if (physical_device->rad_info.chip_class < CIK)
150 radeon_set_config_reg(cs, GRBM_GFX_INDEX,
151 SE_INDEX(se) | SH_BROADCAST_WRITES |
152 INSTANCE_BROADCAST_WRITES);
153 else
154 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
155 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
156 S_030800_INSTANCE_BROADCAST_WRITES(1));
157 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
158 if (physical_device->rad_info.chip_class >= CIK)
159 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
160 }
161
162 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
163 if (physical_device->rad_info.chip_class < CIK)
164 radeon_set_config_reg(cs, GRBM_GFX_INDEX,
165 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
166 INSTANCE_BROADCAST_WRITES);
167 else
168 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
169 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
170 S_030800_INSTANCE_BROADCAST_WRITES(1));
171 }
172
173 static void
174 si_emit_compute(struct radv_physical_device *physical_device,
175 struct radeon_winsys_cs *cs)
176 {
177 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
178 radeon_emit(cs, 0);
179 radeon_emit(cs, 0);
180 radeon_emit(cs, 0);
181
182 radeon_set_sh_reg_seq(cs, R_00B854_COMPUTE_RESOURCE_LIMITS, 3);
183 radeon_emit(cs, 0);
184 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
185 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
186 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
187
188 if (physical_device->rad_info.chip_class >= CIK) {
189 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
190 radeon_set_sh_reg_seq(cs,
191 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
192 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
193 S_00B864_SH1_CU_EN(0xffff));
194 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
195 S_00B868_SH1_CU_EN(0xffff));
196 }
197
198 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
199 * and is now per pipe, so it should be handled in the
200 * kernel if we want to use something other than the default value,
201 * which is now 0x22f.
202 */
203 if (physical_device->rad_info.chip_class <= SI) {
204 /* XXX: This should be:
205 * (number of compute units) * 4 * (waves per simd) - 1 */
206
207 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
208 0x190 /* Default value */);
209 }
210 }
211
212 void
213 si_init_compute(struct radv_cmd_buffer *cmd_buffer)
214 {
215 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
216 si_emit_compute(physical_device, cmd_buffer->cs);
217 }
218
219 static void
220 si_emit_config(struct radv_physical_device *physical_device,
221 struct radeon_winsys_cs *cs)
222 {
223 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
224 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
225 unsigned raster_config, raster_config_1;
226 int i;
227
228 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
229 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
230 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
231
232 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
233 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
234
235 /* FIXME calculate these values somehow ??? */
236 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
237 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
238 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
239
240 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
241 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
242
243 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
244 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
245 if (physical_device->rad_info.chip_class < CIK)
246 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
247 S_008A14_CLIP_VTX_REORDER_ENA(1));
248
249 radeon_set_context_reg(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
250 radeon_set_context_reg(cs, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
251
252 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
253
254 for (i = 0; i < 16; i++) {
255 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
256 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
257 }
258
259 switch (physical_device->rad_info.family) {
260 case CHIP_TAHITI:
261 case CHIP_PITCAIRN:
262 raster_config = 0x2a00126a;
263 raster_config_1 = 0x00000000;
264 break;
265 case CHIP_VERDE:
266 raster_config = 0x0000124a;
267 raster_config_1 = 0x00000000;
268 break;
269 case CHIP_OLAND:
270 raster_config = 0x00000082;
271 raster_config_1 = 0x00000000;
272 break;
273 case CHIP_HAINAN:
274 raster_config = 0x00000000;
275 raster_config_1 = 0x00000000;
276 break;
277 case CHIP_BONAIRE:
278 raster_config = 0x16000012;
279 raster_config_1 = 0x00000000;
280 break;
281 case CHIP_HAWAII:
282 raster_config = 0x3a00161a;
283 raster_config_1 = 0x0000002e;
284 break;
285 case CHIP_FIJI:
286 if (physical_device->rad_info.cik_macrotile_mode_array[0] == 0x000000e8) {
287 /* old kernels with old tiling config */
288 raster_config = 0x16000012;
289 raster_config_1 = 0x0000002a;
290 } else {
291 raster_config = 0x3a00161a;
292 raster_config_1 = 0x0000002e;
293 }
294 break;
295 case CHIP_POLARIS10:
296 raster_config = 0x16000012;
297 raster_config_1 = 0x0000002a;
298 break;
299 case CHIP_POLARIS11:
300 raster_config = 0x16000012;
301 raster_config_1 = 0x00000000;
302 break;
303 case CHIP_TONGA:
304 raster_config = 0x16000012;
305 raster_config_1 = 0x0000002a;
306 break;
307 case CHIP_ICELAND:
308 if (num_rb == 1)
309 raster_config = 0x00000000;
310 else
311 raster_config = 0x00000002;
312 raster_config_1 = 0x00000000;
313 break;
314 case CHIP_CARRIZO:
315 raster_config = 0x00000002;
316 raster_config_1 = 0x00000000;
317 break;
318 case CHIP_KAVERI:
319 /* KV should be 0x00000002, but that causes problems with radeon */
320 raster_config = 0x00000000; /* 0x00000002 */
321 raster_config_1 = 0x00000000;
322 break;
323 case CHIP_KABINI:
324 case CHIP_MULLINS:
325 case CHIP_STONEY:
326 raster_config = 0x00000000;
327 raster_config_1 = 0x00000000;
328 break;
329 default:
330 fprintf(stderr,
331 "radeonsi: Unknown GPU, using 0 for raster_config\n");
332 raster_config = 0x00000000;
333 raster_config_1 = 0x00000000;
334 break;
335 }
336
337 /* Always use the default config when all backends are enabled
338 * (or when we failed to determine the enabled backends).
339 */
340 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
341 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
342 raster_config);
343 if (physical_device->rad_info.chip_class >= CIK)
344 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
345 raster_config_1);
346 } else {
347 si_write_harvested_raster_configs(physical_device, cs, raster_config, raster_config_1);
348 }
349
350 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
351 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
352 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
353 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
354 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
355 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
356 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
357
358 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
359 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
360 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
361 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
362 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
363
364 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
365 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
366 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
367 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
368 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
369 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
370
371 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
372 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
373 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
374
375 if (physical_device->rad_info.chip_class >= CIK) {
376 /* If this is 0, Bonaire can hang even if GS isn't being used.
377 * Other chips are unaffected. These are suboptimal values,
378 * but we don't use on-chip GS.
379 */
380 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
381 S_028A44_ES_VERTS_PER_SUBGRP(64) |
382 S_028A44_GS_PRIMS_PER_SUBGRP(4));
383
384 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
385 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
386 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
387 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
388
389 if (physical_device->rad_info.num_good_compute_units /
390 (physical_device->rad_info.max_se * physical_device->rad_info.max_sh_per_se) <= 4) {
391 /* Too few available compute units per SH. Disallowing
392 * VS to run on CU0 could hurt us more than late VS
393 * allocation would help.
394 *
395 * LATE_ALLOC_VS = 2 is the highest safe number.
396 */
397 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
398 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
399 } else {
400 /* Set LATE_ALLOC_VS == 31. It should be less than
401 * the number of scratch waves. Limitations:
402 * - VS can't execute on CU0.
403 * - If HS writes outputs to LDS, LS can't execute on CU0.
404 */
405 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
406 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
407 }
408
409 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
410 }
411
412 if (physical_device->rad_info.chip_class >= VI) {
413 uint32_t vgt_tess_distribution;
414 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
415 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
416 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
417 if (physical_device->rad_info.family < CHIP_POLARIS10)
418 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
419 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
420
421 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
422 S_028B50_ACCUM_TRI(11) |
423 S_028B50_ACCUM_QUAD(11) |
424 S_028B50_DONUT_SPLIT(16);
425
426 if (physical_device->rad_info.family == CHIP_FIJI ||
427 physical_device->rad_info.family >= CHIP_POLARIS10)
428 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
429
430 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
431 vgt_tess_distribution);
432 } else {
433 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
434 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
435 }
436
437 if (physical_device->rad_info.family == CHIP_STONEY)
438 radeon_set_context_reg(cs, R_028C40_PA_SC_SHADER_CONTROL, 0);
439
440 si_emit_compute(physical_device, cs);
441 }
442
443 void si_init_config(struct radv_cmd_buffer *cmd_buffer)
444 {
445 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
446
447 si_emit_config(physical_device, cmd_buffer->cs);
448 }
449
450 void
451 cik_create_gfx_config(struct radv_device *device)
452 {
453 struct radeon_winsys_cs *cs = device->ws->cs_create(device->ws, RING_GFX);
454 if (!cs)
455 return;
456
457 si_emit_config(device->physical_device, cs);
458
459 while (cs->cdw & 7) {
460 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
461 radeon_emit(cs, 0x80000000);
462 else
463 radeon_emit(cs, 0xffff1000);
464 }
465
466 device->gfx_init = device->ws->buffer_create(device->ws,
467 cs->cdw * 4, 4096,
468 RADEON_DOMAIN_GTT,
469 RADEON_FLAG_CPU_ACCESS);
470 if (!device->gfx_init)
471 goto fail;
472
473 void *map = device->ws->buffer_map(device->gfx_init);
474 if (!map) {
475 device->ws->buffer_destroy(device->gfx_init);
476 device->gfx_init = NULL;
477 goto fail;
478 }
479 memcpy(map, cs->buf, cs->cdw * 4);
480
481 device->ws->buffer_unmap(device->gfx_init);
482 device->gfx_init_size_dw = cs->cdw;
483 fail:
484 device->ws->cs_destroy(cs);
485 }
486
487 static void
488 get_viewport_xform(const VkViewport *viewport,
489 float scale[3], float translate[3])
490 {
491 float x = viewport->x;
492 float y = viewport->y;
493 float half_width = 0.5f * viewport->width;
494 float half_height = 0.5f * viewport->height;
495 double n = viewport->minDepth;
496 double f = viewport->maxDepth;
497
498 scale[0] = half_width;
499 translate[0] = half_width + x;
500 scale[1] = half_height;
501 translate[1] = half_height + y;
502
503 scale[2] = (f - n);
504 translate[2] = n;
505 }
506
507 static void
508 get_viewport_xform_scissor(const VkRect2D *scissor,
509 float scale[2], float translate[2])
510 {
511 float x = scissor->offset.x;
512 float y = scissor->offset.y;
513 float half_width = 0.5f * scissor->extent.width;
514 float half_height = 0.5f * scissor->extent.height;
515
516 scale[0] = half_width;
517 translate[0] = half_width + x;
518 scale[1] = half_height;
519 translate[1] = half_height + y;
520
521 }
522
523 void
524 si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
525 int count, const VkViewport *viewports)
526 {
527 int i;
528
529 assert(count);
530 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
531 first_vp * 4 * 6, count * 6);
532
533 for (i = 0; i < count; i++) {
534 float scale[3], translate[3];
535
536
537 get_viewport_xform(&viewports[i], scale, translate);
538 radeon_emit(cs, fui(scale[0]));
539 radeon_emit(cs, fui(translate[0]));
540 radeon_emit(cs, fui(scale[1]));
541 radeon_emit(cs, fui(translate[1]));
542 radeon_emit(cs, fui(scale[2]));
543 radeon_emit(cs, fui(translate[2]));
544 }
545
546 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
547 first_vp * 4 * 2, count * 2);
548 for (i = 0; i < count; i++) {
549 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
550 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
551 radeon_emit(cs, fui(zmin));
552 radeon_emit(cs, fui(zmax));
553 }
554 }
555
556 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
557 {
558 float scale[3], translate[3];
559 VkRect2D rect;
560
561 get_viewport_xform(viewport, scale, translate);
562
563 rect.offset.x = translate[0] - abs(scale[0]);
564 rect.offset.y = translate[1] - abs(scale[1]);
565 rect.extent.width = ceilf(translate[0] + abs(scale[0])) - rect.offset.x;
566 rect.extent.height = ceilf(translate[1] + abs(scale[1])) - rect.offset.y;
567
568 return rect;
569 }
570
571 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
572 VkRect2D ret;
573 ret.offset.x = MAX2(a->offset.x, b->offset.x);
574 ret.offset.y = MAX2(a->offset.y, b->offset.y);
575 ret.extent.width = MIN2(a->offset.x + a->extent.width,
576 b->offset.x + b->extent.width) - ret.offset.x;
577 ret.extent.height = MIN2(a->offset.y + a->extent.height,
578 b->offset.y + b->extent.height) - ret.offset.y;
579 return ret;
580 }
581
582 static VkRect2D si_union_scissor(const VkRect2D *a, const VkRect2D *b) {
583 VkRect2D ret;
584 ret.offset.x = MIN2(a->offset.x, b->offset.x);
585 ret.offset.y = MIN2(a->offset.y, b->offset.y);
586 ret.extent.width = MAX2(a->offset.x + a->extent.width,
587 b->offset.x + b->extent.width) - ret.offset.x;
588 ret.extent.height = MAX2(a->offset.y + a->extent.height,
589 b->offset.y + b->extent.height) - ret.offset.y;
590 return ret;
591 }
592
593
594 void
595 si_write_scissors(struct radeon_winsys_cs *cs, int first,
596 int count, const VkRect2D *scissors,
597 const VkViewport *viewports, bool can_use_guardband)
598 {
599 int i;
600 VkRect2D merged;
601 float scale[2], translate[2], guardband_x = 1.0, guardband_y = 1.0;
602 const float max_range = 32767.0f;
603 assert(count);
604
605 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
606 for (i = 0; i < count; i++) {
607 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
608 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
609
610 if (i)
611 merged = si_union_scissor(&merged, &scissor);
612 else
613 merged = scissor;
614
615 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
616 S_028250_TL_Y(scissor.offset.y) |
617 S_028250_WINDOW_OFFSET_DISABLE(1));
618 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
619 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
620 }
621
622 get_viewport_xform_scissor(&merged, scale, translate);
623
624 if (can_use_guardband) {
625 guardband_x = (max_range - abs(translate[0])) / scale[0];
626 guardband_y = (max_range - abs(translate[1])) / scale[1];
627 }
628
629 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
630 radeon_emit(cs, fui(guardband_x));
631 radeon_emit(cs, fui(1.0));
632 radeon_emit(cs, fui(guardband_y));
633 radeon_emit(cs, fui(1.0));
634 }
635
636 static inline unsigned
637 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
638 {
639 if (num == 0)
640 return 0;
641
642 if (info->incr == 0)
643 return 0;
644
645 if (num < info->min)
646 return 0;
647
648 return 1 + ((num - info->min) / info->incr);
649 }
650
651 uint32_t
652 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
653 bool instanced_draw, bool indirect_draw,
654 uint32_t draw_vertex_count)
655 {
656 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
657 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
658 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
659 unsigned prim = cmd_buffer->state.pipeline->graphics.prim;
660 unsigned primgroup_size = 128; /* recommended without a GS */
661 unsigned max_primgroup_in_wave = 2;
662 /* SWITCH_ON_EOP(0) is always preferable. */
663 bool wd_switch_on_eop = false;
664 bool ia_switch_on_eop = false;
665 bool ia_switch_on_eoi = false;
666 bool partial_vs_wave = false;
667 bool partial_es_wave = false;
668 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
669 bool multi_instances_smaller_than_primgroup;
670
671 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
672 primgroup_size = 64; /* recommended with a GS */
673
674 multi_instances_smaller_than_primgroup = indirect_draw || (instanced_draw &&
675 num_prims < primgroup_size);
676 /* TODO TES */
677
678 /* TODO linestipple */
679
680 if (chip_class >= CIK) {
681 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
682 * 4 shader engines. Set 1 to pass the assertion below.
683 * The other cases are hardware requirements. */
684 if (info->max_se < 4 ||
685 prim == V_008958_DI_PT_POLYGON ||
686 prim == V_008958_DI_PT_LINELOOP ||
687 prim == V_008958_DI_PT_TRIFAN ||
688 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
689 (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
690 (family < CHIP_POLARIS10 ||
691 (prim != V_008958_DI_PT_POINTLIST &&
692 prim != V_008958_DI_PT_LINESTRIP &&
693 prim != V_008958_DI_PT_TRISTRIP))))
694 wd_switch_on_eop = true;
695
696 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
697 * We don't know that for indirect drawing, so treat it as
698 * always problematic. */
699 if (family == CHIP_HAWAII &&
700 (instanced_draw || indirect_draw))
701 wd_switch_on_eop = true;
702
703 /* Performance recommendation for 4 SE Gfx7-8 parts if
704 * instances are smaller than a primgroup.
705 * Assume indirect draws always use small instances.
706 * This is needed for good VS wave utilization.
707 */
708 if (chip_class <= VI &&
709 info->max_se == 4 &&
710 multi_instances_smaller_than_primgroup)
711 wd_switch_on_eop = true;
712
713 /* Required on CIK and later. */
714 if (info->max_se > 2 && !wd_switch_on_eop)
715 ia_switch_on_eoi = true;
716
717 /* Required by Hawaii and, for some special cases, by VI. */
718 if (ia_switch_on_eoi &&
719 (family == CHIP_HAWAII ||
720 (chip_class == VI &&
721 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
722 partial_vs_wave = true;
723
724 /* Instancing bug on Bonaire. */
725 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
726 (instanced_draw || indirect_draw))
727 partial_vs_wave = true;
728
729 /* If the WD switch is false, the IA switch must be false too. */
730 assert(wd_switch_on_eop || !ia_switch_on_eop);
731 }
732 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
733 if (ia_switch_on_eoi)
734 partial_es_wave = true;
735
736 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
737 /* GS requirement. */
738 if (SI_GS_PER_ES / primgroup_size >= cmd_buffer->device->gs_table_depth - 3)
739 partial_es_wave = true;
740
741 /* Hw bug with single-primitive instances and SWITCH_ON_EOI
742 * on multi-SE chips. */
743 if (info->max_se >= 2 && ia_switch_on_eoi &&
744 ((instanced_draw || indirect_draw) &&
745 num_prims <= 1))
746 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
747 }
748
749 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
750 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
751 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
752 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
753 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
754 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop : 0) |
755 S_028AA8_MAX_PRIMGRP_IN_WAVE(chip_class >= VI ?
756 max_primgroup_in_wave : 0);
757
758 }
759
760 static void
761 si_emit_acquire_mem(struct radeon_winsys_cs *cs,
762 bool is_mec,
763 unsigned cp_coher_cntl)
764 {
765 if (is_mec) {
766 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0) |
767 PKT3_SHADER_TYPE_S(1));
768 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
769 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
770 radeon_emit(cs, 0xff); /* CP_COHER_SIZE_HI */
771 radeon_emit(cs, 0); /* CP_COHER_BASE */
772 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
773 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
774 } else {
775 /* ACQUIRE_MEM is only required on a compute ring. */
776 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
777 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
778 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
779 radeon_emit(cs, 0); /* CP_COHER_BASE */
780 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
781 }
782 }
783
784 void
785 si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
786 enum chip_class chip_class,
787 bool is_mec,
788 enum radv_cmd_flush_bits flush_bits)
789 {
790 unsigned cp_coher_cntl = 0;
791
792 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
793 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
794 if (flush_bits & RADV_CMD_FLAG_INV_SMEM_L1)
795 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
796
797 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
798 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
799 S_0085F0_CB0_DEST_BASE_ENA(1) |
800 S_0085F0_CB1_DEST_BASE_ENA(1) |
801 S_0085F0_CB2_DEST_BASE_ENA(1) |
802 S_0085F0_CB3_DEST_BASE_ENA(1) |
803 S_0085F0_CB4_DEST_BASE_ENA(1) |
804 S_0085F0_CB5_DEST_BASE_ENA(1) |
805 S_0085F0_CB6_DEST_BASE_ENA(1) |
806 S_0085F0_CB7_DEST_BASE_ENA(1);
807
808 /* Necessary for DCC */
809 if (chip_class >= VI) {
810 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
811 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_DATA_TS) |
812 EVENT_INDEX(5));
813 radeon_emit(cs, 0);
814 radeon_emit(cs, 0);
815 radeon_emit(cs, 0);
816 radeon_emit(cs, 0);
817 }
818 }
819
820 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
821 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
822 S_0085F0_DB_DEST_BASE_ENA(1);
823 }
824
825 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
826 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
827 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
828 }
829
830 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
831 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
832 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
833 }
834
835 if (!(flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
836 RADV_CMD_FLAG_FLUSH_AND_INV_DB))) {
837 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
838 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
839 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
840 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
841 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
842 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
843 }
844 }
845
846 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
847 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
848 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
849 }
850
851 /* VGT state sync */
852 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
853 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
854 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
855 }
856
857 /* Make sure ME is idle (it executes most packets) before continuing.
858 * This prevents read-after-write hazards between PFP and ME.
859 */
860 if ((cp_coher_cntl || (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) &&
861 !is_mec) {
862 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
863 radeon_emit(cs, 0);
864 }
865
866 if ((flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) ||
867 (chip_class <= CIK && (flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) {
868 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
869 if (chip_class >= VI)
870 cp_coher_cntl |= S_0301F0_TC_WB_ACTION_ENA(1);
871 } else if(flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2) {
872 cp_coher_cntl |= S_0301F0_TC_WB_ACTION_ENA(1) |
873 S_0301F0_TC_NC_ACTION_ENA(1);
874
875 /* L2 writeback doesn't combine with L1 invalidate */
876 si_emit_acquire_mem(cs, is_mec, cp_coher_cntl);
877
878 cp_coher_cntl = 0;
879 }
880
881 if (flush_bits & RADV_CMD_FLAG_INV_VMEM_L1)
882 cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
883
884 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
885 * Therefore, it should be last. Done in PFP.
886 */
887 if (cp_coher_cntl)
888 si_emit_acquire_mem(cs, is_mec, cp_coher_cntl);
889 }
890
891 void
892 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
893 {
894 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
895
896 if (is_compute)
897 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
898 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
899 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
900 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
901 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
902 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
903 RADV_CMD_FLAG_VGT_FLUSH);
904
905 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
906
907 si_cs_emit_cache_flush(cmd_buffer->cs,
908 cmd_buffer->device->physical_device->rad_info.chip_class,
909 radv_cmd_buffer_uses_mec(cmd_buffer),
910 cmd_buffer->state.flush_bits);
911
912
913 if (cmd_buffer->state.flush_bits)
914 radv_cmd_buffer_trace_emit(cmd_buffer);
915 cmd_buffer->state.flush_bits = 0;
916 }
917
918
919 /* Set this if you want the 3D engine to wait until CP DMA is done.
920 * It should be set on the last CP DMA packet. */
921 #define R600_CP_DMA_SYNC (1 << 0) /* R600+ */
922
923 /* Set this if the source data was used as a destination in a previous CP DMA
924 * packet. It's for preventing a read-after-write (RAW) hazard between two
925 * CP DMA packets. */
926 #define SI_CP_DMA_RAW_WAIT (1 << 1) /* SI+ */
927 #define CIK_CP_DMA_USE_L2 (1 << 2)
928
929 /* Alignment for optimal performance. */
930 #define CP_DMA_ALIGNMENT 32
931 /* The max number of bytes to copy per packet. */
932 #define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - CP_DMA_ALIGNMENT)
933
934 static void si_emit_cp_dma_copy_buffer(struct radv_cmd_buffer *cmd_buffer,
935 uint64_t dst_va, uint64_t src_va,
936 unsigned size, unsigned flags)
937 {
938 struct radeon_winsys_cs *cs = cmd_buffer->cs;
939 uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? S_411_CP_SYNC(1) : 0;
940 uint32_t wr_confirm = !(flags & R600_CP_DMA_SYNC) ? S_414_DISABLE_WR_CONFIRM_GFX6(1) : 0;
941 uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? S_414_RAW_WAIT(1) : 0;
942 uint32_t sel = flags & CIK_CP_DMA_USE_L2 ?
943 S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2) |
944 S_411_DSL_SEL(V_411_DST_ADDR_TC_L2) : 0;
945
946 assert(size);
947 assert((size & ((1<<21)-1)) == size);
948
949 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
950
951 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
952 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
953 radeon_emit(cs, sync_flag | sel); /* CP_SYNC [31] */
954 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
955 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
956 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
957 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
958 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
959 } else {
960 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
961 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
962 radeon_emit(cs, sync_flag | ((src_va >> 32) & 0xffff)); /* CP_SYNC [31] | SRC_ADDR_HI [15:0] */
963 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
964 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
965 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
966 }
967
968 /* CP DMA is executed in ME, but index buffers are read by PFP.
969 * This ensures that ME (CP DMA) is idle before PFP starts fetching
970 * indices. If we wanted to execute CP DMA in PFP, this packet
971 * should precede it.
972 */
973 if (sync_flag && cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
974 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
975 radeon_emit(cs, 0);
976 }
977
978 radv_cmd_buffer_trace_emit(cmd_buffer);
979 }
980
981 /* Emit a CP DMA packet to clear a buffer. The size must fit in bits [20:0]. */
982 static void si_emit_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer,
983 uint64_t dst_va, unsigned size,
984 uint32_t clear_value, unsigned flags)
985 {
986 struct radeon_winsys_cs *cs = cmd_buffer->cs;
987 uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? S_411_CP_SYNC(1) : 0;
988 uint32_t wr_confirm = !(flags & R600_CP_DMA_SYNC) ? S_414_DISABLE_WR_CONFIRM_GFX6(1) : 0;
989 uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? S_414_RAW_WAIT(1) : 0;
990 uint32_t dst_sel = flags & CIK_CP_DMA_USE_L2 ? S_411_DSL_SEL(V_411_DST_ADDR_TC_L2) : 0;
991
992 assert(size);
993 assert((size & ((1<<21)-1)) == size);
994
995 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
996
997 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
998 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
999 radeon_emit(cs, sync_flag | dst_sel | S_411_SRC_SEL(V_411_DATA)); /* CP_SYNC [31] | SRC_SEL[30:29] */
1000 radeon_emit(cs, clear_value); /* DATA [31:0] */
1001 radeon_emit(cs, 0);
1002 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1003 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [15:0] */
1004 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
1005 } else {
1006 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
1007 radeon_emit(cs, clear_value); /* DATA [31:0] */
1008 radeon_emit(cs, sync_flag | S_411_SRC_SEL(V_411_DATA)); /* CP_SYNC [31] | SRC_SEL[30:29] */
1009 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1010 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1011 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
1012 }
1013
1014 /* See "copy_buffer" for explanation. */
1015 if (sync_flag && cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1016 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1017 radeon_emit(cs, 0);
1018 }
1019 radv_cmd_buffer_trace_emit(cmd_buffer);
1020 }
1021
1022 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1023 uint64_t remaining_size, unsigned *flags)
1024 {
1025
1026 /* Flush the caches for the first copy only.
1027 * Also wait for the previous CP DMA operations.
1028 */
1029 if (cmd_buffer->state.flush_bits) {
1030 si_emit_cache_flush(cmd_buffer);
1031 *flags |= SI_CP_DMA_RAW_WAIT;
1032 }
1033
1034 /* Do the synchronization after the last dma, so that all data
1035 * is written to memory.
1036 */
1037 if (byte_count == remaining_size)
1038 *flags |= R600_CP_DMA_SYNC;
1039 }
1040
1041 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1042 {
1043 uint64_t va;
1044 uint32_t offset;
1045 unsigned dma_flags = 0;
1046 unsigned buf_size = CP_DMA_ALIGNMENT * 2;
1047 void *ptr;
1048
1049 assert(size < CP_DMA_ALIGNMENT);
1050
1051 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, CP_DMA_ALIGNMENT, &offset, &ptr);
1052
1053 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1054 va += offset;
1055
1056 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1057
1058 si_emit_cp_dma_copy_buffer(cmd_buffer, va, va + CP_DMA_ALIGNMENT, size,
1059 dma_flags);
1060 }
1061
1062 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1063 uint64_t src_va, uint64_t dest_va,
1064 uint64_t size)
1065 {
1066 uint64_t main_src_va, main_dest_va;
1067 uint64_t skipped_size = 0, realign_size = 0;
1068
1069
1070 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1071 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1072 /* If the size is not aligned, we must add a dummy copy at the end
1073 * just to align the internal counter. Otherwise, the DMA engine
1074 * would slow down by an order of magnitude for following copies.
1075 */
1076 if (size % CP_DMA_ALIGNMENT)
1077 realign_size = CP_DMA_ALIGNMENT - (size % CP_DMA_ALIGNMENT);
1078
1079 /* If the copy begins unaligned, we must start copying from the next
1080 * aligned block and the skipped part should be copied after everything
1081 * else has been copied. Only the src alignment matters, not dst.
1082 */
1083 if (src_va % CP_DMA_ALIGNMENT) {
1084 skipped_size = CP_DMA_ALIGNMENT - (src_va % CP_DMA_ALIGNMENT);
1085 /* The main part will be skipped if the size is too small. */
1086 skipped_size = MIN2(skipped_size, size);
1087 size -= skipped_size;
1088 }
1089 }
1090 main_src_va = src_va + skipped_size;
1091 main_dest_va = dest_va + skipped_size;
1092
1093 while (size) {
1094 unsigned dma_flags = 0;
1095 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
1096
1097 si_cp_dma_prepare(cmd_buffer, byte_count,
1098 size + skipped_size + realign_size,
1099 &dma_flags);
1100
1101 si_emit_cp_dma_copy_buffer(cmd_buffer, main_dest_va, main_src_va,
1102 byte_count, dma_flags);
1103
1104 size -= byte_count;
1105 main_src_va += byte_count;
1106 main_dest_va += byte_count;
1107 }
1108
1109 if (skipped_size) {
1110 unsigned dma_flags = 0;
1111
1112 si_cp_dma_prepare(cmd_buffer, skipped_size,
1113 size + skipped_size + realign_size,
1114 &dma_flags);
1115
1116 si_emit_cp_dma_copy_buffer(cmd_buffer, dest_va, src_va,
1117 skipped_size, dma_flags);
1118 }
1119 if (realign_size)
1120 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1121 }
1122
1123 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1124 uint64_t size, unsigned value)
1125 {
1126
1127 if (!size)
1128 return;
1129
1130 assert(va % 4 == 0 && size % 4 == 0);
1131
1132 while (size) {
1133 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
1134 unsigned dma_flags = 0;
1135
1136 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1137
1138 /* Emit the clear packet. */
1139 si_emit_cp_dma_clear_buffer(cmd_buffer, va, byte_count, value,
1140 dma_flags);
1141
1142 size -= byte_count;
1143 va += byte_count;
1144 }
1145 }
1146
1147 /* For MSAA sample positions. */
1148 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1149 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
1150 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1151 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1152 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1153
1154
1155 /* 2xMSAA
1156 * There are two locations (4, 4), (-4, -4). */
1157 const uint32_t eg_sample_locs_2x[4] = {
1158 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1159 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1160 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1161 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1162 };
1163 const unsigned eg_max_dist_2x = 4;
1164 /* 4xMSAA
1165 * There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
1166 const uint32_t eg_sample_locs_4x[4] = {
1167 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1168 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1169 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1170 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1171 };
1172 const unsigned eg_max_dist_4x = 6;
1173
1174 /* Cayman 8xMSAA */
1175 static const uint32_t cm_sample_locs_8x[] = {
1176 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1177 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1178 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1179 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1180 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1181 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1182 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1183 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1184 };
1185 static const unsigned cm_max_dist_8x = 8;
1186 /* Cayman 16xMSAA */
1187 static const uint32_t cm_sample_locs_16x[] = {
1188 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1189 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1190 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1191 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1192 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1193 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1194 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1195 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1196 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1197 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1198 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1199 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1200 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1201 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1202 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1203 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1204 };
1205 static const unsigned cm_max_dist_16x = 8;
1206
1207 unsigned radv_cayman_get_maxdist(int log_samples)
1208 {
1209 unsigned max_dist[] = {
1210 0,
1211 eg_max_dist_2x,
1212 eg_max_dist_4x,
1213 cm_max_dist_8x,
1214 cm_max_dist_16x
1215 };
1216 return max_dist[log_samples];
1217 }
1218
1219 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples)
1220 {
1221 switch (nr_samples) {
1222 default:
1223 case 1:
1224 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
1225 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
1226 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
1227 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
1228 break;
1229 case 2:
1230 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
1231 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
1232 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
1233 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
1234 break;
1235 case 4:
1236 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
1237 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
1238 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
1239 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
1240 break;
1241 case 8:
1242 radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1243 radeon_emit(cs, cm_sample_locs_8x[0]);
1244 radeon_emit(cs, cm_sample_locs_8x[4]);
1245 radeon_emit(cs, 0);
1246 radeon_emit(cs, 0);
1247 radeon_emit(cs, cm_sample_locs_8x[1]);
1248 radeon_emit(cs, cm_sample_locs_8x[5]);
1249 radeon_emit(cs, 0);
1250 radeon_emit(cs, 0);
1251 radeon_emit(cs, cm_sample_locs_8x[2]);
1252 radeon_emit(cs, cm_sample_locs_8x[6]);
1253 radeon_emit(cs, 0);
1254 radeon_emit(cs, 0);
1255 radeon_emit(cs, cm_sample_locs_8x[3]);
1256 radeon_emit(cs, cm_sample_locs_8x[7]);
1257 break;
1258 case 16:
1259 radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
1260 radeon_emit(cs, cm_sample_locs_16x[0]);
1261 radeon_emit(cs, cm_sample_locs_16x[4]);
1262 radeon_emit(cs, cm_sample_locs_16x[8]);
1263 radeon_emit(cs, cm_sample_locs_16x[12]);
1264 radeon_emit(cs, cm_sample_locs_16x[1]);
1265 radeon_emit(cs, cm_sample_locs_16x[5]);
1266 radeon_emit(cs, cm_sample_locs_16x[9]);
1267 radeon_emit(cs, cm_sample_locs_16x[13]);
1268 radeon_emit(cs, cm_sample_locs_16x[2]);
1269 radeon_emit(cs, cm_sample_locs_16x[6]);
1270 radeon_emit(cs, cm_sample_locs_16x[10]);
1271 radeon_emit(cs, cm_sample_locs_16x[14]);
1272 radeon_emit(cs, cm_sample_locs_16x[3]);
1273 radeon_emit(cs, cm_sample_locs_16x[7]);
1274 radeon_emit(cs, cm_sample_locs_16x[11]);
1275 radeon_emit(cs, cm_sample_locs_16x[15]);
1276 break;
1277 }
1278 }
1279
1280 static void radv_cayman_get_sample_position(struct radv_device *device,
1281 unsigned sample_count,
1282 unsigned sample_index, float *out_value)
1283 {
1284 int offset, index;
1285 struct {
1286 int idx:4;
1287 } val;
1288 switch (sample_count) {
1289 case 1:
1290 default:
1291 out_value[0] = out_value[1] = 0.5;
1292 break;
1293 case 2:
1294 offset = 4 * (sample_index * 2);
1295 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1296 out_value[0] = (float)(val.idx + 8) / 16.0f;
1297 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1298 out_value[1] = (float)(val.idx + 8) / 16.0f;
1299 break;
1300 case 4:
1301 offset = 4 * (sample_index * 2);
1302 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1303 out_value[0] = (float)(val.idx + 8) / 16.0f;
1304 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1305 out_value[1] = (float)(val.idx + 8) / 16.0f;
1306 break;
1307 case 8:
1308 offset = 4 * (sample_index % 4 * 2);
1309 index = (sample_index / 4) * 4;
1310 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1311 out_value[0] = (float)(val.idx + 8) / 16.0f;
1312 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1313 out_value[1] = (float)(val.idx + 8) / 16.0f;
1314 break;
1315 case 16:
1316 offset = 4 * (sample_index % 4 * 2);
1317 index = (sample_index / 4) * 4;
1318 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1319 out_value[0] = (float)(val.idx + 8) / 16.0f;
1320 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1321 out_value[1] = (float)(val.idx + 8) / 16.0f;
1322 break;
1323 }
1324 }
1325
1326 void radv_device_init_msaa(struct radv_device *device)
1327 {
1328 int i;
1329 radv_cayman_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1330
1331 for (i = 0; i < 2; i++)
1332 radv_cayman_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1333 for (i = 0; i < 4; i++)
1334 radv_cayman_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1335 for (i = 0; i < 8; i++)
1336 radv_cayman_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1337 for (i = 0; i < 16; i++)
1338 radv_cayman_get_sample_position(device, 16, i, device->sample_locations_16x[i]);
1339 }