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a61a950de682c0008dabea01c586e9f5d62b0513
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for SI */
29
30 #include "radv_private.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "radv_util.h"
34 #include "main/macros.h"
35
36 #define SI_GS_PER_ES 128
37
38 static void
39 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
40 struct radeon_winsys_cs *cs,
41 unsigned raster_config,
42 unsigned raster_config_1)
43 {
44 unsigned sh_per_se = MAX2(physical_device->rad_info.max_sh_per_se, 1);
45 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
46 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
47 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
48 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
49 unsigned rb_per_se = num_rb / num_se;
50 unsigned se_mask[4];
51 unsigned se;
52
53 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
54 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
55 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
56 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
57
58 assert(num_se == 1 || num_se == 2 || num_se == 4);
59 assert(sh_per_se == 1 || sh_per_se == 2);
60 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
61
62 /* XXX: I can't figure out what the *_XSEL and *_YSEL
63 * fields are for, so I'm leaving them as their default
64 * values. */
65
66 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
67 (!se_mask[2] && !se_mask[3]))) {
68 raster_config_1 &= C_028354_SE_PAIR_MAP;
69
70 if (!se_mask[0] && !se_mask[1]) {
71 raster_config_1 |=
72 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
73 } else {
74 raster_config_1 |=
75 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
76 }
77 }
78
79 for (se = 0; se < num_se; se++) {
80 unsigned raster_config_se = raster_config;
81 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
82 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
83 int idx = (se / 2) * 2;
84
85 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
86 raster_config_se &= C_028350_SE_MAP;
87
88 if (!se_mask[idx]) {
89 raster_config_se |=
90 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
91 } else {
92 raster_config_se |=
93 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
94 }
95 }
96
97 pkr0_mask &= rb_mask;
98 pkr1_mask &= rb_mask;
99 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
100 raster_config_se &= C_028350_PKR_MAP;
101
102 if (!pkr0_mask) {
103 raster_config_se |=
104 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
105 } else {
106 raster_config_se |=
107 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
108 }
109 }
110
111 if (rb_per_se >= 2) {
112 unsigned rb0_mask = 1 << (se * rb_per_se);
113 unsigned rb1_mask = rb0_mask << 1;
114
115 rb0_mask &= rb_mask;
116 rb1_mask &= rb_mask;
117 if (!rb0_mask || !rb1_mask) {
118 raster_config_se &= C_028350_RB_MAP_PKR0;
119
120 if (!rb0_mask) {
121 raster_config_se |=
122 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
123 } else {
124 raster_config_se |=
125 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
126 }
127 }
128
129 if (rb_per_se > 2) {
130 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
131 rb1_mask = rb0_mask << 1;
132 rb0_mask &= rb_mask;
133 rb1_mask &= rb_mask;
134 if (!rb0_mask || !rb1_mask) {
135 raster_config_se &= C_028350_RB_MAP_PKR1;
136
137 if (!rb0_mask) {
138 raster_config_se |=
139 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
140 } else {
141 raster_config_se |=
142 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
143 }
144 }
145 }
146 }
147
148 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
149 if (physical_device->rad_info.chip_class < CIK)
150 radeon_set_config_reg(cs, GRBM_GFX_INDEX,
151 SE_INDEX(se) | SH_BROADCAST_WRITES |
152 INSTANCE_BROADCAST_WRITES);
153 else
154 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
155 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
156 S_030800_INSTANCE_BROADCAST_WRITES(1));
157 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
158 if (physical_device->rad_info.chip_class >= CIK)
159 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
160 }
161
162 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
163 if (physical_device->rad_info.chip_class < CIK)
164 radeon_set_config_reg(cs, GRBM_GFX_INDEX,
165 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
166 INSTANCE_BROADCAST_WRITES);
167 else
168 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
169 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
170 S_030800_INSTANCE_BROADCAST_WRITES(1));
171 }
172
173 static void
174 si_init_compute(struct radv_physical_device *physical_device,
175 struct radeon_winsys_cs *cs)
176 {
177 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
178 radeon_emit(cs, 0);
179 radeon_emit(cs, 0);
180 radeon_emit(cs, 0);
181
182 radeon_set_sh_reg_seq(cs, R_00B854_COMPUTE_RESOURCE_LIMITS, 3);
183 radeon_emit(cs, 0);
184 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
185 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
186 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
187
188 if (physical_device->rad_info.chip_class >= CIK) {
189 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
190 radeon_set_sh_reg_seq(cs,
191 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
192 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
193 S_00B864_SH1_CU_EN(0xffff));
194 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
195 S_00B868_SH1_CU_EN(0xffff));
196 }
197
198 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
199 * and is now per pipe, so it should be handled in the
200 * kernel if we want to use something other than the default value,
201 * which is now 0x22f.
202 */
203 if (physical_device->rad_info.chip_class <= SI) {
204 /* XXX: This should be:
205 * (number of compute units) * 4 * (waves per simd) - 1 */
206
207 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
208 0x190 /* Default value */);
209 }
210 }
211
212
213 void si_init_config(struct radv_physical_device *physical_device,
214 struct radv_cmd_buffer *cmd_buffer)
215 {
216 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
217 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
218 unsigned raster_config, raster_config_1;
219 int i;
220 struct radeon_winsys_cs *cs = cmd_buffer->cs;
221 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
222 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
223 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
224
225 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
226 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
227
228 /* FIXME calculate these values somehow ??? */
229 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
230 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
231 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
232
233 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
234 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
235
236 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
237 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
238 if (physical_device->rad_info.chip_class < CIK)
239 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
240 S_008A14_CLIP_VTX_REORDER_ENA(1));
241
242 radeon_set_context_reg(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
243 radeon_set_context_reg(cs, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
244
245 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
246
247 for (i = 0; i < 16; i++) {
248 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
249 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
250 }
251
252 switch (physical_device->rad_info.family) {
253 case CHIP_TAHITI:
254 case CHIP_PITCAIRN:
255 raster_config = 0x2a00126a;
256 raster_config_1 = 0x00000000;
257 break;
258 case CHIP_VERDE:
259 raster_config = 0x0000124a;
260 raster_config_1 = 0x00000000;
261 break;
262 case CHIP_OLAND:
263 raster_config = 0x00000082;
264 raster_config_1 = 0x00000000;
265 break;
266 case CHIP_HAINAN:
267 raster_config = 0x00000000;
268 raster_config_1 = 0x00000000;
269 break;
270 case CHIP_BONAIRE:
271 raster_config = 0x16000012;
272 raster_config_1 = 0x00000000;
273 break;
274 case CHIP_HAWAII:
275 raster_config = 0x3a00161a;
276 raster_config_1 = 0x0000002e;
277 break;
278 case CHIP_FIJI:
279 if (physical_device->rad_info.cik_macrotile_mode_array[0] == 0x000000e8) {
280 /* old kernels with old tiling config */
281 raster_config = 0x16000012;
282 raster_config_1 = 0x0000002a;
283 } else {
284 raster_config = 0x3a00161a;
285 raster_config_1 = 0x0000002e;
286 }
287 break;
288 case CHIP_POLARIS10:
289 raster_config = 0x16000012;
290 raster_config_1 = 0x0000002a;
291 break;
292 case CHIP_POLARIS11:
293 raster_config = 0x16000012;
294 raster_config_1 = 0x00000000;
295 break;
296 case CHIP_TONGA:
297 raster_config = 0x16000012;
298 raster_config_1 = 0x0000002a;
299 break;
300 case CHIP_ICELAND:
301 if (num_rb == 1)
302 raster_config = 0x00000000;
303 else
304 raster_config = 0x00000002;
305 raster_config_1 = 0x00000000;
306 break;
307 case CHIP_CARRIZO:
308 raster_config = 0x00000002;
309 raster_config_1 = 0x00000000;
310 break;
311 case CHIP_KAVERI:
312 /* KV should be 0x00000002, but that causes problems with radeon */
313 raster_config = 0x00000000; /* 0x00000002 */
314 raster_config_1 = 0x00000000;
315 break;
316 case CHIP_KABINI:
317 case CHIP_MULLINS:
318 case CHIP_STONEY:
319 raster_config = 0x00000000;
320 raster_config_1 = 0x00000000;
321 break;
322 default:
323 fprintf(stderr,
324 "radeonsi: Unknown GPU, using 0 for raster_config\n");
325 raster_config = 0x00000000;
326 raster_config_1 = 0x00000000;
327 break;
328 }
329
330 /* Always use the default config when all backends are enabled
331 * (or when we failed to determine the enabled backends).
332 */
333 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
334 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
335 raster_config);
336 if (physical_device->rad_info.chip_class >= CIK)
337 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
338 raster_config_1);
339 } else {
340 si_write_harvested_raster_configs(physical_device, cs, raster_config, raster_config_1);
341 }
342
343 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
344 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
345 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
346 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
347 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
348 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
349 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
350
351 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
352 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
353 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
354 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
355 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
356
357 radeon_set_context_reg(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0));
358 radeon_set_context_reg(cs, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0));
359 radeon_set_context_reg(cs, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0));
360 radeon_set_context_reg(cs, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0));
361
362 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
363 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
364 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
365 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
366 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
367 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
368
369 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
370 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
371 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
372
373 if (physical_device->rad_info.chip_class >= CIK) {
374 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
375 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
376 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
377
378 if (physical_device->rad_info.num_good_compute_units /
379 (physical_device->rad_info.max_se * physical_device->rad_info.max_sh_per_se) <= 4) {
380 /* Too few available compute units per SH. Disallowing
381 * VS to run on CU0 could hurt us more than late VS
382 * allocation would help.
383 *
384 * LATE_ALLOC_VS = 2 is the highest safe number.
385 */
386 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
387 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
388 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
389 } else {
390 /* Set LATE_ALLOC_VS == 31. It should be less than
391 * the number of scratch waves. Limitations:
392 * - VS can't execute on CU0.
393 * - If HS writes outputs to LDS, LS can't execute on CU0.
394 */
395 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffe));
396 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
397 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
398 }
399
400 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
401 }
402
403 if (physical_device->rad_info.chip_class >= VI) {
404 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
405 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
406 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
407 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
408 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
409 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
410 S_028B50_ACCUM_ISOLINE(32) |
411 S_028B50_ACCUM_TRI(11) |
412 S_028B50_ACCUM_QUAD(11) |
413 S_028B50_DONUT_SPLIT(16));
414 } else {
415 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
416 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
417 }
418
419 if (physical_device->rad_info.family == CHIP_STONEY)
420 radeon_set_context_reg(cs, R_028C40_PA_SC_SHADER_CONTROL, 0);
421
422 si_init_compute(physical_device, cs);
423 }
424
425 static void
426 get_viewport_xform(const VkViewport *viewport,
427 float scale[3], float translate[3])
428 {
429 float x = viewport->x;
430 float y = viewport->y;
431 float half_width = 0.5f * viewport->width;
432 float half_height = 0.5f * viewport->height;
433 double n = viewport->minDepth;
434 double f = viewport->maxDepth;
435
436 scale[0] = half_width;
437 translate[0] = half_width + x;
438 scale[1] = half_height;
439 translate[1] = half_height + y;
440
441 scale[2] = (f - n);
442 translate[2] = n;
443 }
444
445 void
446 si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
447 int count, const VkViewport *viewports)
448 {
449 int i;
450
451 if (count == 0) {
452 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
453 radeon_emit(cs, fui(1.0));
454 radeon_emit(cs, fui(0.0));
455 radeon_emit(cs, fui(1.0));
456 radeon_emit(cs, fui(0.0));
457 radeon_emit(cs, fui(1.0));
458 radeon_emit(cs, fui(0.0));
459
460 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
461 radeon_emit(cs, fui(0.0));
462 radeon_emit(cs, fui(1.0));
463
464 return;
465 }
466 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
467 first_vp * 4 * 6, count * 6);
468
469 for (i = 0; i < count; i++) {
470 float scale[3], translate[3];
471
472
473 get_viewport_xform(&viewports[i], scale, translate);
474 radeon_emit(cs, fui(scale[0]));
475 radeon_emit(cs, fui(translate[0]));
476 radeon_emit(cs, fui(scale[1]));
477 radeon_emit(cs, fui(translate[1]));
478 radeon_emit(cs, fui(scale[2]));
479 radeon_emit(cs, fui(translate[2]));
480 }
481
482 for (i = 0; i < count; i++) {
483 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
484 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
485 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
486 first_vp * 4 * 2, count * 2);
487 radeon_emit(cs, fui(zmin));
488 radeon_emit(cs, fui(zmax));
489 }
490 }
491
492 void
493 si_write_scissors(struct radeon_winsys_cs *cs, int first,
494 int count, const VkRect2D *scissors)
495 {
496 int i;
497 if (count == 0)
498 return;
499
500 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
501 for (i = 0; i < count; i++) {
502 radeon_emit(cs, S_028250_TL_X(scissors[i].offset.x) |
503 S_028250_TL_Y(scissors[i].offset.y) |
504 S_028250_WINDOW_OFFSET_DISABLE(1));
505 radeon_emit(cs, S_028254_BR_X(scissors[i].offset.x + scissors[i].extent.width) |
506 S_028254_BR_Y(scissors[i].offset.y + scissors[i].extent.height));
507 }
508 }
509
510 uint32_t
511 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer)
512 {
513 enum chip_class chip_class = cmd_buffer->device->instance->physicalDevice.rad_info.chip_class;
514 struct radeon_info *info = &cmd_buffer->device->instance->physicalDevice.rad_info;
515 unsigned prim = cmd_buffer->state.pipeline->graphics.prim;
516 unsigned primgroup_size = 128; /* recommended without a GS */
517 unsigned max_primgroup_in_wave = 2;
518 /* SWITCH_ON_EOP(0) is always preferable. */
519 bool wd_switch_on_eop = false;
520 bool ia_switch_on_eop = false;
521 bool ia_switch_on_eoi = false;
522 bool partial_vs_wave = false;
523 bool partial_es_wave = false;
524
525 /* TODO GS */
526
527 /* TODO TES */
528
529 /* TODO linestipple */
530
531 if (chip_class >= CIK) {
532 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
533 * 4 shader engines. Set 1 to pass the assertion below.
534 * The other cases are hardware requirements. */
535 if (info->max_se < 4 ||
536 prim == V_008958_DI_PT_POLYGON ||
537 prim == V_008958_DI_PT_LINELOOP ||
538 prim == V_008958_DI_PT_TRIFAN ||
539 prim == V_008958_DI_PT_TRISTRIP_ADJ)
540 // info->primitive_restart ||
541 // info->count_from_stream_output)
542 wd_switch_on_eop = true;
543
544 /* TODO HAWAII */
545
546 /* Required on CIK and later. */
547 if (info->max_se > 2 && !wd_switch_on_eop)
548 ia_switch_on_eoi = true;
549
550 /* Required by Hawaii and, for some special cases, by VI. */
551 #if 0
552 if (ia_switch_on_eoi &&
553 (sctx->b.family == CHIP_HAWAII ||
554 (sctx->b.chip_class == VI &&
555 (sctx->gs_shader.cso || max_primgroup_in_wave != 2))))
556 partial_vs_wave = true;
557 #endif
558
559 #if 0
560 /* Instancing bug on Bonaire. */
561 if (sctx->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
562 (info->indirect || info->instance_count > 1))
563 partial_vs_wave = true;
564 #endif
565 /* If the WD switch is false, the IA switch must be false too. */
566 assert(wd_switch_on_eop || !ia_switch_on_eop);
567 }
568 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
569 if (ia_switch_on_eoi)
570 partial_es_wave = true;
571
572 /* GS requirement. */
573 #if 0
574 if (SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
575 partial_es_wave = true;
576 #endif
577
578 /* Hw bug with single-primitive instances and SWITCH_ON_EOI
579 * on multi-SE chips. */
580 #if 0
581 if (sctx->b.screen->info.max_se >= 2 && ia_switch_on_eoi &&
582 (info->indirect ||
583 (info->instance_count > 1 &&
584 si_num_prims_for_vertices(info) <= 1)))
585 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
586 #endif
587 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
588 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
589 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
590 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
591 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
592 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop : 0) |
593 S_028AA8_MAX_PRIMGRP_IN_WAVE(chip_class >= VI ?
594 max_primgroup_in_wave : 0);
595
596 }
597
598 void
599 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
600 {
601 enum chip_class chip_class = cmd_buffer->device->instance->physicalDevice.rad_info.chip_class;
602 unsigned cp_coher_cntl = 0;
603
604 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
605
606 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_INV_ICACHE)
607 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
608 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_INV_SMEM_L1)
609 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
610 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_INV_VMEM_L1)
611 cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
612 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) {
613 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
614 if (chip_class >= VI)
615 cp_coher_cntl |= S_0301F0_TC_WB_ACTION_ENA(1);
616 }
617
618 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
619 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
620 S_0085F0_CB0_DEST_BASE_ENA(1) |
621 S_0085F0_CB1_DEST_BASE_ENA(1) |
622 S_0085F0_CB2_DEST_BASE_ENA(1) |
623 S_0085F0_CB3_DEST_BASE_ENA(1) |
624 S_0085F0_CB4_DEST_BASE_ENA(1) |
625 S_0085F0_CB5_DEST_BASE_ENA(1) |
626 S_0085F0_CB6_DEST_BASE_ENA(1) |
627 S_0085F0_CB7_DEST_BASE_ENA(1);
628
629 /* Necessary for DCC */
630 if (cmd_buffer->device->instance->physicalDevice.rad_info.chip_class >= VI) {
631 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
632 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_DATA_TS) |
633 EVENT_INDEX(5));
634 radeon_emit(cmd_buffer->cs, 0);
635 radeon_emit(cmd_buffer->cs, 0);
636 radeon_emit(cmd_buffer->cs, 0);
637 radeon_emit(cmd_buffer->cs, 0);
638 }
639 }
640
641 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
642 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
643 S_0085F0_DB_DEST_BASE_ENA(1);
644 }
645
646 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
647 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
648 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
649 }
650
651 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
652 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
653 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
654 }
655
656 if (!(cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
657 RADV_CMD_FLAG_FLUSH_AND_INV_DB))) {
658 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
659 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
660 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
661 } else if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
662 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
663 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
664 }
665 }
666
667 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
668 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
669 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
670 }
671
672 /* VGT state sync */
673 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
674 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
675 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
676 }
677
678 /* Make sure ME is idle (it executes most packets) before continuing.
679 * This prevents read-after-write hazards between PFP and ME.
680 */
681 if (cp_coher_cntl || (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
682 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
683 radeon_emit(cmd_buffer->cs, 0);
684 }
685
686 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
687 * Therefore, it should be last. Done in PFP.
688 */
689 if (cp_coher_cntl) {
690 /* ACQUIRE_MEM is only required on a compute ring. */
691 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
692 radeon_emit(cmd_buffer->cs, cp_coher_cntl); /* CP_COHER_CNTL */
693 radeon_emit(cmd_buffer->cs, 0xffffffff); /* CP_COHER_SIZE */
694 radeon_emit(cmd_buffer->cs, 0); /* CP_COHER_BASE */
695 radeon_emit(cmd_buffer->cs, 0x0000000A); /* POLL_INTERVAL */
696 }
697
698 cmd_buffer->state.flush_bits = 0;
699 }
700
701
702 /* Set this if you want the 3D engine to wait until CP DMA is done.
703 * It should be set on the last CP DMA packet. */
704 #define R600_CP_DMA_SYNC (1 << 0) /* R600+ */
705
706 /* Set this if the source data was used as a destination in a previous CP DMA
707 * packet. It's for preventing a read-after-write (RAW) hazard between two
708 * CP DMA packets. */
709 #define SI_CP_DMA_RAW_WAIT (1 << 1) /* SI+ */
710 #define CIK_CP_DMA_USE_L2 (1 << 2)
711
712 /* Alignment for optimal performance. */
713 #define CP_DMA_ALIGNMENT 32
714 /* The max number of bytes to copy per packet. */
715 #define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - CP_DMA_ALIGNMENT)
716
717 static void si_emit_cp_dma_copy_buffer(struct radv_cmd_buffer *cmd_buffer,
718 uint64_t dst_va, uint64_t src_va,
719 unsigned size, unsigned flags)
720 {
721 struct radeon_winsys_cs *cs = cmd_buffer->cs;
722 uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? S_411_CP_SYNC(1) : 0;
723 uint32_t wr_confirm = !(flags & R600_CP_DMA_SYNC) ? S_414_DISABLE_WR_CONFIRM(1) : 0;
724 uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? S_414_RAW_WAIT(1) : 0;
725 uint32_t sel = flags & CIK_CP_DMA_USE_L2 ?
726 S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2) |
727 S_411_DSL_SEL(V_411_DST_ADDR_TC_L2) : 0;
728
729 assert(size);
730 assert((size & ((1<<21)-1)) == size);
731
732 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
733
734 if (cmd_buffer->device->instance->physicalDevice.rad_info.chip_class >= CIK) {
735 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
736 radeon_emit(cs, sync_flag | sel); /* CP_SYNC [31] */
737 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
738 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
739 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
740 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
741 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
742 } else {
743 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
744 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
745 radeon_emit(cs, sync_flag | ((src_va >> 32) & 0xffff)); /* CP_SYNC [31] | SRC_ADDR_HI [15:0] */
746 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
747 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
748 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
749 }
750
751 /* CP DMA is executed in ME, but index buffers are read by PFP.
752 * This ensures that ME (CP DMA) is idle before PFP starts fetching
753 * indices. If we wanted to execute CP DMA in PFP, this packet
754 * should precede it.
755 */
756 if (sync_flag) {
757 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
758 radeon_emit(cs, 0);
759 }
760 }
761
762 /* Emit a CP DMA packet to clear a buffer. The size must fit in bits [20:0]. */
763 static void si_emit_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer,
764 uint64_t dst_va, unsigned size,
765 uint32_t clear_value, unsigned flags)
766 {
767 struct radeon_winsys_cs *cs = cmd_buffer->cs;
768 uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? S_411_CP_SYNC(1) : 0;
769 uint32_t wr_confirm = !(flags & R600_CP_DMA_SYNC) ? S_414_DISABLE_WR_CONFIRM(1) : 0;
770 uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? S_414_RAW_WAIT(1) : 0;
771 uint32_t dst_sel = flags & CIK_CP_DMA_USE_L2 ? S_411_DSL_SEL(V_411_DST_ADDR_TC_L2) : 0;
772
773 assert(size);
774 assert((size & ((1<<21)-1)) == size);
775
776 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
777
778 if (cmd_buffer->device->instance->physicalDevice.rad_info.chip_class >= CIK) {
779 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
780 radeon_emit(cs, sync_flag | dst_sel | S_411_SRC_SEL(V_411_DATA)); /* CP_SYNC [31] | SRC_SEL[30:29] */
781 radeon_emit(cs, clear_value); /* DATA [31:0] */
782 radeon_emit(cs, 0);
783 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
784 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [15:0] */
785 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
786 } else {
787 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
788 radeon_emit(cs, clear_value); /* DATA [31:0] */
789 radeon_emit(cs, sync_flag | S_411_SRC_SEL(V_411_DATA)); /* CP_SYNC [31] | SRC_SEL[30:29] */
790 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
791 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
792 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
793 }
794
795 /* See "copy_buffer" for explanation. */
796 if (sync_flag) {
797 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
798 radeon_emit(cs, 0);
799 }
800 }
801
802 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
803 uint64_t remaining_size, unsigned *flags)
804 {
805
806 /* Flush the caches for the first copy only.
807 * Also wait for the previous CP DMA operations.
808 */
809 if (cmd_buffer->state.flush_bits) {
810 si_emit_cache_flush(cmd_buffer);
811 *flags |= SI_CP_DMA_RAW_WAIT;
812 }
813
814 /* Do the synchronization after the last dma, so that all data
815 * is written to memory.
816 */
817 if (byte_count == remaining_size)
818 *flags |= R600_CP_DMA_SYNC;
819 }
820
821 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
822 {
823 uint64_t va;
824 uint32_t offset;
825 unsigned dma_flags = 0;
826 unsigned buf_size = CP_DMA_ALIGNMENT * 2;
827 void *ptr;
828
829 assert(size < CP_DMA_ALIGNMENT);
830
831 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, CP_DMA_ALIGNMENT, &offset, &ptr);
832
833 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
834 va += offset;
835
836 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
837
838 si_emit_cp_dma_copy_buffer(cmd_buffer, va, va + CP_DMA_ALIGNMENT, size,
839 dma_flags);
840 }
841
842 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
843 uint64_t src_va, uint64_t dest_va,
844 uint64_t size)
845 {
846 uint64_t main_src_va, main_dest_va;
847 uint64_t skipped_size = 0, realign_size = 0;
848
849
850 if (cmd_buffer->device->instance->physicalDevice.rad_info.family <= CHIP_CARRIZO ||
851 cmd_buffer->device->instance->physicalDevice.rad_info.family == CHIP_STONEY) {
852 /* If the size is not aligned, we must add a dummy copy at the end
853 * just to align the internal counter. Otherwise, the DMA engine
854 * would slow down by an order of magnitude for following copies.
855 */
856 if (size % CP_DMA_ALIGNMENT)
857 realign_size = CP_DMA_ALIGNMENT - (size % CP_DMA_ALIGNMENT);
858
859 /* If the copy begins unaligned, we must start copying from the next
860 * aligned block and the skipped part should be copied after everything
861 * else has been copied. Only the src alignment matters, not dst.
862 */
863 if (src_va % CP_DMA_ALIGNMENT) {
864 skipped_size = CP_DMA_ALIGNMENT - (src_va % CP_DMA_ALIGNMENT);
865 /* The main part will be skipped if the size is too small. */
866 skipped_size = MIN2(skipped_size, size);
867 size -= skipped_size;
868 }
869 }
870 main_src_va = src_va + skipped_size;
871 main_dest_va = dest_va + skipped_size;
872
873 while (size) {
874 unsigned dma_flags = 0;
875 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
876
877 si_cp_dma_prepare(cmd_buffer, byte_count,
878 size + skipped_size + realign_size,
879 &dma_flags);
880
881 si_emit_cp_dma_copy_buffer(cmd_buffer, main_dest_va, main_src_va,
882 byte_count, dma_flags);
883
884 size -= byte_count;
885 main_src_va += byte_count;
886 main_dest_va += byte_count;
887 }
888
889 if (skipped_size) {
890 unsigned dma_flags = 0;
891
892 si_cp_dma_prepare(cmd_buffer, skipped_size,
893 size + skipped_size + realign_size,
894 &dma_flags);
895
896 si_emit_cp_dma_copy_buffer(cmd_buffer, dest_va, src_va,
897 skipped_size, dma_flags);
898 }
899 if (realign_size)
900 si_cp_dma_realign_engine(cmd_buffer, realign_size);
901 }
902
903 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
904 uint64_t size, unsigned value)
905 {
906
907 if (!size)
908 return;
909
910 assert(va % 4 == 0 && size % 4 == 0);
911
912 while (size) {
913 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
914 unsigned dma_flags = 0;
915
916 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
917
918 /* Emit the clear packet. */
919 si_emit_cp_dma_clear_buffer(cmd_buffer, va, byte_count, value,
920 dma_flags);
921
922 size -= byte_count;
923 va += byte_count;
924 }
925 }
926
927 /* For MSAA sample positions. */
928 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
929 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
930 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
931 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
932 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
933
934
935 /* 2xMSAA
936 * There are two locations (4, 4), (-4, -4). */
937 const uint32_t eg_sample_locs_2x[4] = {
938 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
939 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
940 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
941 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
942 };
943 const unsigned eg_max_dist_2x = 4;
944 /* 4xMSAA
945 * There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
946 const uint32_t eg_sample_locs_4x[4] = {
947 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
948 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
949 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
950 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
951 };
952 const unsigned eg_max_dist_4x = 6;
953
954 /* Cayman 8xMSAA */
955 static const uint32_t cm_sample_locs_8x[] = {
956 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
957 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
958 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
959 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
960 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
961 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
962 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
963 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
964 };
965 static const unsigned cm_max_dist_8x = 8;
966 /* Cayman 16xMSAA */
967 static const uint32_t cm_sample_locs_16x[] = {
968 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
969 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
970 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
971 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
972 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
973 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
974 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
975 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
976 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
977 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
978 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
979 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
980 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
981 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
982 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
983 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
984 };
985 static const unsigned cm_max_dist_16x = 8;
986
987 unsigned radv_cayman_get_maxdist(int log_samples)
988 {
989 unsigned max_dist[] = {
990 0,
991 eg_max_dist_2x,
992 eg_max_dist_4x,
993 cm_max_dist_8x,
994 cm_max_dist_16x
995 };
996 return max_dist[log_samples];
997 }
998
999 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples)
1000 {
1001 switch (nr_samples) {
1002 default:
1003 case 1:
1004 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
1005 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
1006 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
1007 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
1008 break;
1009 case 2:
1010 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
1011 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
1012 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
1013 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
1014 break;
1015 case 4:
1016 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
1017 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
1018 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
1019 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
1020 break;
1021 case 8:
1022 radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1023 radeon_emit(cs, cm_sample_locs_8x[0]);
1024 radeon_emit(cs, cm_sample_locs_8x[4]);
1025 radeon_emit(cs, 0);
1026 radeon_emit(cs, 0);
1027 radeon_emit(cs, cm_sample_locs_8x[1]);
1028 radeon_emit(cs, cm_sample_locs_8x[5]);
1029 radeon_emit(cs, 0);
1030 radeon_emit(cs, 0);
1031 radeon_emit(cs, cm_sample_locs_8x[2]);
1032 radeon_emit(cs, cm_sample_locs_8x[6]);
1033 radeon_emit(cs, 0);
1034 radeon_emit(cs, 0);
1035 radeon_emit(cs, cm_sample_locs_8x[3]);
1036 radeon_emit(cs, cm_sample_locs_8x[7]);
1037 break;
1038 case 16:
1039 radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
1040 radeon_emit(cs, cm_sample_locs_16x[0]);
1041 radeon_emit(cs, cm_sample_locs_16x[4]);
1042 radeon_emit(cs, cm_sample_locs_16x[8]);
1043 radeon_emit(cs, cm_sample_locs_16x[12]);
1044 radeon_emit(cs, cm_sample_locs_16x[1]);
1045 radeon_emit(cs, cm_sample_locs_16x[5]);
1046 radeon_emit(cs, cm_sample_locs_16x[9]);
1047 radeon_emit(cs, cm_sample_locs_16x[13]);
1048 radeon_emit(cs, cm_sample_locs_16x[2]);
1049 radeon_emit(cs, cm_sample_locs_16x[6]);
1050 radeon_emit(cs, cm_sample_locs_16x[10]);
1051 radeon_emit(cs, cm_sample_locs_16x[14]);
1052 radeon_emit(cs, cm_sample_locs_16x[3]);
1053 radeon_emit(cs, cm_sample_locs_16x[7]);
1054 radeon_emit(cs, cm_sample_locs_16x[11]);
1055 radeon_emit(cs, cm_sample_locs_16x[15]);
1056 break;
1057 }
1058 }
1059
1060 static void radv_cayman_get_sample_position(struct radv_device *device,
1061 unsigned sample_count,
1062 unsigned sample_index, float *out_value)
1063 {
1064 int offset, index;
1065 struct {
1066 int idx:4;
1067 } val;
1068 switch (sample_count) {
1069 case 1:
1070 default:
1071 out_value[0] = out_value[1] = 0.5;
1072 break;
1073 case 2:
1074 offset = 4 * (sample_index * 2);
1075 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1076 out_value[0] = (float)(val.idx + 8) / 16.0f;
1077 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1078 out_value[1] = (float)(val.idx + 8) / 16.0f;
1079 break;
1080 case 4:
1081 offset = 4 * (sample_index * 2);
1082 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1083 out_value[0] = (float)(val.idx + 8) / 16.0f;
1084 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1085 out_value[1] = (float)(val.idx + 8) / 16.0f;
1086 break;
1087 case 8:
1088 offset = 4 * (sample_index % 4 * 2);
1089 index = (sample_index / 4) * 4;
1090 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1091 out_value[0] = (float)(val.idx + 8) / 16.0f;
1092 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1093 out_value[1] = (float)(val.idx + 8) / 16.0f;
1094 break;
1095 case 16:
1096 offset = 4 * (sample_index % 4 * 2);
1097 index = (sample_index / 4) * 4;
1098 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1099 out_value[0] = (float)(val.idx + 8) / 16.0f;
1100 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1101 out_value[1] = (float)(val.idx + 8) / 16.0f;
1102 break;
1103 }
1104 }
1105
1106 void radv_device_init_msaa(struct radv_device *device)
1107 {
1108 int i;
1109 radv_cayman_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1110
1111 for (i = 0; i < 2; i++)
1112 radv_cayman_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1113 for (i = 0; i < 4; i++)
1114 radv_cayman_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1115 for (i = 0; i < 8; i++)
1116 radv_cayman_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1117 for (i = 0; i < 16; i++)
1118 radv_cayman_get_sample_position(device, 16, i, device->sample_locations_16x[i]);
1119 }