projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: simplify checking for Navi1x chips
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for AMD GCN */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "radv_util.h"
35
36 static void
37 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
38 struct radeon_cmdbuf *cs,
39 unsigned raster_config,
40 unsigned raster_config_1)
41 {
42 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
43 unsigned raster_config_se[4];
44 unsigned se;
45
46 ac_get_harvested_configs(&physical_device->rad_info,
47 raster_config,
48 &raster_config_1,
49 raster_config_se);
50
51 for (se = 0; se < num_se; se++) {
52 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
53 if (physical_device->rad_info.chip_class < GFX7)
54 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
55 S_00802C_SE_INDEX(se) |
56 S_00802C_SH_BROADCAST_WRITES(1) |
57 S_00802C_INSTANCE_BROADCAST_WRITES(1));
58 else
59 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
60 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
61 S_030800_INSTANCE_BROADCAST_WRITES(1));
62 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
63 }
64
65 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
66 if (physical_device->rad_info.chip_class < GFX7)
67 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
68 S_00802C_SE_BROADCAST_WRITES(1) |
69 S_00802C_SH_BROADCAST_WRITES(1) |
70 S_00802C_INSTANCE_BROADCAST_WRITES(1));
71 else
72 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
73 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
74 S_030800_INSTANCE_BROADCAST_WRITES(1));
75
76 if (physical_device->rad_info.chip_class >= GFX7)
77 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
78 }
79
80 void
81 si_emit_compute(struct radv_physical_device *physical_device,
82 struct radeon_cmdbuf *cs)
83 {
84 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
85 radeon_emit(cs, 0);
86 radeon_emit(cs, 0);
87 radeon_emit(cs, 0);
88
89 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
90 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
91 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
92 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
93 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
94
95 if (physical_device->rad_info.chip_class >= GFX7) {
96 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
97 radeon_set_sh_reg_seq(cs,
98 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
99 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
100 S_00B858_SH1_CU_EN(0xffff));
101 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
102 S_00B858_SH1_CU_EN(0xffff));
103 }
104
105 if (physical_device->rad_info.chip_class >= GFX10)
106 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
107
108 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
109 * and is now per pipe, so it should be handled in the
110 * kernel if we want to use something other than the default value,
111 * which is now 0x22f.
112 */
113 if (physical_device->rad_info.chip_class <= GFX6) {
114 /* XXX: This should be:
115 * (number of compute units) * 4 * (waves per simd) - 1 */
116
117 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
118 0x190 /* Default value */);
119 }
120 }
121
122 /* 12.4 fixed-point */
123 static unsigned radv_pack_float_12p4(float x)
124 {
125 return x <= 0 ? 0 :
126 x >= 4096 ? 0xffff : x * 16;
127 }
128
129 static void
130 si_set_raster_config(struct radv_physical_device *physical_device,
131 struct radeon_cmdbuf *cs)
132 {
133 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
134 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
135 unsigned raster_config, raster_config_1;
136
137 ac_get_raster_config(&physical_device->rad_info,
138 &raster_config,
139 &raster_config_1, NULL);
140
141 /* Always use the default config when all backends are enabled
142 * (or when we failed to determine the enabled backends).
143 */
144 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
145 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
146 raster_config);
147 if (physical_device->rad_info.chip_class >= GFX7)
148 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
149 raster_config_1);
150 } else {
151 si_write_harvested_raster_configs(physical_device, cs,
152 raster_config,
153 raster_config_1);
154 }
155 }
156
157 void
158 si_emit_graphics(struct radv_physical_device *physical_device,
159 struct radeon_cmdbuf *cs)
160 {
161 bool has_clear_state = physical_device->rad_info.has_clear_state;
162 int i;
163
164 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
165 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
166 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
167
168 if (has_clear_state) {
169 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
170 radeon_emit(cs, 0);
171 }
172
173 if (physical_device->rad_info.chip_class <= GFX8)
174 si_set_raster_config(physical_device, cs);
175
176 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
177 if (!has_clear_state)
178 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
179
180 /* FIXME calculate these values somehow ??? */
181 if (physical_device->rad_info.chip_class <= GFX8) {
182 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
183 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
184 }
185
186 if (!has_clear_state) {
187 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
188 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
189 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
190 }
191
192 if (physical_device->rad_info.chip_class <= GFX9)
193 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
194 if (!has_clear_state)
195 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
196 if (physical_device->rad_info.chip_class < GFX7)
197 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
198 S_008A14_CLIP_VTX_REORDER_ENA(1));
199
200 if (!has_clear_state)
201 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
202
203 /* CLEAR_STATE doesn't clear these correctly on certain generations.
204 * I don't know why. Deduced by trial and error.
205 */
206 if (physical_device->rad_info.chip_class <= GFX7 || !has_clear_state) {
207 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
208 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
209 S_028204_WINDOW_OFFSET_DISABLE(1));
210 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
211 S_028240_WINDOW_OFFSET_DISABLE(1));
212 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
213 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
214 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
215 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
216 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
217 }
218
219 if (!has_clear_state) {
220 for (i = 0; i < 16; i++) {
221 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
222 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
223 }
224 }
225
226 if (!has_clear_state) {
227 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
228 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
229 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on GFX6 */
230 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
231 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
232 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
233 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
234 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
235 }
236
237 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
238 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
239 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
240
241 if (physical_device->rad_info.chip_class >= GFX10) {
242 radeon_set_context_reg(cs, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0);
243 radeon_set_uconfig_reg(cs, R_030964_GE_MAX_VTX_INDX, ~0);
244 radeon_set_uconfig_reg(cs, R_030924_GE_MIN_VTX_INDX, 0);
245 radeon_set_uconfig_reg(cs, R_030928_GE_INDX_OFFSET, 0);
246 radeon_set_uconfig_reg(cs, R_03097C_GE_STEREO_CNTL, 0);
247 radeon_set_uconfig_reg(cs, R_030988_GE_USER_VGPR_EN, 0);
248 } else if (physical_device->rad_info.chip_class == GFX9) {
249 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
250 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
251 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
252 } else {
253 /* These registers, when written, also overwrite the
254 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
255 * them. It would be an issue if there was another UMD
256 * changing them.
257 */
258 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
259 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
260 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
261 }
262
263 if (physical_device->rad_info.chip_class >= GFX7) {
264 if (physical_device->rad_info.chip_class >= GFX10) {
265 /* Logical CUs 16 - 31 */
266 radeon_set_sh_reg_idx(physical_device, cs, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
267 3, S_00B404_CU_EN(0xffff));
268 radeon_set_sh_reg_idx(physical_device, cs, R_00B104_SPI_SHADER_PGM_RSRC4_VS,
269 3, S_00B104_CU_EN(0xffff));
270 radeon_set_sh_reg_idx(physical_device, cs, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
271 3, S_00B004_CU_EN(0xffff));
272 }
273
274 if (physical_device->rad_info.chip_class >= GFX9) {
275 radeon_set_sh_reg_idx(physical_device, cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
276 3, S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
277 } else {
278 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
279 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
280 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
281 S_00B41C_WAVE_LIMIT(0x3F));
282 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
283 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
284 /* If this is 0, Bonaire can hang even if GS isn't being used.
285 * Other chips are unaffected. These are suboptimal values,
286 * but we don't use on-chip GS.
287 */
288 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
289 S_028A44_ES_VERTS_PER_SUBGRP(64) |
290 S_028A44_GS_PRIMS_PER_SUBGRP(4));
291 }
292
293 /* Compute LATE_ALLOC_VS.LIMIT. */
294 unsigned num_cu_per_sh = physical_device->rad_info.num_good_cu_per_sh;
295 unsigned late_alloc_wave64 = 0; /* The limit is per SH. */
296 unsigned late_alloc_wave64_gs = 0;
297 unsigned cu_mask_vs = 0xffff;
298 unsigned cu_mask_gs = 0xffff;
299
300 if (physical_device->rad_info.chip_class >= GFX10) {
301 /* For Wave32, the hw will launch twice the number of late
302 * alloc waves, so 1 == 2x wave32.
303 */
304 if (!physical_device->rad_info.use_late_alloc) {
305 late_alloc_wave64 = 0;
306 } else if (num_cu_per_sh <= 6) {
307 late_alloc_wave64 = num_cu_per_sh - 2;
308 } else {
309 late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
310
311 /* CU2 & CU3 disabled because of the dual CU design */
312 cu_mask_vs = 0xfff3;
313 cu_mask_gs = 0xfff3; /* NGG only */
314 }
315
316 late_alloc_wave64_gs = late_alloc_wave64;
317
318 /* Don't use late alloc for NGG on Navi14 due to a hw
319 * bug. If NGG is never used, enable all CUs.
320 */
321 if (!physical_device->use_ngg ||
322 physical_device->rad_info.family == CHIP_NAVI14) {
323 late_alloc_wave64_gs = 0;
324 cu_mask_gs = 0xffff;
325 }
326 } else {
327 if (!physical_device->rad_info.use_late_alloc) {
328 late_alloc_wave64 = 0;
329 } else if (num_cu_per_sh <= 4) {
330 /* Too few available compute units per SH.
331 * Disallowing VS to run on one CU could hurt
332 * us more than late VS allocation would help.
333 *
334 * 2 is the highest safe number that allows us
335 * to keep all CUs enabled.
336 */
337 late_alloc_wave64 = 2;
338 } else {
339 /* This is a good initial value, allowing 1
340 * late_alloc wave per SIMD on num_cu - 2.
341 */
342 late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
343 }
344
345 if (late_alloc_wave64 > 2)
346 cu_mask_vs = 0xfffe; /* 1 CU disabled */
347 }
348
349 radeon_set_sh_reg_idx(physical_device, cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
350 3, S_00B118_CU_EN(cu_mask_vs) |
351 S_00B118_WAVE_LIMIT(0x3F));
352 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
353 S_00B11C_LIMIT(late_alloc_wave64));
354
355 radeon_set_sh_reg_idx(physical_device, cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
356 3, S_00B21C_CU_EN(cu_mask_gs) | S_00B21C_WAVE_LIMIT(0x3F));
357
358 if (physical_device->rad_info.chip_class >= GFX10) {
359 radeon_set_sh_reg_idx(physical_device, cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
360 3, S_00B204_CU_EN(0xffff) |
361 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64_gs));
362 }
363
364 radeon_set_sh_reg_idx(physical_device, cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
365 3, S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
366 }
367
368 if (physical_device->rad_info.chip_class >= GFX10) {
369 /* Break up a pixel wave if it contains deallocs for more than
370 * half the parameter cache.
371 *
372 * To avoid a deadlock where pixel waves aren't launched
373 * because they're waiting for more pixels while the frontend
374 * is stuck waiting for PC space, the maximum allowed value is
375 * the size of the PC minus the largest possible allocation for
376 * a single primitive shader subgroup.
377 */
378 radeon_set_context_reg(cs, R_028C50_PA_SC_NGG_MODE_CNTL,
379 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
380 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
381
382 /* Enable CMASK/FMASK/HTILE/DCC caching in L2 for small chips. */
383 unsigned meta_write_policy, meta_read_policy;
384
385 /* TODO: investigate whether LRU improves performance on other chips too */
386 if (physical_device->rad_info.num_render_backends <= 4) {
387 meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */
388 meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */
389 } else {
390 meta_write_policy = V_02807C_CACHE_STREAM_WR; /* write combine */
391 meta_read_policy = V_02807C_CACHE_NOA_RD; /* don't cache reads */
392 }
393
394 radeon_set_context_reg(cs, R_02807C_DB_RMI_L2_CACHE_CONTROL,
395 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
396 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
397 S_02807C_HTILE_WR_POLICY(meta_write_policy) |
398 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
399 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
400 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
401 S_02807C_HTILE_RD_POLICY(meta_read_policy));
402
403 radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
404 S_028410_CMASK_WR_POLICY(meta_write_policy) |
405 S_028410_FMASK_WR_POLICY(meta_write_policy) |
406 S_028410_DCC_WR_POLICY(meta_write_policy) |
407 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
408 S_028410_CMASK_RD_POLICY(meta_read_policy) |
409 S_028410_FMASK_RD_POLICY(meta_read_policy) |
410 S_028410_DCC_RD_POLICY(meta_read_policy) |
411 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
412 radeon_set_context_reg(cs, R_028428_CB_COVERAGE_OUT_CONTROL, 0);
413
414 radeon_set_sh_reg(cs, R_00B0C0_SPI_SHADER_REQ_CTRL_PS,
415 S_00B0C0_SOFT_GROUPING_EN(1) |
416 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
417 radeon_set_sh_reg(cs, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
418
419 if (physical_device->rad_info.chip_class == GFX10) {
420 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
421 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
422 radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
423 }
424
425 /* TODO: For culling, replace 128 with 256. */
426 radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC,
427 S_030980_OVERSUB_EN(physical_device->rad_info.use_late_alloc) |
428 S_030980_NUM_PC_LINES(128 * physical_device->rad_info.max_se - 1));
429 }
430
431 if (physical_device->rad_info.chip_class >= GFX9) {
432 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
433 S_028B50_ACCUM_ISOLINE(40) |
434 S_028B50_ACCUM_TRI(30) |
435 S_028B50_ACCUM_QUAD(24) |
436 S_028B50_DONUT_SPLIT(24) |
437 S_028B50_TRAP_SPLIT(6));
438 } else if (physical_device->rad_info.chip_class >= GFX8) {
439 uint32_t vgt_tess_distribution;
440
441 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
442 S_028B50_ACCUM_TRI(11) |
443 S_028B50_ACCUM_QUAD(11) |
444 S_028B50_DONUT_SPLIT(16);
445
446 if (physical_device->rad_info.family == CHIP_FIJI ||
447 physical_device->rad_info.family >= CHIP_POLARIS10)
448 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
449
450 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
451 vgt_tess_distribution);
452 } else if (!has_clear_state) {
453 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
454 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
455 }
456
457 if (physical_device->rad_info.chip_class >= GFX9) {
458 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
459 S_028C48_MAX_ALLOC_COUNT(physical_device->rad_info.pbb_max_alloc_count - 1) |
460 S_028C48_MAX_PRIM_PER_BATCH(1023));
461 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
462 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
463 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
464 }
465
466 unsigned tmp = (unsigned)(1.0 * 8.0);
467 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
468 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
469 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
470 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
471 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
472
473 if (!has_clear_state) {
474 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
475 S_028004_ZPASS_INCREMENT_DISABLE(1));
476 }
477
478 /* Enable the Polaris small primitive filter control.
479 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
480 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
481 * and AMDVLK doesn't have a workaround as well.
482 */
483 if (physical_device->rad_info.family >= CHIP_POLARIS10) {
484 unsigned small_prim_filter_cntl =
485 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
486 /* Workaround for a hw line bug. */
487 S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12);
488
489 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
490 small_prim_filter_cntl);
491 }
492
493 si_emit_compute(physical_device, cs);
494 }
495
496 void
497 cik_create_gfx_config(struct radv_device *device)
498 {
499 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX);
500 if (!cs)
501 return;
502
503 si_emit_graphics(device->physical_device, cs);
504
505 while (cs->cdw & 7) {
506 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
507 radeon_emit(cs, 0x80000000);
508 else
509 radeon_emit(cs, 0xffff1000);
510 }
511
512 device->gfx_init = device->ws->buffer_create(device->ws,
513 cs->cdw * 4, 4096,
514 RADEON_DOMAIN_GTT,
515 RADEON_FLAG_CPU_ACCESS|
516 RADEON_FLAG_NO_INTERPROCESS_SHARING |
517 RADEON_FLAG_READ_ONLY,
518 RADV_BO_PRIORITY_CS);
519 if (!device->gfx_init)
520 goto fail;
521
522 void *map = device->ws->buffer_map(device->gfx_init);
523 if (!map) {
524 device->ws->buffer_destroy(device->gfx_init);
525 device->gfx_init = NULL;
526 goto fail;
527 }
528 memcpy(map, cs->buf, cs->cdw * 4);
529
530 device->ws->buffer_unmap(device->gfx_init);
531 device->gfx_init_size_dw = cs->cdw;
532 fail:
533 device->ws->cs_destroy(cs);
534 }
535
536 static void
537 get_viewport_xform(const VkViewport *viewport,
538 float scale[3], float translate[3])
539 {
540 float x = viewport->x;
541 float y = viewport->y;
542 float half_width = 0.5f * viewport->width;
543 float half_height = 0.5f * viewport->height;
544 double n = viewport->minDepth;
545 double f = viewport->maxDepth;
546
547 scale[0] = half_width;
548 translate[0] = half_width + x;
549 scale[1] = half_height;
550 translate[1] = half_height + y;
551
552 scale[2] = (f - n);
553 translate[2] = n;
554 }
555
556 void
557 si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
558 int count, const VkViewport *viewports)
559 {
560 int i;
561
562 assert(count);
563 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
564 first_vp * 4 * 6, count * 6);
565
566 for (i = 0; i < count; i++) {
567 float scale[3], translate[3];
568
569
570 get_viewport_xform(&viewports[i], scale, translate);
571 radeon_emit(cs, fui(scale[0]));
572 radeon_emit(cs, fui(translate[0]));
573 radeon_emit(cs, fui(scale[1]));
574 radeon_emit(cs, fui(translate[1]));
575 radeon_emit(cs, fui(scale[2]));
576 radeon_emit(cs, fui(translate[2]));
577 }
578
579 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
580 first_vp * 4 * 2, count * 2);
581 for (i = 0; i < count; i++) {
582 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
583 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
584 radeon_emit(cs, fui(zmin));
585 radeon_emit(cs, fui(zmax));
586 }
587 }
588
589 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
590 {
591 float scale[3], translate[3];
592 VkRect2D rect;
593
594 get_viewport_xform(viewport, scale, translate);
595
596 rect.offset.x = translate[0] - fabsf(scale[0]);
597 rect.offset.y = translate[1] - fabsf(scale[1]);
598 rect.extent.width = ceilf(translate[0] + fabsf(scale[0])) - rect.offset.x;
599 rect.extent.height = ceilf(translate[1] + fabsf(scale[1])) - rect.offset.y;
600
601 return rect;
602 }
603
604 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
605 VkRect2D ret;
606 ret.offset.x = MAX2(a->offset.x, b->offset.x);
607 ret.offset.y = MAX2(a->offset.y, b->offset.y);
608 ret.extent.width = MIN2(a->offset.x + a->extent.width,
609 b->offset.x + b->extent.width) - ret.offset.x;
610 ret.extent.height = MIN2(a->offset.y + a->extent.height,
611 b->offset.y + b->extent.height) - ret.offset.y;
612 return ret;
613 }
614
615 void
616 si_write_scissors(struct radeon_cmdbuf *cs, int first,
617 int count, const VkRect2D *scissors,
618 const VkViewport *viewports, bool can_use_guardband)
619 {
620 int i;
621 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
622 const float max_range = 32767.0f;
623 if (!count)
624 return;
625
626 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
627 for (i = 0; i < count; i++) {
628 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
629 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
630
631 get_viewport_xform(viewports + i, scale, translate);
632 scale[0] = fabsf(scale[0]);
633 scale[1] = fabsf(scale[1]);
634
635 if (scale[0] < 0.5)
636 scale[0] = 0.5;
637 if (scale[1] < 0.5)
638 scale[1] = 0.5;
639
640 guardband_x = MIN2(guardband_x, (max_range - fabsf(translate[0])) / scale[0]);
641 guardband_y = MIN2(guardband_y, (max_range - fabsf(translate[1])) / scale[1]);
642
643 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
644 S_028250_TL_Y(scissor.offset.y) |
645 S_028250_WINDOW_OFFSET_DISABLE(1));
646 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
647 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
648 }
649 if (!can_use_guardband) {
650 guardband_x = 1.0;
651 guardband_y = 1.0;
652 }
653
654 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
655 radeon_emit(cs, fui(guardband_y));
656 radeon_emit(cs, fui(1.0));
657 radeon_emit(cs, fui(guardband_x));
658 radeon_emit(cs, fui(1.0));
659 }
660
661 static inline unsigned
662 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
663 {
664 if (num == 0)
665 return 0;
666
667 if (info->incr == 0)
668 return 0;
669
670 if (num < info->min)
671 return 0;
672
673 return 1 + ((num - info->min) / info->incr);
674 }
675
676 uint32_t
677 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
678 bool instanced_draw, bool indirect_draw,
679 bool count_from_stream_output,
680 uint32_t draw_vertex_count)
681 {
682 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
683 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
684 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
685 const unsigned max_primgroup_in_wave = 2;
686 /* SWITCH_ON_EOP(0) is always preferable. */
687 bool wd_switch_on_eop = false;
688 bool ia_switch_on_eop = false;
689 bool ia_switch_on_eoi = false;
690 bool partial_vs_wave = false;
691 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave;
692 bool multi_instances_smaller_than_primgroup;
693
694 multi_instances_smaller_than_primgroup = indirect_draw;
695 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
696 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
697 if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size)
698 multi_instances_smaller_than_primgroup = true;
699 }
700
701 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
702 partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
703
704 if (chip_class >= GFX7) {
705 wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.wd_switch_on_eop;
706
707 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
708 * We don't know that for indirect drawing, so treat it as
709 * always problematic. */
710 if (family == CHIP_HAWAII &&
711 (instanced_draw || indirect_draw))
712 wd_switch_on_eop = true;
713
714 /* Performance recommendation for 4 SE Gfx7-8 parts if
715 * instances are smaller than a primgroup.
716 * Assume indirect draws always use small instances.
717 * This is needed for good VS wave utilization.
718 */
719 if (chip_class <= GFX8 &&
720 info->max_se == 4 &&
721 multi_instances_smaller_than_primgroup)
722 wd_switch_on_eop = true;
723
724 /* Required on GFX7 and later. */
725 if (info->max_se > 2 && !wd_switch_on_eop)
726 ia_switch_on_eoi = true;
727
728 /* Required by Hawaii and, for some special cases, by GFX8. */
729 if (ia_switch_on_eoi &&
730 (family == CHIP_HAWAII ||
731 (chip_class == GFX8 &&
732 /* max primgroup in wave is always 2 - leave this for documentation */
733 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
734 partial_vs_wave = true;
735
736 /* Instancing bug on Bonaire. */
737 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
738 (instanced_draw || indirect_draw))
739 partial_vs_wave = true;
740
741 /* Hardware requirement when drawing primitives from a stream
742 * output buffer.
743 */
744 if (count_from_stream_output)
745 wd_switch_on_eop = true;
746
747 /* If the WD switch is false, the IA switch must be false too. */
748 assert(wd_switch_on_eop || !ia_switch_on_eop);
749 }
750 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
751 if (chip_class <= GFX8 && ia_switch_on_eoi)
752 partial_es_wave = true;
753
754 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
755 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
756 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
757 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
758 */
759 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
760 bool set_vgt_flush = indirect_draw;
761 if (!set_vgt_flush && instanced_draw) {
762 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
763 if (num_prims <= 1)
764 set_vgt_flush = true;
765 }
766 if (set_vgt_flush)
767 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
768 }
769 }
770
771 return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base |
772 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
773 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
774 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
775 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
776 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= GFX7 ? wd_switch_on_eop : 0);
777
778 }
779
780 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
781 enum chip_class chip_class,
782 bool is_mec,
783 unsigned event, unsigned event_flags,
784 unsigned dst_sel, unsigned data_sel,
785 uint64_t va,
786 uint32_t new_fence,
787 uint64_t gfx9_eop_bug_va)
788 {
789 unsigned op = EVENT_TYPE(event) |
790 EVENT_INDEX(event == V_028A90_CS_DONE ||
791 event == V_028A90_PS_DONE ? 6 : 5) |
792 event_flags;
793 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
794 unsigned sel = EOP_DST_SEL(dst_sel) |
795 EOP_DATA_SEL(data_sel);
796
797 /* Wait for write confirmation before writing data, but don't send
798 * an interrupt. */
799 if (data_sel != EOP_DATA_SEL_DISCARD)
800 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
801
802 if (chip_class >= GFX9 || is_gfx8_mec) {
803 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
804 * counters) must immediately precede every timestamp event to
805 * prevent a GPU hang on GFX9.
806 */
807 if (chip_class == GFX9 && !is_mec) {
808 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
809 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
810 radeon_emit(cs, gfx9_eop_bug_va);
811 radeon_emit(cs, gfx9_eop_bug_va >> 32);
812 }
813
814 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false));
815 radeon_emit(cs, op);
816 radeon_emit(cs, sel);
817 radeon_emit(cs, va); /* address lo */
818 radeon_emit(cs, va >> 32); /* address hi */
819 radeon_emit(cs, new_fence); /* immediate data lo */
820 radeon_emit(cs, 0); /* immediate data hi */
821 if (!is_gfx8_mec)
822 radeon_emit(cs, 0); /* unused */
823 } else {
824 if (chip_class == GFX7 ||
825 chip_class == GFX8) {
826 /* Two EOP events are required to make all engines go idle
827 * (and optional cache flushes executed) before the timestamp
828 * is written.
829 */
830 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
831 radeon_emit(cs, op);
832 radeon_emit(cs, va);
833 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
834 radeon_emit(cs, 0); /* immediate data */
835 radeon_emit(cs, 0); /* unused */
836 }
837
838 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
839 radeon_emit(cs, op);
840 radeon_emit(cs, va);
841 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
842 radeon_emit(cs, new_fence); /* immediate data */
843 radeon_emit(cs, 0); /* unused */
844 }
845 }
846
847 void
848 radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
849 uint32_t ref, uint32_t mask)
850 {
851 assert(op == WAIT_REG_MEM_EQUAL ||
852 op == WAIT_REG_MEM_NOT_EQUAL ||
853 op == WAIT_REG_MEM_GREATER_OR_EQUAL);
854
855 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false));
856 radeon_emit(cs, op | WAIT_REG_MEM_MEM_SPACE(1));
857 radeon_emit(cs, va);
858 radeon_emit(cs, va >> 32);
859 radeon_emit(cs, ref); /* reference value */
860 radeon_emit(cs, mask); /* mask */
861 radeon_emit(cs, 4); /* poll interval */
862 }
863
864 static void
865 si_emit_acquire_mem(struct radeon_cmdbuf *cs,
866 bool is_mec,
867 bool is_gfx9,
868 unsigned cp_coher_cntl)
869 {
870 if (is_mec || is_gfx9) {
871 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
872 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) |
873 PKT3_SHADER_TYPE_S(is_mec));
874 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
875 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
876 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
877 radeon_emit(cs, 0); /* CP_COHER_BASE */
878 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
879 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
880 } else {
881 /* ACQUIRE_MEM is only required on a compute ring. */
882 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false));
883 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
884 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
885 radeon_emit(cs, 0); /* CP_COHER_BASE */
886 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
887 }
888 }
889
890 static void
891 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
892 enum chip_class chip_class,
893 uint32_t *flush_cnt,
894 uint64_t flush_va,
895 bool is_mec,
896 enum radv_cmd_flush_bits flush_bits,
897 uint64_t gfx9_eop_bug_va)
898 {
899 uint32_t gcr_cntl = 0;
900 unsigned cb_db_event = 0;
901
902 /* We don't need these. */
903 assert(!(flush_bits & (RADV_CMD_FLAG_VGT_STREAMOUT_SYNC)));
904
905 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
906 gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
907 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE) {
908 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
909 * to FORWARD when both L1 and L2 are written out (WB or INV).
910 */
911 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
912 }
913 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE)
914 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
915 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
916 /* Writeback and invalidate everything in L2. */
917 gcr_cntl |= S_586_GL2_INV(1) | S_586_GL2_WB(1) |
918 S_586_GLM_INV(1) | S_586_GLM_WB(1);
919 } else if (flush_bits & RADV_CMD_FLAG_WB_L2) {
920 /* Writeback but do not invalidate.
921 * GLM doesn't support WB alone. If WB is set, INV must be set too.
922 */
923 gcr_cntl |= S_586_GL2_WB(1) |
924 S_586_GLM_WB(1) | S_586_GLM_INV(1);
925 }
926
927 /* TODO: Implement this new flag for GFX9+.
928 else if (flush_bits & RADV_CMD_FLAG_INV_L2_METADATA)
929 gcr_cntl |= S_586_GLM_INV(1) | S_586_GLM_WB(1);
930 */
931
932 if (flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
933 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_CB_META */
934 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
935 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
936 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
937 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
938 EVENT_INDEX(0));
939 }
940
941 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_DB_META ? */
942 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
943 /* Flush HTILE. Will wait for idle later. */
944 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
945 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) |
946 EVENT_INDEX(0));
947 }
948
949 /* First flush CB/DB, then L1/L2. */
950 gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
951
952 if ((flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) ==
953 (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
954 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
955 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
956 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
957 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
958 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
959 } else {
960 assert(0);
961 }
962 } else {
963 /* Wait for graphics shaders to go idle if requested. */
964 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
965 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
966 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
967 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
968 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
969 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
970 }
971 }
972
973 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
974 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
975 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
976 }
977
978 if (cb_db_event) {
979 /* CB/DB flush and invalidate (or possibly just a wait for a
980 * meta flush) via RELEASE_MEM.
981 *
982 * Combine this with other cache flushes when possible; this
983 * requires affected shaders to be idle, so do it after the
984 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
985 * implied).
986 */
987 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
988 unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
989 unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
990 unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
991 unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
992 assert(G_586_GL2_US(gcr_cntl) == 0);
993 assert(G_586_GL2_RANGE(gcr_cntl) == 0);
994 assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
995 unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
996 unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
997 unsigned gcr_seq = G_586_SEQ(gcr_cntl);
998
999 gcr_cntl &= C_586_GLM_WB &
1000 C_586_GLM_INV &
1001 C_586_GLV_INV &
1002 C_586_GL1_INV &
1003 C_586_GL2_INV &
1004 C_586_GL2_WB; /* keep SEQ */
1005
1006 assert(flush_cnt);
1007 (*flush_cnt)++;
1008
1009 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event,
1010 S_490_GLM_WB(glm_wb) |
1011 S_490_GLM_INV(glm_inv) |
1012 S_490_GLV_INV(glv_inv) |
1013 S_490_GL1_INV(gl1_inv) |
1014 S_490_GL2_INV(gl2_inv) |
1015 S_490_GL2_WB(gl2_wb) |
1016 S_490_SEQ(gcr_seq),
1017 EOP_DST_SEL_MEM,
1018 EOP_DATA_SEL_VALUE_32BIT,
1019 flush_va, *flush_cnt,
1020 gfx9_eop_bug_va);
1021
1022 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
1023 *flush_cnt, 0xffffffff);
1024 }
1025
1026 /* VGT state sync */
1027 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1028 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1029 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1030 }
1031
1032 /* Ignore fields that only modify the behavior of other fields. */
1033 if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
1034 /* Flush caches and wait for the caches to assert idle.
1035 * The cache flush is executed in the ME, but the PFP waits
1036 * for completion.
1037 */
1038 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
1039 radeon_emit(cs, 0); /* CP_COHER_CNTL */
1040 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1041 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1042 radeon_emit(cs, 0); /* CP_COHER_BASE */
1043 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1044 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1045 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
1046 } else if ((cb_db_event ||
1047 (flush_bits & (RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1048 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1049 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)))
1050 && !is_mec) {
1051 /* We need to ensure that PFP waits as well. */
1052 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1053 radeon_emit(cs, 0);
1054 }
1055
1056 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1057 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1058 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1059 EVENT_INDEX(0));
1060 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1061 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1062 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1063 EVENT_INDEX(0));
1064 }
1065 }
1066
1067 void
1068 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1069 enum chip_class chip_class,
1070 uint32_t *flush_cnt,
1071 uint64_t flush_va,
1072 bool is_mec,
1073 enum radv_cmd_flush_bits flush_bits,
1074 uint64_t gfx9_eop_bug_va)
1075 {
1076 unsigned cp_coher_cntl = 0;
1077 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1078 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
1079
1080 if (chip_class >= GFX10) {
1081 /* GFX10 cache flush handling is quite different. */
1082 gfx10_cs_emit_cache_flush(cs, chip_class, flush_cnt, flush_va,
1083 is_mec, flush_bits, gfx9_eop_bug_va);
1084 return;
1085 }
1086
1087 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
1088 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1089 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE)
1090 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1091
1092 if (chip_class <= GFX8) {
1093 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
1094 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
1095 S_0085F0_CB0_DEST_BASE_ENA(1) |
1096 S_0085F0_CB1_DEST_BASE_ENA(1) |
1097 S_0085F0_CB2_DEST_BASE_ENA(1) |
1098 S_0085F0_CB3_DEST_BASE_ENA(1) |
1099 S_0085F0_CB4_DEST_BASE_ENA(1) |
1100 S_0085F0_CB5_DEST_BASE_ENA(1) |
1101 S_0085F0_CB6_DEST_BASE_ENA(1) |
1102 S_0085F0_CB7_DEST_BASE_ENA(1);
1103
1104 /* Necessary for DCC */
1105 if (chip_class >= GFX8) {
1106 si_cs_emit_write_event_eop(cs,
1107 chip_class,
1108 is_mec,
1109 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
1110 0,
1111 EOP_DST_SEL_MEM,
1112 EOP_DATA_SEL_DISCARD,
1113 0, 0,
1114 gfx9_eop_bug_va);
1115 }
1116 }
1117 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
1118 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
1119 S_0085F0_DB_DEST_BASE_ENA(1);
1120 }
1121 }
1122
1123 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
1124 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1125 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1126 }
1127
1128 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
1129 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1130 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1131 }
1132
1133 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
1134 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1135 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1136 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
1137 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1138 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1139 }
1140
1141 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
1142 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1143 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1144 }
1145
1146 if (chip_class == GFX9 && flush_cb_db) {
1147 unsigned cb_db_event, tc_flags;
1148
1149 /* Set the CB/DB flush event. */
1150 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1151
1152 /* These are the only allowed combinations. If you need to
1153 * do multiple operations at once, do them separately.
1154 * All operations that invalidate L2 also seem to invalidate
1155 * metadata. Volatile (VOL) and WC flushes are not listed here.
1156 *
1157 * TC | TC_WB = writeback & invalidate L2 & L1
1158 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1159 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1160 * TC | TC_NC = invalidate L2 for MTYPE == NC
1161 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1162 * TCL1 = invalidate L1
1163 */
1164 tc_flags = EVENT_TC_ACTION_ENA |
1165 EVENT_TC_MD_ACTION_ENA;
1166
1167 /* Ideally flush TC together with CB/DB. */
1168 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
1169 /* Writeback and invalidate everything in L2 & L1. */
1170 tc_flags = EVENT_TC_ACTION_ENA |
1171 EVENT_TC_WB_ACTION_ENA;
1172
1173
1174 /* Clear the flags. */
1175 flush_bits &= ~(RADV_CMD_FLAG_INV_L2 |
1176 RADV_CMD_FLAG_WB_L2 |
1177 RADV_CMD_FLAG_INV_VCACHE);
1178 }
1179 assert(flush_cnt);
1180 (*flush_cnt)++;
1181
1182 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags,
1183 EOP_DST_SEL_MEM,
1184 EOP_DATA_SEL_VALUE_32BIT,
1185 flush_va, *flush_cnt,
1186 gfx9_eop_bug_va);
1187 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
1188 *flush_cnt, 0xffffffff);
1189 }
1190
1191 /* VGT state sync */
1192 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1193 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1194 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1195 }
1196
1197 /* VGT streamout state sync */
1198 if (flush_bits & RADV_CMD_FLAG_VGT_STREAMOUT_SYNC) {
1199 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1200 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1201 }
1202
1203 /* Make sure ME is idle (it executes most packets) before continuing.
1204 * This prevents read-after-write hazards between PFP and ME.
1205 */
1206 if ((cp_coher_cntl ||
1207 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1208 RADV_CMD_FLAG_INV_VCACHE |
1209 RADV_CMD_FLAG_INV_L2 |
1210 RADV_CMD_FLAG_WB_L2))) &&
1211 !is_mec) {
1212 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1213 radeon_emit(cs, 0);
1214 }
1215
1216 if ((flush_bits & RADV_CMD_FLAG_INV_L2) ||
1217 (chip_class <= GFX7 && (flush_bits & RADV_CMD_FLAG_WB_L2))) {
1218 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9,
1219 cp_coher_cntl |
1220 S_0085F0_TC_ACTION_ENA(1) |
1221 S_0085F0_TCL1_ACTION_ENA(1) |
1222 S_0301F0_TC_WB_ACTION_ENA(chip_class >= GFX8));
1223 cp_coher_cntl = 0;
1224 } else {
1225 if(flush_bits & RADV_CMD_FLAG_WB_L2) {
1226 /* WB = write-back
1227 * NC = apply to non-coherent MTYPEs
1228 * (i.e. MTYPE <= 1, which is what we use everywhere)
1229 *
1230 * WB doesn't work without NC.
1231 */
1232 si_emit_acquire_mem(cs, is_mec,
1233 chip_class == GFX9,
1234 cp_coher_cntl |
1235 S_0301F0_TC_WB_ACTION_ENA(1) |
1236 S_0301F0_TC_NC_ACTION_ENA(1));
1237 cp_coher_cntl = 0;
1238 }
1239 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE) {
1240 si_emit_acquire_mem(cs, is_mec,
1241 chip_class == GFX9,
1242 cp_coher_cntl |
1243 S_0085F0_TCL1_ACTION_ENA(1));
1244 cp_coher_cntl = 0;
1245 }
1246 }
1247
1248 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1249 * Therefore, it should be last. Done in PFP.
1250 */
1251 if (cp_coher_cntl)
1252 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9, cp_coher_cntl);
1253
1254 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1255 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1256 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1257 EVENT_INDEX(0));
1258 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1259 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1260 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1261 EVENT_INDEX(0));
1262 }
1263 }
1264
1265 void
1266 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
1267 {
1268 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1269
1270 if (is_compute)
1271 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1272 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1273 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1274 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1275 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1276 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1277 RADV_CMD_FLAG_VGT_FLUSH |
1278 RADV_CMD_FLAG_START_PIPELINE_STATS |
1279 RADV_CMD_FLAG_STOP_PIPELINE_STATS);
1280
1281 if (!cmd_buffer->state.flush_bits)
1282 return;
1283
1284 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1285
1286 si_cs_emit_cache_flush(cmd_buffer->cs,
1287 cmd_buffer->device->physical_device->rad_info.chip_class,
1288 &cmd_buffer->gfx9_fence_idx,
1289 cmd_buffer->gfx9_fence_va,
1290 radv_cmd_buffer_uses_mec(cmd_buffer),
1291 cmd_buffer->state.flush_bits,
1292 cmd_buffer->gfx9_eop_bug_va);
1293
1294
1295 if (unlikely(cmd_buffer->device->trace_bo))
1296 radv_cmd_buffer_trace_emit(cmd_buffer);
1297
1298 /* Clear the caches that have been flushed to avoid syncing too much
1299 * when there is some pending active queries.
1300 */
1301 cmd_buffer->active_query_flush_bits &= ~cmd_buffer->state.flush_bits;
1302
1303 cmd_buffer->state.flush_bits = 0;
1304
1305 /* If the driver used a compute shader for resetting a query pool, it
1306 * should be finished at this point.
1307 */
1308 cmd_buffer->pending_reset_query = false;
1309 }
1310
1311 /* sets the CP predication state using a boolean stored at va */
1312 void
1313 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1314 bool draw_visible, uint64_t va)
1315 {
1316 uint32_t op = 0;
1317
1318 if (va) {
1319 op = PRED_OP(PREDICATION_OP_BOOL64);
1320
1321 /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
1322 * zero, all rendering commands are discarded. Otherwise, they
1323 * are discarded if the value is non zero.
1324 */
1325 op |= draw_visible ? PREDICATION_DRAW_VISIBLE :
1326 PREDICATION_DRAW_NOT_VISIBLE;
1327 }
1328 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1329 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1330 radeon_emit(cmd_buffer->cs, op);
1331 radeon_emit(cmd_buffer->cs, va);
1332 radeon_emit(cmd_buffer->cs, va >> 32);
1333 } else {
1334 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1335 radeon_emit(cmd_buffer->cs, va);
1336 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1337 }
1338 }
1339
1340 /* Set this if you want the 3D engine to wait until CP DMA is done.
1341 * It should be set on the last CP DMA packet. */
1342 #define CP_DMA_SYNC (1 << 0)
1343
1344 /* Set this if the source data was used as a destination in a previous CP DMA
1345 * packet. It's for preventing a read-after-write (RAW) hazard between two
1346 * CP DMA packets. */
1347 #define CP_DMA_RAW_WAIT (1 << 1)
1348 #define CP_DMA_USE_L2 (1 << 2)
1349 #define CP_DMA_CLEAR (1 << 3)
1350
1351 /* Alignment for optimal performance. */
1352 #define SI_CPDMA_ALIGNMENT 32
1353
1354 /* The max number of bytes that can be copied per packet. */
1355 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1356 {
1357 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1358 S_414_BYTE_COUNT_GFX9(~0u) :
1359 S_414_BYTE_COUNT_GFX6(~0u);
1360
1361 /* make it aligned for optimal performance */
1362 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1363 }
1364
1365 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1366 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1367 * clear value.
1368 */
1369 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1370 uint64_t dst_va, uint64_t src_va,
1371 unsigned size, unsigned flags)
1372 {
1373 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1374 uint32_t header = 0, command = 0;
1375
1376 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1377
1378 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1379 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1380 command |= S_414_BYTE_COUNT_GFX9(size);
1381 else
1382 command |= S_414_BYTE_COUNT_GFX6(size);
1383
1384 /* Sync flags. */
1385 if (flags & CP_DMA_SYNC)
1386 header |= S_411_CP_SYNC(1);
1387 else {
1388 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1389 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1390 else
1391 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1392 }
1393
1394 if (flags & CP_DMA_RAW_WAIT)
1395 command |= S_414_RAW_WAIT(1);
1396
1397 /* Src and dst flags. */
1398 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1399 !(flags & CP_DMA_CLEAR) &&
1400 src_va == dst_va)
1401 header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
1402 else if (flags & CP_DMA_USE_L2)
1403 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
1404
1405 if (flags & CP_DMA_CLEAR)
1406 header |= S_411_SRC_SEL(V_411_DATA);
1407 else if (flags & CP_DMA_USE_L2)
1408 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1409
1410 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1411 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1412 radeon_emit(cs, header);
1413 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1414 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1415 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1416 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1417 radeon_emit(cs, command);
1418 } else {
1419 assert(!(flags & CP_DMA_USE_L2));
1420 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1421 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1422 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1423 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1424 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1425 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1426 radeon_emit(cs, command);
1427 }
1428
1429 /* CP DMA is executed in ME, but index buffers are read by PFP.
1430 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1431 * indices. If we wanted to execute CP DMA in PFP, this packet
1432 * should precede it.
1433 */
1434 if (flags & CP_DMA_SYNC) {
1435 if (cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1436 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1437 radeon_emit(cs, 0);
1438 }
1439
1440 /* CP will see the sync flag and wait for all DMAs to complete. */
1441 cmd_buffer->state.dma_is_busy = false;
1442 }
1443
1444 if (unlikely(cmd_buffer->device->trace_bo))
1445 radv_cmd_buffer_trace_emit(cmd_buffer);
1446 }
1447
1448 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1449 unsigned size)
1450 {
1451 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1452 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1453
1454 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1455 aligned_size, CP_DMA_USE_L2);
1456 }
1457
1458 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1459 uint64_t remaining_size, unsigned *flags)
1460 {
1461
1462 /* Flush the caches for the first copy only.
1463 * Also wait for the previous CP DMA operations.
1464 */
1465 if (cmd_buffer->state.flush_bits) {
1466 si_emit_cache_flush(cmd_buffer);
1467 *flags |= CP_DMA_RAW_WAIT;
1468 }
1469
1470 /* Do the synchronization after the last dma, so that all data
1471 * is written to memory.
1472 */
1473 if (byte_count == remaining_size)
1474 *flags |= CP_DMA_SYNC;
1475 }
1476
1477 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1478 {
1479 uint64_t va;
1480 uint32_t offset;
1481 unsigned dma_flags = 0;
1482 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1483 void *ptr;
1484
1485 assert(size < SI_CPDMA_ALIGNMENT);
1486
1487 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1488
1489 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1490 va += offset;
1491
1492 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1493
1494 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1495 dma_flags);
1496 }
1497
1498 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1499 uint64_t src_va, uint64_t dest_va,
1500 uint64_t size)
1501 {
1502 uint64_t main_src_va, main_dest_va;
1503 uint64_t skipped_size = 0, realign_size = 0;
1504
1505 /* Assume that we are not going to sync after the last DMA operation. */
1506 cmd_buffer->state.dma_is_busy = true;
1507
1508 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1509 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1510 /* If the size is not aligned, we must add a dummy copy at the end
1511 * just to align the internal counter. Otherwise, the DMA engine
1512 * would slow down by an order of magnitude for following copies.
1513 */
1514 if (size % SI_CPDMA_ALIGNMENT)
1515 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1516
1517 /* If the copy begins unaligned, we must start copying from the next
1518 * aligned block and the skipped part should be copied after everything
1519 * else has been copied. Only the src alignment matters, not dst.
1520 */
1521 if (src_va % SI_CPDMA_ALIGNMENT) {
1522 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1523 /* The main part will be skipped if the size is too small. */
1524 skipped_size = MIN2(skipped_size, size);
1525 size -= skipped_size;
1526 }
1527 }
1528 main_src_va = src_va + skipped_size;
1529 main_dest_va = dest_va + skipped_size;
1530
1531 while (size) {
1532 unsigned dma_flags = 0;
1533 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1534
1535 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1536 /* DMA operations via L2 are coherent and faster.
1537 * TODO: GFX7-GFX9 should also support this but it
1538 * requires tests/benchmarks.
1539 */
1540 dma_flags |= CP_DMA_USE_L2;
1541 }
1542
1543 si_cp_dma_prepare(cmd_buffer, byte_count,
1544 size + skipped_size + realign_size,
1545 &dma_flags);
1546
1547 dma_flags &= ~CP_DMA_SYNC;
1548
1549 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1550 byte_count, dma_flags);
1551
1552 size -= byte_count;
1553 main_src_va += byte_count;
1554 main_dest_va += byte_count;
1555 }
1556
1557 if (skipped_size) {
1558 unsigned dma_flags = 0;
1559
1560 si_cp_dma_prepare(cmd_buffer, skipped_size,
1561 size + skipped_size + realign_size,
1562 &dma_flags);
1563
1564 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1565 skipped_size, dma_flags);
1566 }
1567 if (realign_size)
1568 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1569 }
1570
1571 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1572 uint64_t size, unsigned value)
1573 {
1574
1575 if (!size)
1576 return;
1577
1578 assert(va % 4 == 0 && size % 4 == 0);
1579
1580 /* Assume that we are not going to sync after the last DMA operation. */
1581 cmd_buffer->state.dma_is_busy = true;
1582
1583 while (size) {
1584 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1585 unsigned dma_flags = CP_DMA_CLEAR;
1586
1587 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1588 /* DMA operations via L2 are coherent and faster.
1589 * TODO: GFX7-GFX9 should also support this but it
1590 * requires tests/benchmarks.
1591 */
1592 dma_flags |= CP_DMA_USE_L2;
1593 }
1594
1595 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1596
1597 /* Emit the clear packet. */
1598 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1599 dma_flags);
1600
1601 size -= byte_count;
1602 va += byte_count;
1603 }
1604 }
1605
1606 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
1607 {
1608 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX7)
1609 return;
1610
1611 if (!cmd_buffer->state.dma_is_busy)
1612 return;
1613
1614 /* Issue a dummy DMA that copies zero bytes.
1615 *
1616 * The DMA engine will see that there's no work to do and skip this
1617 * DMA request, however, the CP will see the sync flag and still wait
1618 * for all DMAs to complete.
1619 */
1620 si_emit_cp_dma(cmd_buffer, 0, 0, 0, CP_DMA_SYNC);
1621
1622 cmd_buffer->state.dma_is_busy = false;
1623 }
1624
1625 /* For MSAA sample positions. */
1626 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1627 ((((unsigned)(s0x) & 0xf) << 0) | (((unsigned)(s0y) & 0xf) << 4) | \
1628 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1629 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1630 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1631
1632 /* For obtaining location coordinates from registers */
1633 #define SEXT4(x) ((int)((x) | ((x) & 0x8 ? 0xfffffff0 : 0)))
1634 #define GET_SFIELD(reg, index) SEXT4(((reg) >> ((index) * 4)) & 0xf)
1635 #define GET_SX(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2)
1636 #define GET_SY(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2 + 1)
1637
1638 /* 1x MSAA */
1639 static const uint32_t sample_locs_1x =
1640 FILL_SREG(0, 0, 0, 0, 0, 0, 0, 0);
1641 static const unsigned max_dist_1x = 0;
1642 static const uint64_t centroid_priority_1x = 0x0000000000000000ull;
1643
1644 /* 2xMSAA */
1645 static const uint32_t sample_locs_2x =
1646 FILL_SREG(4,4, -4, -4, 0, 0, 0, 0);
1647 static const unsigned max_dist_2x = 4;
1648 static const uint64_t centroid_priority_2x = 0x1010101010101010ull;
1649
1650 /* 4xMSAA */
1651 static const uint32_t sample_locs_4x =
1652 FILL_SREG(-2,-6, 6, -2, -6, 2, 2, 6);
1653 static const unsigned max_dist_4x = 6;
1654 static const uint64_t centroid_priority_4x = 0x3210321032103210ull;
1655
1656 /* 8xMSAA */
1657 static const uint32_t sample_locs_8x[] = {
1658 FILL_SREG( 1,-3, -1, 3, 5, 1, -3,-5),
1659 FILL_SREG(-5, 5, -7,-1, 3, 7, 7,-7),
1660 /* The following are unused by hardware, but we emit them to IBs
1661 * instead of multiple SET_CONTEXT_REG packets. */
1662 0,
1663 0,
1664 };
1665 static const unsigned max_dist_8x = 7;
1666 static const uint64_t centroid_priority_8x = 0x7654321076543210ull;
1667
1668 unsigned radv_get_default_max_sample_dist(int log_samples)
1669 {
1670 unsigned max_dist[] = {
1671 max_dist_1x,
1672 max_dist_2x,
1673 max_dist_4x,
1674 max_dist_8x,
1675 };
1676 return max_dist[log_samples];
1677 }
1678
1679 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples)
1680 {
1681 switch (nr_samples) {
1682 default:
1683 case 1:
1684 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1685 radeon_emit(cs, (uint32_t)centroid_priority_1x);
1686 radeon_emit(cs, centroid_priority_1x >> 32);
1687 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_1x);
1688 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_1x);
1689 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_1x);
1690 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_1x);
1691 break;
1692 case 2:
1693 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1694 radeon_emit(cs, (uint32_t)centroid_priority_2x);
1695 radeon_emit(cs, centroid_priority_2x >> 32);
1696 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x);
1697 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x);
1698 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x);
1699 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x);
1700 break;
1701 case 4:
1702 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1703 radeon_emit(cs, (uint32_t)centroid_priority_4x);
1704 radeon_emit(cs, centroid_priority_4x >> 32);
1705 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x);
1706 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x);
1707 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x);
1708 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x);
1709 break;
1710 case 8:
1711 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1712 radeon_emit(cs, (uint32_t)centroid_priority_8x);
1713 radeon_emit(cs, centroid_priority_8x >> 32);
1714 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1715 radeon_emit_array(cs, sample_locs_8x, 4);
1716 radeon_emit_array(cs, sample_locs_8x, 4);
1717 radeon_emit_array(cs, sample_locs_8x, 4);
1718 radeon_emit_array(cs, sample_locs_8x, 2);
1719 break;
1720 }
1721 }
1722
1723 static void radv_get_sample_position(struct radv_device *device,
1724 unsigned sample_count,
1725 unsigned sample_index, float *out_value)
1726 {
1727 const uint32_t *sample_locs;
1728
1729 switch (sample_count) {
1730 case 1:
1731 default:
1732 sample_locs = &sample_locs_1x;
1733 break;
1734 case 2:
1735 sample_locs = &sample_locs_2x;
1736 break;
1737 case 4:
1738 sample_locs = &sample_locs_4x;
1739 break;
1740 case 8:
1741 sample_locs = sample_locs_8x;
1742 break;
1743 }
1744
1745 out_value[0] = (GET_SX(sample_locs, sample_index) + 8) / 16.0f;
1746 out_value[1] = (GET_SY(sample_locs, sample_index) + 8) / 16.0f;
1747 }
1748
1749 void radv_device_init_msaa(struct radv_device *device)
1750 {
1751 int i;
1752
1753 radv_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1754
1755 for (i = 0; i < 2; i++)
1756 radv_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1757 for (i = 0; i < 4; i++)
1758 radv_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1759 for (i = 0; i < 8; i++)
1760 radv_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1761 }