projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: enable the Polaris small primitive filter control
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for SI */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "gfx9d.h"
35 #include "radv_util.h"
36 #include "main/macros.h"
37
38 static void
39 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
40 struct radeon_winsys_cs *cs,
41 unsigned raster_config,
42 unsigned raster_config_1)
43 {
44 unsigned sh_per_se = MAX2(physical_device->rad_info.max_sh_per_se, 1);
45 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
46 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
47 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
48 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
49 unsigned rb_per_se = num_rb / num_se;
50 unsigned se_mask[4];
51 unsigned se;
52
53 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
54 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
55 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
56 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
57
58 assert(num_se == 1 || num_se == 2 || num_se == 4);
59 assert(sh_per_se == 1 || sh_per_se == 2);
60 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
61
62 /* XXX: I can't figure out what the *_XSEL and *_YSEL
63 * fields are for, so I'm leaving them as their default
64 * values. */
65
66 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
67 (!se_mask[2] && !se_mask[3]))) {
68 raster_config_1 &= C_028354_SE_PAIR_MAP;
69
70 if (!se_mask[0] && !se_mask[1]) {
71 raster_config_1 |=
72 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
73 } else {
74 raster_config_1 |=
75 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
76 }
77 }
78
79 for (se = 0; se < num_se; se++) {
80 unsigned raster_config_se = raster_config;
81 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
82 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
83 int idx = (se / 2) * 2;
84
85 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
86 raster_config_se &= C_028350_SE_MAP;
87
88 if (!se_mask[idx]) {
89 raster_config_se |=
90 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
91 } else {
92 raster_config_se |=
93 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
94 }
95 }
96
97 pkr0_mask &= rb_mask;
98 pkr1_mask &= rb_mask;
99 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
100 raster_config_se &= C_028350_PKR_MAP;
101
102 if (!pkr0_mask) {
103 raster_config_se |=
104 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
105 } else {
106 raster_config_se |=
107 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
108 }
109 }
110
111 if (rb_per_se >= 2) {
112 unsigned rb0_mask = 1 << (se * rb_per_se);
113 unsigned rb1_mask = rb0_mask << 1;
114
115 rb0_mask &= rb_mask;
116 rb1_mask &= rb_mask;
117 if (!rb0_mask || !rb1_mask) {
118 raster_config_se &= C_028350_RB_MAP_PKR0;
119
120 if (!rb0_mask) {
121 raster_config_se |=
122 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
123 } else {
124 raster_config_se |=
125 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
126 }
127 }
128
129 if (rb_per_se > 2) {
130 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
131 rb1_mask = rb0_mask << 1;
132 rb0_mask &= rb_mask;
133 rb1_mask &= rb_mask;
134 if (!rb0_mask || !rb1_mask) {
135 raster_config_se &= C_028350_RB_MAP_PKR1;
136
137 if (!rb0_mask) {
138 raster_config_se |=
139 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
140 } else {
141 raster_config_se |=
142 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
143 }
144 }
145 }
146 }
147
148 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
149 if (physical_device->rad_info.chip_class < CIK)
150 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
151 S_00802C_SE_INDEX(se) |
152 S_00802C_SH_BROADCAST_WRITES(1) |
153 S_00802C_INSTANCE_BROADCAST_WRITES(1));
154 else
155 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
156 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
157 S_030800_INSTANCE_BROADCAST_WRITES(1));
158 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
159 if (physical_device->rad_info.chip_class >= CIK)
160 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
161 }
162
163 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
164 if (physical_device->rad_info.chip_class < CIK)
165 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
166 S_00802C_SE_BROADCAST_WRITES(1) |
167 S_00802C_SH_BROADCAST_WRITES(1) |
168 S_00802C_INSTANCE_BROADCAST_WRITES(1));
169 else
170 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
171 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
172 S_030800_INSTANCE_BROADCAST_WRITES(1));
173 }
174
175 static void
176 si_emit_compute(struct radv_physical_device *physical_device,
177 struct radeon_winsys_cs *cs)
178 {
179 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
180 radeon_emit(cs, 0);
181 radeon_emit(cs, 0);
182 radeon_emit(cs, 0);
183
184 radeon_set_sh_reg_seq(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
185 S_00B854_WAVES_PER_SH(0x3));
186 radeon_emit(cs, 0);
187 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
188 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
189 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
190
191 if (physical_device->rad_info.chip_class >= CIK) {
192 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
193 radeon_set_sh_reg_seq(cs,
194 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
195 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
196 S_00B864_SH1_CU_EN(0xffff));
197 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
198 S_00B868_SH1_CU_EN(0xffff));
199 }
200
201 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
202 * and is now per pipe, so it should be handled in the
203 * kernel if we want to use something other than the default value,
204 * which is now 0x22f.
205 */
206 if (physical_device->rad_info.chip_class <= SI) {
207 /* XXX: This should be:
208 * (number of compute units) * 4 * (waves per simd) - 1 */
209
210 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
211 0x190 /* Default value */);
212 }
213 }
214
215 void
216 si_init_compute(struct radv_cmd_buffer *cmd_buffer)
217 {
218 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
219 si_emit_compute(physical_device, cmd_buffer->cs);
220 }
221
222 /* 12.4 fixed-point */
223 static unsigned radv_pack_float_12p4(float x)
224 {
225 return x <= 0 ? 0 :
226 x >= 4096 ? 0xffff : x * 16;
227 }
228
229 static void
230 si_set_raster_config(struct radv_physical_device *physical_device,
231 struct radeon_winsys_cs *cs)
232 {
233 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
234 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
235 unsigned raster_config, raster_config_1;
236
237 switch (physical_device->rad_info.family) {
238 case CHIP_TAHITI:
239 case CHIP_PITCAIRN:
240 raster_config = 0x2a00126a;
241 raster_config_1 = 0x00000000;
242 break;
243 case CHIP_VERDE:
244 raster_config = 0x0000124a;
245 raster_config_1 = 0x00000000;
246 break;
247 case CHIP_OLAND:
248 raster_config = 0x00000082;
249 raster_config_1 = 0x00000000;
250 break;
251 case CHIP_HAINAN:
252 raster_config = 0x00000000;
253 raster_config_1 = 0x00000000;
254 break;
255 case CHIP_BONAIRE:
256 raster_config = 0x16000012;
257 raster_config_1 = 0x00000000;
258 break;
259 case CHIP_HAWAII:
260 raster_config = 0x3a00161a;
261 raster_config_1 = 0x0000002e;
262 break;
263 case CHIP_FIJI:
264 if (physical_device->rad_info.cik_macrotile_mode_array[0] == 0x000000e8) {
265 /* old kernels with old tiling config */
266 raster_config = 0x16000012;
267 raster_config_1 = 0x0000002a;
268 } else {
269 raster_config = 0x3a00161a;
270 raster_config_1 = 0x0000002e;
271 }
272 break;
273 case CHIP_POLARIS10:
274 raster_config = 0x16000012;
275 raster_config_1 = 0x0000002a;
276 break;
277 case CHIP_POLARIS11:
278 case CHIP_POLARIS12:
279 raster_config = 0x16000012;
280 raster_config_1 = 0x00000000;
281 break;
282 case CHIP_TONGA:
283 raster_config = 0x16000012;
284 raster_config_1 = 0x0000002a;
285 break;
286 case CHIP_ICELAND:
287 if (num_rb == 1)
288 raster_config = 0x00000000;
289 else
290 raster_config = 0x00000002;
291 raster_config_1 = 0x00000000;
292 break;
293 case CHIP_CARRIZO:
294 raster_config = 0x00000002;
295 raster_config_1 = 0x00000000;
296 break;
297 case CHIP_KAVERI:
298 /* KV should be 0x00000002, but that causes problems with radeon */
299 raster_config = 0x00000000; /* 0x00000002 */
300 raster_config_1 = 0x00000000;
301 break;
302 case CHIP_KABINI:
303 case CHIP_MULLINS:
304 case CHIP_STONEY:
305 raster_config = 0x00000000;
306 raster_config_1 = 0x00000000;
307 break;
308 default:
309 fprintf(stderr,
310 "radv: Unknown GPU, using 0 for raster_config\n");
311 raster_config = 0x00000000;
312 raster_config_1 = 0x00000000;
313 break;
314 }
315
316 /* Always use the default config when all backends are enabled
317 * (or when we failed to determine the enabled backends).
318 */
319 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
320 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
321 raster_config);
322 if (physical_device->rad_info.chip_class >= CIK)
323 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
324 raster_config_1);
325 } else {
326 si_write_harvested_raster_configs(physical_device, cs,
327 raster_config,
328 raster_config_1);
329 }
330 }
331
332 static void
333 si_emit_config(struct radv_physical_device *physical_device,
334 struct radeon_winsys_cs *cs)
335 {
336 int i;
337
338 /* Only SI can disable CLEAR_STATE for now. */
339 assert(physical_device->has_clear_state ||
340 physical_device->rad_info.chip_class == SI);
341
342 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
343 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
344 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
345
346 if (physical_device->has_clear_state) {
347 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
348 radeon_emit(cs, 0);
349 }
350
351 if (physical_device->rad_info.chip_class <= VI)
352 si_set_raster_config(physical_device, cs);
353
354 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
355 if (!physical_device->has_clear_state)
356 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
357
358 /* FIXME calculate these values somehow ??? */
359 if (physical_device->rad_info.chip_class <= VI) {
360 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
361 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
362 }
363
364 if (!physical_device->has_clear_state) {
365 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
366 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
367 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
368 }
369
370 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
371 if (!physical_device->has_clear_state)
372 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
373 if (physical_device->rad_info.chip_class < CIK)
374 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
375 S_008A14_CLIP_VTX_REORDER_ENA(1));
376
377 radeon_set_context_reg(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
378 radeon_set_context_reg(cs, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
379
380 if (!physical_device->has_clear_state)
381 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
382
383 /* CLEAR_STATE doesn't clear these correctly on certain generations.
384 * I don't know why. Deduced by trial and error.
385 */
386 if (physical_device->rad_info.chip_class <= CIK) {
387 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
388 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
389 S_028204_WINDOW_OFFSET_DISABLE(1));
390 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
391 S_028240_WINDOW_OFFSET_DISABLE(1));
392 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
393 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
394 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
395 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
396 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
397 }
398
399 if (!physical_device->has_clear_state) {
400 for (i = 0; i < 16; i++) {
401 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
402 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
403 }
404 }
405
406 if (!physical_device->has_clear_state) {
407 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
408 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
409 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
410 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
411 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
412 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
413 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
414 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
415 }
416
417 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
418 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
419 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
420
421 if (physical_device->rad_info.chip_class >= GFX9) {
422 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
423 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
424 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
425 } else {
426 /* These registers, when written, also overwrite the
427 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
428 * them. It would be an issue if there was another UMD
429 * changing them.
430 */
431 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
432 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
433 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
434 }
435
436 if (physical_device->rad_info.chip_class >= CIK) {
437 if (physical_device->rad_info.chip_class >= GFX9) {
438 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
439 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
440 } else {
441 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
442 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
443 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
444 S_00B41C_WAVE_LIMIT(0x3F));
445 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
446 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
447 /* If this is 0, Bonaire can hang even if GS isn't being used.
448 * Other chips are unaffected. These are suboptimal values,
449 * but we don't use on-chip GS.
450 */
451 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
452 S_028A44_ES_VERTS_PER_SUBGRP(64) |
453 S_028A44_GS_PRIMS_PER_SUBGRP(4));
454 }
455 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
456 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
457
458 if (physical_device->rad_info.num_good_compute_units /
459 (physical_device->rad_info.max_se * physical_device->rad_info.max_sh_per_se) <= 4) {
460 /* Too few available compute units per SH. Disallowing
461 * VS to run on CU0 could hurt us more than late VS
462 * allocation would help.
463 *
464 * LATE_ALLOC_VS = 2 is the highest safe number.
465 */
466 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
467 S_00B118_CU_EN(0xffff) | S_00B118_WAVE_LIMIT(0x3F) );
468 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
469 } else {
470 /* Set LATE_ALLOC_VS == 31. It should be less than
471 * the number of scratch waves. Limitations:
472 * - VS can't execute on CU0.
473 * - If HS writes outputs to LDS, LS can't execute on CU0.
474 */
475 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
476 S_00B118_CU_EN(0xfffe) | S_00B118_WAVE_LIMIT(0x3F));
477 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
478 }
479
480 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
481 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
482 }
483
484 if (physical_device->rad_info.chip_class >= VI) {
485 uint32_t vgt_tess_distribution;
486 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
487 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
488 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
489
490 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
491 S_028B50_ACCUM_TRI(11) |
492 S_028B50_ACCUM_QUAD(11) |
493 S_028B50_DONUT_SPLIT(16);
494
495 if (physical_device->rad_info.family == CHIP_FIJI ||
496 physical_device->rad_info.family >= CHIP_POLARIS10)
497 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
498
499 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
500 vgt_tess_distribution);
501 } else if (!physical_device->has_clear_state) {
502 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
503 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
504 }
505
506 if (physical_device->rad_info.chip_class >= GFX9) {
507 unsigned num_se = physical_device->rad_info.max_se;
508 unsigned pc_lines = 0;
509
510 switch (physical_device->rad_info.family) {
511 case CHIP_VEGA10:
512 case CHIP_VEGA12:
513 pc_lines = 4096;
514 break;
515 case CHIP_RAVEN:
516 pc_lines = 1024;
517 break;
518 default:
519 assert(0);
520 }
521
522 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
523 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
524 S_028C48_MAX_PRIM_PER_BATCH(1023));
525 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
526 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
527 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
528 }
529
530 unsigned tmp = (unsigned)(1.0 * 8.0);
531 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
532 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
533 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
534 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
535 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
536
537 if (!physical_device->has_clear_state) {
538 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
539 S_028004_ZPASS_INCREMENT_DISABLE(1));
540 }
541
542 /* Enable the Polaris small primitive filter control.
543 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
544 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
545 * and AMDVLK doesn't have a workaround as well.
546 */
547 if (physical_device->rad_info.family >= CHIP_POLARIS10) {
548 unsigned small_prim_filter_cntl =
549 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
550 /* Workaround for a hw line bug. */
551 S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12);
552
553 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
554 small_prim_filter_cntl);
555 }
556
557 si_emit_compute(physical_device, cs);
558 }
559
560 void si_init_config(struct radv_cmd_buffer *cmd_buffer)
561 {
562 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
563
564 si_emit_config(physical_device, cmd_buffer->cs);
565 }
566
567 void
568 cik_create_gfx_config(struct radv_device *device)
569 {
570 struct radeon_winsys_cs *cs = device->ws->cs_create(device->ws, RING_GFX);
571 if (!cs)
572 return;
573
574 si_emit_config(device->physical_device, cs);
575
576 while (cs->cdw & 7) {
577 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
578 radeon_emit(cs, 0x80000000);
579 else
580 radeon_emit(cs, 0xffff1000);
581 }
582
583 device->gfx_init = device->ws->buffer_create(device->ws,
584 cs->cdw * 4, 4096,
585 RADEON_DOMAIN_GTT,
586 RADEON_FLAG_CPU_ACCESS|
587 RADEON_FLAG_NO_INTERPROCESS_SHARING |
588 RADEON_FLAG_READ_ONLY);
589 if (!device->gfx_init)
590 goto fail;
591
592 void *map = device->ws->buffer_map(device->gfx_init);
593 if (!map) {
594 device->ws->buffer_destroy(device->gfx_init);
595 device->gfx_init = NULL;
596 goto fail;
597 }
598 memcpy(map, cs->buf, cs->cdw * 4);
599
600 device->ws->buffer_unmap(device->gfx_init);
601 device->gfx_init_size_dw = cs->cdw;
602 fail:
603 device->ws->cs_destroy(cs);
604 }
605
606 static void
607 get_viewport_xform(const VkViewport *viewport,
608 float scale[3], float translate[3])
609 {
610 float x = viewport->x;
611 float y = viewport->y;
612 float half_width = 0.5f * viewport->width;
613 float half_height = 0.5f * viewport->height;
614 double n = viewport->minDepth;
615 double f = viewport->maxDepth;
616
617 scale[0] = half_width;
618 translate[0] = half_width + x;
619 scale[1] = half_height;
620 translate[1] = half_height + y;
621
622 scale[2] = (f - n);
623 translate[2] = n;
624 }
625
626 void
627 si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
628 int count, const VkViewport *viewports)
629 {
630 int i;
631
632 assert(count);
633 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
634 first_vp * 4 * 6, count * 6);
635
636 for (i = 0; i < count; i++) {
637 float scale[3], translate[3];
638
639
640 get_viewport_xform(&viewports[i], scale, translate);
641 radeon_emit(cs, fui(scale[0]));
642 radeon_emit(cs, fui(translate[0]));
643 radeon_emit(cs, fui(scale[1]));
644 radeon_emit(cs, fui(translate[1]));
645 radeon_emit(cs, fui(scale[2]));
646 radeon_emit(cs, fui(translate[2]));
647 }
648
649 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
650 first_vp * 4 * 2, count * 2);
651 for (i = 0; i < count; i++) {
652 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
653 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
654 radeon_emit(cs, fui(zmin));
655 radeon_emit(cs, fui(zmax));
656 }
657 }
658
659 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
660 {
661 float scale[3], translate[3];
662 VkRect2D rect;
663
664 get_viewport_xform(viewport, scale, translate);
665
666 rect.offset.x = translate[0] - abs(scale[0]);
667 rect.offset.y = translate[1] - abs(scale[1]);
668 rect.extent.width = ceilf(translate[0] + abs(scale[0])) - rect.offset.x;
669 rect.extent.height = ceilf(translate[1] + abs(scale[1])) - rect.offset.y;
670
671 return rect;
672 }
673
674 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
675 VkRect2D ret;
676 ret.offset.x = MAX2(a->offset.x, b->offset.x);
677 ret.offset.y = MAX2(a->offset.y, b->offset.y);
678 ret.extent.width = MIN2(a->offset.x + a->extent.width,
679 b->offset.x + b->extent.width) - ret.offset.x;
680 ret.extent.height = MIN2(a->offset.y + a->extent.height,
681 b->offset.y + b->extent.height) - ret.offset.y;
682 return ret;
683 }
684
685 void
686 si_write_scissors(struct radeon_winsys_cs *cs, int first,
687 int count, const VkRect2D *scissors,
688 const VkViewport *viewports, bool can_use_guardband)
689 {
690 int i;
691 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
692 const float max_range = 32767.0f;
693 if (!count)
694 return;
695
696 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
697 for (i = 0; i < count; i++) {
698 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
699 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
700
701 get_viewport_xform(viewports + i, scale, translate);
702 scale[0] = abs(scale[0]);
703 scale[1] = abs(scale[1]);
704
705 if (scale[0] < 0.5)
706 scale[0] = 0.5;
707 if (scale[1] < 0.5)
708 scale[1] = 0.5;
709
710 guardband_x = MIN2(guardband_x, (max_range - abs(translate[0])) / scale[0]);
711 guardband_y = MIN2(guardband_y, (max_range - abs(translate[1])) / scale[1]);
712
713 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
714 S_028250_TL_Y(scissor.offset.y) |
715 S_028250_WINDOW_OFFSET_DISABLE(1));
716 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
717 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
718 }
719 if (!can_use_guardband) {
720 guardband_x = 1.0;
721 guardband_y = 1.0;
722 }
723
724 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
725 radeon_emit(cs, fui(guardband_y));
726 radeon_emit(cs, fui(1.0));
727 radeon_emit(cs, fui(guardband_x));
728 radeon_emit(cs, fui(1.0));
729 }
730
731 static inline unsigned
732 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
733 {
734 if (num == 0)
735 return 0;
736
737 if (info->incr == 0)
738 return 0;
739
740 if (num < info->min)
741 return 0;
742
743 return 1 + ((num - info->min) / info->incr);
744 }
745
746 uint32_t
747 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
748 bool instanced_draw, bool indirect_draw,
749 uint32_t draw_vertex_count)
750 {
751 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
752 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
753 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
754 const unsigned max_primgroup_in_wave = 2;
755 /* SWITCH_ON_EOP(0) is always preferable. */
756 bool wd_switch_on_eop = false;
757 bool ia_switch_on_eop = false;
758 bool ia_switch_on_eoi = false;
759 bool partial_vs_wave = false;
760 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave;
761 bool multi_instances_smaller_than_primgroup;
762
763 multi_instances_smaller_than_primgroup = indirect_draw;
764 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
765 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
766 if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size)
767 multi_instances_smaller_than_primgroup = true;
768 }
769
770 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
771 partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
772
773 if (chip_class >= CIK) {
774 wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.wd_switch_on_eop;
775
776 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
777 * We don't know that for indirect drawing, so treat it as
778 * always problematic. */
779 if (family == CHIP_HAWAII &&
780 (instanced_draw || indirect_draw))
781 wd_switch_on_eop = true;
782
783 /* Performance recommendation for 4 SE Gfx7-8 parts if
784 * instances are smaller than a primgroup.
785 * Assume indirect draws always use small instances.
786 * This is needed for good VS wave utilization.
787 */
788 if (chip_class <= VI &&
789 info->max_se == 4 &&
790 multi_instances_smaller_than_primgroup)
791 wd_switch_on_eop = true;
792
793 /* Required on CIK and later. */
794 if (info->max_se > 2 && !wd_switch_on_eop)
795 ia_switch_on_eoi = true;
796
797 /* Required by Hawaii and, for some special cases, by VI. */
798 if (ia_switch_on_eoi &&
799 (family == CHIP_HAWAII ||
800 (chip_class == VI &&
801 /* max primgroup in wave is always 2 - leave this for documentation */
802 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
803 partial_vs_wave = true;
804
805 /* Instancing bug on Bonaire. */
806 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
807 (instanced_draw || indirect_draw))
808 partial_vs_wave = true;
809
810 /* If the WD switch is false, the IA switch must be false too. */
811 assert(wd_switch_on_eop || !ia_switch_on_eop);
812 }
813 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
814 if (chip_class <= VI && ia_switch_on_eoi)
815 partial_es_wave = true;
816
817 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
818 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
819 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
820 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
821 */
822 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
823 bool set_vgt_flush = indirect_draw;
824 if (!set_vgt_flush && instanced_draw) {
825 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
826 if (num_prims <= 1)
827 set_vgt_flush = true;
828 }
829 if (set_vgt_flush)
830 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
831 }
832 }
833
834 return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base |
835 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
836 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
837 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
838 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
839 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop : 0);
840
841 }
842
843 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
844 bool predicated,
845 enum chip_class chip_class,
846 bool is_mec,
847 unsigned event, unsigned event_flags,
848 unsigned data_sel,
849 uint64_t va,
850 uint32_t old_fence,
851 uint32_t new_fence)
852 {
853 unsigned op = EVENT_TYPE(event) |
854 EVENT_INDEX(5) |
855 event_flags;
856 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
857
858 if (chip_class >= GFX9 || is_gfx8_mec) {
859 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, predicated));
860 radeon_emit(cs, op);
861 radeon_emit(cs, EOP_DATA_SEL(data_sel));
862 radeon_emit(cs, va); /* address lo */
863 radeon_emit(cs, va >> 32); /* address hi */
864 radeon_emit(cs, new_fence); /* immediate data lo */
865 radeon_emit(cs, 0); /* immediate data hi */
866 if (!is_gfx8_mec)
867 radeon_emit(cs, 0); /* unused */
868 } else {
869 if (chip_class == CIK ||
870 chip_class == VI) {
871 /* Two EOP events are required to make all engines go idle
872 * (and optional cache flushes executed) before the timestamp
873 * is written.
874 */
875 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated));
876 radeon_emit(cs, op);
877 radeon_emit(cs, va);
878 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
879 radeon_emit(cs, old_fence); /* immediate data */
880 radeon_emit(cs, 0); /* unused */
881 }
882
883 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated));
884 radeon_emit(cs, op);
885 radeon_emit(cs, va);
886 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
887 radeon_emit(cs, new_fence); /* immediate data */
888 radeon_emit(cs, 0); /* unused */
889 }
890 }
891
892 void
893 si_emit_wait_fence(struct radeon_winsys_cs *cs,
894 bool predicated,
895 uint64_t va, uint32_t ref,
896 uint32_t mask)
897 {
898 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, predicated));
899 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
900 radeon_emit(cs, va);
901 radeon_emit(cs, va >> 32);
902 radeon_emit(cs, ref); /* reference value */
903 radeon_emit(cs, mask); /* mask */
904 radeon_emit(cs, 4); /* poll interval */
905 }
906
907 static void
908 si_emit_acquire_mem(struct radeon_winsys_cs *cs,
909 bool is_mec,
910 bool predicated,
911 bool is_gfx9,
912 unsigned cp_coher_cntl)
913 {
914 if (is_mec || is_gfx9) {
915 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
916 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, predicated) |
917 PKT3_SHADER_TYPE_S(is_mec));
918 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
919 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
920 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
921 radeon_emit(cs, 0); /* CP_COHER_BASE */
922 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
923 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
924 } else {
925 /* ACQUIRE_MEM is only required on a compute ring. */
926 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, predicated));
927 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
928 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
929 radeon_emit(cs, 0); /* CP_COHER_BASE */
930 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
931 }
932 }
933
934 void
935 si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
936 enum chip_class chip_class,
937 uint32_t *flush_cnt,
938 uint64_t flush_va,
939 bool is_mec,
940 enum radv_cmd_flush_bits flush_bits)
941 {
942 unsigned cp_coher_cntl = 0;
943 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
944 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
945
946 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
947 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
948 if (flush_bits & RADV_CMD_FLAG_INV_SMEM_L1)
949 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
950
951 if (chip_class <= VI) {
952 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
953 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
954 S_0085F0_CB0_DEST_BASE_ENA(1) |
955 S_0085F0_CB1_DEST_BASE_ENA(1) |
956 S_0085F0_CB2_DEST_BASE_ENA(1) |
957 S_0085F0_CB3_DEST_BASE_ENA(1) |
958 S_0085F0_CB4_DEST_BASE_ENA(1) |
959 S_0085F0_CB5_DEST_BASE_ENA(1) |
960 S_0085F0_CB6_DEST_BASE_ENA(1) |
961 S_0085F0_CB7_DEST_BASE_ENA(1);
962
963 /* Necessary for DCC */
964 if (chip_class >= VI) {
965 si_cs_emit_write_event_eop(cs,
966 false,
967 chip_class,
968 is_mec,
969 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
970 0, 0, 0, 0, 0);
971 }
972 }
973 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
974 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
975 S_0085F0_DB_DEST_BASE_ENA(1);
976 }
977 }
978
979 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
980 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
981 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
982 }
983
984 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
985 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
986 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
987 }
988
989 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
990 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
991 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
992 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
993 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
994 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
995 }
996
997 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
998 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
999 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1000 }
1001
1002 if (chip_class >= GFX9 && flush_cb_db) {
1003 unsigned cb_db_event, tc_flags;
1004
1005 #if 0
1006 /* This breaks a bunch of:
1007 dEQP-VK.renderpass.dedicated_allocation.formats.d32_sfloat_s8_uint.input*.
1008 use the big hammer always.
1009 */
1010 /* Set the CB/DB flush event. */
1011 switch (flush_cb_db) {
1012 case RADV_CMD_FLAG_FLUSH_AND_INV_CB:
1013 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1014 break;
1015 case RADV_CMD_FLAG_FLUSH_AND_INV_DB:
1016 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1017 break;
1018 default:
1019 /* both CB & DB */
1020 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1021 }
1022 #else
1023 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1024 #endif
1025 /* These are the only allowed combinations. If you need to
1026 * do multiple operations at once, do them separately.
1027 * All operations that invalidate L2 also seem to invalidate
1028 * metadata. Volatile (VOL) and WC flushes are not listed here.
1029 *
1030 * TC | TC_WB = writeback & invalidate L2 & L1
1031 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1032 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1033 * TC | TC_NC = invalidate L2 for MTYPE == NC
1034 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1035 * TCL1 = invalidate L1
1036 */
1037 tc_flags = EVENT_TC_ACTION_ENA |
1038 EVENT_TC_MD_ACTION_ENA;
1039
1040 /* Ideally flush TC together with CB/DB. */
1041 if (flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) {
1042 /* Writeback and invalidate everything in L2 & L1. */
1043 tc_flags = EVENT_TC_ACTION_ENA |
1044 EVENT_TC_WB_ACTION_ENA;
1045
1046
1047 /* Clear the flags. */
1048 flush_bits &= ~(RADV_CMD_FLAG_INV_GLOBAL_L2 |
1049 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 |
1050 RADV_CMD_FLAG_INV_VMEM_L1);
1051 }
1052 assert(flush_cnt);
1053 uint32_t old_fence = (*flush_cnt)++;
1054
1055 si_cs_emit_write_event_eop(cs, false, chip_class, false, cb_db_event, tc_flags, 1,
1056 flush_va, old_fence, *flush_cnt);
1057 si_emit_wait_fence(cs, false, flush_va, *flush_cnt, 0xffffffff);
1058 }
1059
1060 /* VGT state sync */
1061 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1062 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1063 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1064 }
1065
1066 /* Make sure ME is idle (it executes most packets) before continuing.
1067 * This prevents read-after-write hazards between PFP and ME.
1068 */
1069 if ((cp_coher_cntl ||
1070 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1071 RADV_CMD_FLAG_INV_VMEM_L1 |
1072 RADV_CMD_FLAG_INV_GLOBAL_L2 |
1073 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) &&
1074 !is_mec) {
1075 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1076 radeon_emit(cs, 0);
1077 }
1078
1079 if ((flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) ||
1080 (chip_class <= CIK && (flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) {
1081 si_emit_acquire_mem(cs, is_mec, false, chip_class >= GFX9,
1082 cp_coher_cntl |
1083 S_0085F0_TC_ACTION_ENA(1) |
1084 S_0085F0_TCL1_ACTION_ENA(1) |
1085 S_0301F0_TC_WB_ACTION_ENA(chip_class >= VI));
1086 cp_coher_cntl = 0;
1087 } else {
1088 if(flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2) {
1089 /* WB = write-back
1090 * NC = apply to non-coherent MTYPEs
1091 * (i.e. MTYPE <= 1, which is what we use everywhere)
1092 *
1093 * WB doesn't work without NC.
1094 */
1095 si_emit_acquire_mem(cs, is_mec, false,
1096 chip_class >= GFX9,
1097 cp_coher_cntl |
1098 S_0301F0_TC_WB_ACTION_ENA(1) |
1099 S_0301F0_TC_NC_ACTION_ENA(1));
1100 cp_coher_cntl = 0;
1101 }
1102 if (flush_bits & RADV_CMD_FLAG_INV_VMEM_L1) {
1103 si_emit_acquire_mem(cs, is_mec,
1104 false, chip_class >= GFX9,
1105 cp_coher_cntl |
1106 S_0085F0_TCL1_ACTION_ENA(1));
1107 cp_coher_cntl = 0;
1108 }
1109 }
1110
1111 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1112 * Therefore, it should be last. Done in PFP.
1113 */
1114 if (cp_coher_cntl)
1115 si_emit_acquire_mem(cs, is_mec, false, chip_class >= GFX9, cp_coher_cntl);
1116 }
1117
1118 void
1119 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
1120 {
1121 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1122
1123 if (is_compute)
1124 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1125 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1126 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1127 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1128 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1129 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1130 RADV_CMD_FLAG_VGT_FLUSH);
1131
1132 if (!cmd_buffer->state.flush_bits)
1133 return;
1134
1135 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
1136 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1137
1138 uint32_t *ptr = NULL;
1139 uint64_t va = 0;
1140 if (chip_class == GFX9) {
1141 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) + cmd_buffer->gfx9_fence_offset;
1142 ptr = &cmd_buffer->gfx9_fence_idx;
1143 }
1144 si_cs_emit_cache_flush(cmd_buffer->cs,
1145 cmd_buffer->device->physical_device->rad_info.chip_class,
1146 ptr, va,
1147 radv_cmd_buffer_uses_mec(cmd_buffer),
1148 cmd_buffer->state.flush_bits);
1149
1150
1151 if (unlikely(cmd_buffer->device->trace_bo))
1152 radv_cmd_buffer_trace_emit(cmd_buffer);
1153
1154 cmd_buffer->state.flush_bits = 0;
1155 }
1156
1157 /* sets the CP predication state using a boolean stored at va */
1158 void
1159 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
1160 {
1161 uint32_t op = 0;
1162
1163 if (va)
1164 op = PRED_OP(PREDICATION_OP_BOOL64) | PREDICATION_DRAW_VISIBLE;
1165 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1166 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1167 radeon_emit(cmd_buffer->cs, op);
1168 radeon_emit(cmd_buffer->cs, va);
1169 radeon_emit(cmd_buffer->cs, va >> 32);
1170 } else {
1171 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1172 radeon_emit(cmd_buffer->cs, va);
1173 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1174 }
1175 }
1176
1177 /* Set this if you want the 3D engine to wait until CP DMA is done.
1178 * It should be set on the last CP DMA packet. */
1179 #define CP_DMA_SYNC (1 << 0)
1180
1181 /* Set this if the source data was used as a destination in a previous CP DMA
1182 * packet. It's for preventing a read-after-write (RAW) hazard between two
1183 * CP DMA packets. */
1184 #define CP_DMA_RAW_WAIT (1 << 1)
1185 #define CP_DMA_USE_L2 (1 << 2)
1186 #define CP_DMA_CLEAR (1 << 3)
1187
1188 /* Alignment for optimal performance. */
1189 #define SI_CPDMA_ALIGNMENT 32
1190
1191 /* The max number of bytes that can be copied per packet. */
1192 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1193 {
1194 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1195 S_414_BYTE_COUNT_GFX9(~0u) :
1196 S_414_BYTE_COUNT_GFX6(~0u);
1197
1198 /* make it aligned for optimal performance */
1199 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1200 }
1201
1202 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1203 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1204 * clear value.
1205 */
1206 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1207 uint64_t dst_va, uint64_t src_va,
1208 unsigned size, unsigned flags)
1209 {
1210 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1211 uint32_t header = 0, command = 0;
1212
1213 assert(size);
1214 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1215
1216 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1217 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1218 command |= S_414_BYTE_COUNT_GFX9(size);
1219 else
1220 command |= S_414_BYTE_COUNT_GFX6(size);
1221
1222 /* Sync flags. */
1223 if (flags & CP_DMA_SYNC)
1224 header |= S_411_CP_SYNC(1);
1225 else {
1226 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1227 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1228 else
1229 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1230 }
1231
1232 if (flags & CP_DMA_RAW_WAIT)
1233 command |= S_414_RAW_WAIT(1);
1234
1235 /* Src and dst flags. */
1236 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1237 !(flags & CP_DMA_CLEAR) &&
1238 src_va == dst_va)
1239 header |= S_411_DSL_SEL(V_411_NOWHERE); /* prefetch only */
1240 else if (flags & CP_DMA_USE_L2)
1241 header |= S_411_DSL_SEL(V_411_DST_ADDR_TC_L2);
1242
1243 if (flags & CP_DMA_CLEAR)
1244 header |= S_411_SRC_SEL(V_411_DATA);
1245 else if (flags & CP_DMA_USE_L2)
1246 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1247
1248 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1249 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1250 radeon_emit(cs, header);
1251 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1252 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1253 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1254 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1255 radeon_emit(cs, command);
1256 } else {
1257 assert(!(flags & CP_DMA_USE_L2));
1258 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1259 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1260 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1261 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1262 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1263 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1264 radeon_emit(cs, command);
1265 }
1266
1267 /* CP DMA is executed in ME, but index buffers are read by PFP.
1268 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1269 * indices. If we wanted to execute CP DMA in PFP, this packet
1270 * should precede it.
1271 */
1272 if ((flags & CP_DMA_SYNC) && cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1273 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1274 radeon_emit(cs, 0);
1275 }
1276
1277 if (unlikely(cmd_buffer->device->trace_bo))
1278 radv_cmd_buffer_trace_emit(cmd_buffer);
1279 }
1280
1281 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1282 unsigned size)
1283 {
1284 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1285 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1286
1287 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1288 aligned_size, CP_DMA_USE_L2);
1289 }
1290
1291 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1292 uint64_t remaining_size, unsigned *flags)
1293 {
1294
1295 /* Flush the caches for the first copy only.
1296 * Also wait for the previous CP DMA operations.
1297 */
1298 if (cmd_buffer->state.flush_bits) {
1299 si_emit_cache_flush(cmd_buffer);
1300 *flags |= CP_DMA_RAW_WAIT;
1301 }
1302
1303 /* Do the synchronization after the last dma, so that all data
1304 * is written to memory.
1305 */
1306 if (byte_count == remaining_size)
1307 *flags |= CP_DMA_SYNC;
1308 }
1309
1310 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1311 {
1312 uint64_t va;
1313 uint32_t offset;
1314 unsigned dma_flags = 0;
1315 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1316 void *ptr;
1317
1318 assert(size < SI_CPDMA_ALIGNMENT);
1319
1320 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1321
1322 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1323 va += offset;
1324
1325 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1326
1327 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1328 dma_flags);
1329 }
1330
1331 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1332 uint64_t src_va, uint64_t dest_va,
1333 uint64_t size)
1334 {
1335 uint64_t main_src_va, main_dest_va;
1336 uint64_t skipped_size = 0, realign_size = 0;
1337
1338
1339 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1340 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1341 /* If the size is not aligned, we must add a dummy copy at the end
1342 * just to align the internal counter. Otherwise, the DMA engine
1343 * would slow down by an order of magnitude for following copies.
1344 */
1345 if (size % SI_CPDMA_ALIGNMENT)
1346 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1347
1348 /* If the copy begins unaligned, we must start copying from the next
1349 * aligned block and the skipped part should be copied after everything
1350 * else has been copied. Only the src alignment matters, not dst.
1351 */
1352 if (src_va % SI_CPDMA_ALIGNMENT) {
1353 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1354 /* The main part will be skipped if the size is too small. */
1355 skipped_size = MIN2(skipped_size, size);
1356 size -= skipped_size;
1357 }
1358 }
1359 main_src_va = src_va + skipped_size;
1360 main_dest_va = dest_va + skipped_size;
1361
1362 while (size) {
1363 unsigned dma_flags = 0;
1364 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1365
1366 si_cp_dma_prepare(cmd_buffer, byte_count,
1367 size + skipped_size + realign_size,
1368 &dma_flags);
1369
1370 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1371 byte_count, dma_flags);
1372
1373 size -= byte_count;
1374 main_src_va += byte_count;
1375 main_dest_va += byte_count;
1376 }
1377
1378 if (skipped_size) {
1379 unsigned dma_flags = 0;
1380
1381 si_cp_dma_prepare(cmd_buffer, skipped_size,
1382 size + skipped_size + realign_size,
1383 &dma_flags);
1384
1385 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1386 skipped_size, dma_flags);
1387 }
1388 if (realign_size)
1389 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1390 }
1391
1392 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1393 uint64_t size, unsigned value)
1394 {
1395
1396 if (!size)
1397 return;
1398
1399 assert(va % 4 == 0 && size % 4 == 0);
1400
1401 while (size) {
1402 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1403 unsigned dma_flags = CP_DMA_CLEAR;
1404
1405 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1406
1407 /* Emit the clear packet. */
1408 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1409 dma_flags);
1410
1411 size -= byte_count;
1412 va += byte_count;
1413 }
1414 }
1415
1416 /* For MSAA sample positions. */
1417 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1418 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
1419 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1420 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1421 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1422
1423
1424 /* 2xMSAA
1425 * There are two locations (4, 4), (-4, -4). */
1426 const uint32_t eg_sample_locs_2x[4] = {
1427 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1428 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1429 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1430 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1431 };
1432 const unsigned eg_max_dist_2x = 4;
1433 /* 4xMSAA
1434 * There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
1435 const uint32_t eg_sample_locs_4x[4] = {
1436 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1437 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1438 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1439 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1440 };
1441 const unsigned eg_max_dist_4x = 6;
1442
1443 /* Cayman 8xMSAA */
1444 static const uint32_t cm_sample_locs_8x[] = {
1445 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1446 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1447 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1448 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1449 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1450 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1451 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1452 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1453 };
1454 static const unsigned cm_max_dist_8x = 8;
1455 /* Cayman 16xMSAA */
1456 static const uint32_t cm_sample_locs_16x[] = {
1457 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1458 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1459 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1460 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1461 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1462 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1463 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1464 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1465 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1466 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1467 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1468 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1469 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1470 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1471 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1472 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1473 };
1474 static const unsigned cm_max_dist_16x = 8;
1475
1476 unsigned radv_cayman_get_maxdist(int log_samples)
1477 {
1478 unsigned max_dist[] = {
1479 0,
1480 eg_max_dist_2x,
1481 eg_max_dist_4x,
1482 cm_max_dist_8x,
1483 cm_max_dist_16x
1484 };
1485 return max_dist[log_samples];
1486 }
1487
1488 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples)
1489 {
1490 switch (nr_samples) {
1491 default:
1492 case 1:
1493 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
1494 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
1495 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
1496 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
1497 break;
1498 case 2:
1499 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
1500 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
1501 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
1502 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
1503 break;
1504 case 4:
1505 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
1506 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
1507 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
1508 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
1509 break;
1510 case 8:
1511 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1512 radeon_emit(cs, cm_sample_locs_8x[0]);
1513 radeon_emit(cs, cm_sample_locs_8x[4]);
1514 radeon_emit(cs, 0);
1515 radeon_emit(cs, 0);
1516 radeon_emit(cs, cm_sample_locs_8x[1]);
1517 radeon_emit(cs, cm_sample_locs_8x[5]);
1518 radeon_emit(cs, 0);
1519 radeon_emit(cs, 0);
1520 radeon_emit(cs, cm_sample_locs_8x[2]);
1521 radeon_emit(cs, cm_sample_locs_8x[6]);
1522 radeon_emit(cs, 0);
1523 radeon_emit(cs, 0);
1524 radeon_emit(cs, cm_sample_locs_8x[3]);
1525 radeon_emit(cs, cm_sample_locs_8x[7]);
1526 break;
1527 case 16:
1528 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
1529 radeon_emit(cs, cm_sample_locs_16x[0]);
1530 radeon_emit(cs, cm_sample_locs_16x[4]);
1531 radeon_emit(cs, cm_sample_locs_16x[8]);
1532 radeon_emit(cs, cm_sample_locs_16x[12]);
1533 radeon_emit(cs, cm_sample_locs_16x[1]);
1534 radeon_emit(cs, cm_sample_locs_16x[5]);
1535 radeon_emit(cs, cm_sample_locs_16x[9]);
1536 radeon_emit(cs, cm_sample_locs_16x[13]);
1537 radeon_emit(cs, cm_sample_locs_16x[2]);
1538 radeon_emit(cs, cm_sample_locs_16x[6]);
1539 radeon_emit(cs, cm_sample_locs_16x[10]);
1540 radeon_emit(cs, cm_sample_locs_16x[14]);
1541 radeon_emit(cs, cm_sample_locs_16x[3]);
1542 radeon_emit(cs, cm_sample_locs_16x[7]);
1543 radeon_emit(cs, cm_sample_locs_16x[11]);
1544 radeon_emit(cs, cm_sample_locs_16x[15]);
1545 break;
1546 }
1547 }
1548
1549 static void radv_cayman_get_sample_position(struct radv_device *device,
1550 unsigned sample_count,
1551 unsigned sample_index, float *out_value)
1552 {
1553 int offset, index;
1554 struct {
1555 int idx:4;
1556 } val;
1557 switch (sample_count) {
1558 case 1:
1559 default:
1560 out_value[0] = out_value[1] = 0.5;
1561 break;
1562 case 2:
1563 offset = 4 * (sample_index * 2);
1564 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1565 out_value[0] = (float)(val.idx + 8) / 16.0f;
1566 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1567 out_value[1] = (float)(val.idx + 8) / 16.0f;
1568 break;
1569 case 4:
1570 offset = 4 * (sample_index * 2);
1571 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1572 out_value[0] = (float)(val.idx + 8) / 16.0f;
1573 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1574 out_value[1] = (float)(val.idx + 8) / 16.0f;
1575 break;
1576 case 8:
1577 offset = 4 * (sample_index % 4 * 2);
1578 index = (sample_index / 4) * 4;
1579 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1580 out_value[0] = (float)(val.idx + 8) / 16.0f;
1581 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1582 out_value[1] = (float)(val.idx + 8) / 16.0f;
1583 break;
1584 case 16:
1585 offset = 4 * (sample_index % 4 * 2);
1586 index = (sample_index / 4) * 4;
1587 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1588 out_value[0] = (float)(val.idx + 8) / 16.0f;
1589 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1590 out_value[1] = (float)(val.idx + 8) / 16.0f;
1591 break;
1592 }
1593 }
1594
1595 void radv_device_init_msaa(struct radv_device *device)
1596 {
1597 int i;
1598 radv_cayman_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1599
1600 for (i = 0; i < 2; i++)
1601 radv_cayman_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1602 for (i = 0; i < 4; i++)
1603 radv_cayman_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1604 for (i = 0; i < 8; i++)
1605 radv_cayman_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1606 for (i = 0; i < 16; i++)
1607 radv_cayman_get_sample_position(device, 16, i, device->sample_locations_16x[i]);
1608 }