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radv: only enable TC-compat HTILE for images readable by a shader
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for AMD GCN */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "radv_util.h"
35
36 static void
37 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
38 struct radeon_cmdbuf *cs,
39 unsigned raster_config,
40 unsigned raster_config_1)
41 {
42 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
43 unsigned raster_config_se[4];
44 unsigned se;
45
46 ac_get_harvested_configs(&physical_device->rad_info,
47 raster_config,
48 &raster_config_1,
49 raster_config_se);
50
51 for (se = 0; se < num_se; se++) {
52 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
53 if (physical_device->rad_info.chip_class < GFX7)
54 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
55 S_00802C_SE_INDEX(se) |
56 S_00802C_SH_BROADCAST_WRITES(1) |
57 S_00802C_INSTANCE_BROADCAST_WRITES(1));
58 else
59 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
60 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
61 S_030800_INSTANCE_BROADCAST_WRITES(1));
62 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
63 }
64
65 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
66 if (physical_device->rad_info.chip_class < GFX7)
67 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
68 S_00802C_SE_BROADCAST_WRITES(1) |
69 S_00802C_SH_BROADCAST_WRITES(1) |
70 S_00802C_INSTANCE_BROADCAST_WRITES(1));
71 else
72 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
73 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
74 S_030800_INSTANCE_BROADCAST_WRITES(1));
75
76 if (physical_device->rad_info.chip_class >= GFX7)
77 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
78 }
79
80 void
81 si_emit_compute(struct radv_physical_device *physical_device,
82 struct radeon_cmdbuf *cs)
83 {
84 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
85 radeon_emit(cs, 0);
86 radeon_emit(cs, 0);
87 radeon_emit(cs, 0);
88
89 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
90 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
91 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
92 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
93 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
94
95 if (physical_device->rad_info.chip_class >= GFX7) {
96 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
97 radeon_set_sh_reg_seq(cs,
98 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
99 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
100 S_00B858_SH1_CU_EN(0xffff));
101 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
102 S_00B858_SH1_CU_EN(0xffff));
103 }
104
105 if (physical_device->rad_info.chip_class >= GFX10)
106 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
107
108 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
109 * and is now per pipe, so it should be handled in the
110 * kernel if we want to use something other than the default value,
111 * which is now 0x22f.
112 */
113 if (physical_device->rad_info.chip_class <= GFX6) {
114 /* XXX: This should be:
115 * (number of compute units) * 4 * (waves per simd) - 1 */
116
117 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
118 0x190 /* Default value */);
119 }
120 }
121
122 /* 12.4 fixed-point */
123 static unsigned radv_pack_float_12p4(float x)
124 {
125 return x <= 0 ? 0 :
126 x >= 4096 ? 0xffff : x * 16;
127 }
128
129 static void
130 si_set_raster_config(struct radv_physical_device *physical_device,
131 struct radeon_cmdbuf *cs)
132 {
133 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
134 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
135 unsigned raster_config, raster_config_1;
136
137 ac_get_raster_config(&physical_device->rad_info,
138 &raster_config,
139 &raster_config_1, NULL);
140
141 /* Always use the default config when all backends are enabled
142 * (or when we failed to determine the enabled backends).
143 */
144 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
145 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
146 raster_config);
147 if (physical_device->rad_info.chip_class >= GFX7)
148 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
149 raster_config_1);
150 } else {
151 si_write_harvested_raster_configs(physical_device, cs,
152 raster_config,
153 raster_config_1);
154 }
155 }
156
157 void
158 si_emit_graphics(struct radv_physical_device *physical_device,
159 struct radeon_cmdbuf *cs)
160 {
161 bool has_clear_state = physical_device->rad_info.has_clear_state;
162 int i;
163
164 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
165 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
166 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
167
168 if (has_clear_state) {
169 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
170 radeon_emit(cs, 0);
171 }
172
173 if (physical_device->rad_info.chip_class <= GFX8)
174 si_set_raster_config(physical_device, cs);
175
176 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
177 if (!has_clear_state)
178 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
179
180 /* FIXME calculate these values somehow ??? */
181 if (physical_device->rad_info.chip_class <= GFX8) {
182 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
183 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
184 }
185
186 if (!has_clear_state) {
187 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
188 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
189 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
190 }
191
192 if (physical_device->rad_info.chip_class <= GFX9)
193 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
194 if (!has_clear_state)
195 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
196 if (physical_device->rad_info.chip_class < GFX7)
197 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
198 S_008A14_CLIP_VTX_REORDER_ENA(1));
199
200 if (!has_clear_state)
201 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
202
203 /* CLEAR_STATE doesn't clear these correctly on certain generations.
204 * I don't know why. Deduced by trial and error.
205 */
206 if (physical_device->rad_info.chip_class <= GFX7 || !has_clear_state) {
207 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
208 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
209 S_028204_WINDOW_OFFSET_DISABLE(1));
210 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
211 S_028240_WINDOW_OFFSET_DISABLE(1));
212 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
213 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
214 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
215 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
216 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
217 }
218
219 if (!has_clear_state) {
220 for (i = 0; i < 16; i++) {
221 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
222 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
223 }
224 }
225
226 if (!has_clear_state) {
227 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
228 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
229 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on GFX6 */
230 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
231 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
232 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
233 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
234 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
235 }
236
237 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
238 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
239 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
240
241 if (physical_device->rad_info.chip_class >= GFX10) {
242 radeon_set_context_reg(cs, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0);
243 radeon_set_uconfig_reg(cs, R_030964_GE_MAX_VTX_INDX, ~0);
244 radeon_set_uconfig_reg(cs, R_030924_GE_MIN_VTX_INDX, 0);
245 radeon_set_uconfig_reg(cs, R_030928_GE_INDX_OFFSET, 0);
246 radeon_set_uconfig_reg(cs, R_03097C_GE_STEREO_CNTL, 0);
247 radeon_set_uconfig_reg(cs, R_030988_GE_USER_VGPR_EN, 0);
248 } else if (physical_device->rad_info.chip_class == GFX9) {
249 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
250 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
251 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
252 } else {
253 /* These registers, when written, also overwrite the
254 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
255 * them. It would be an issue if there was another UMD
256 * changing them.
257 */
258 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
259 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
260 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
261 }
262
263 if (physical_device->rad_info.chip_class >= GFX7) {
264 if (physical_device->rad_info.chip_class >= GFX10) {
265 /* Logical CUs 16 - 31 */
266 radeon_set_sh_reg_idx(physical_device, cs, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
267 3, S_00B404_CU_EN(0xffff));
268 radeon_set_sh_reg_idx(physical_device, cs, R_00B104_SPI_SHADER_PGM_RSRC4_VS,
269 3, S_00B104_CU_EN(0xffff));
270 radeon_set_sh_reg_idx(physical_device, cs, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
271 3, S_00B004_CU_EN(0xffff));
272 }
273
274 if (physical_device->rad_info.chip_class >= GFX9) {
275 radeon_set_sh_reg_idx(physical_device, cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
276 3, S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
277 } else {
278 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
279 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
280 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
281 S_00B41C_WAVE_LIMIT(0x3F));
282 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
283 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
284 /* If this is 0, Bonaire can hang even if GS isn't being used.
285 * Other chips are unaffected. These are suboptimal values,
286 * but we don't use on-chip GS.
287 */
288 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
289 S_028A44_ES_VERTS_PER_SUBGRP(64) |
290 S_028A44_GS_PRIMS_PER_SUBGRP(4));
291 }
292
293 /* Compute LATE_ALLOC_VS.LIMIT. */
294 unsigned num_cu_per_sh = physical_device->rad_info.num_good_cu_per_sh;
295 unsigned late_alloc_wave64 = 0; /* The limit is per SH. */
296 unsigned late_alloc_wave64_gs = 0;
297 unsigned cu_mask_vs = 0xffff;
298 unsigned cu_mask_gs = 0xffff;
299
300 if (physical_device->rad_info.chip_class >= GFX10) {
301 /* For Wave32, the hw will launch twice the number of late
302 * alloc waves, so 1 == 2x wave32.
303 */
304 if (!physical_device->rad_info.use_late_alloc) {
305 late_alloc_wave64 = 0;
306 } else if (num_cu_per_sh <= 6) {
307 late_alloc_wave64 = num_cu_per_sh - 2;
308 } else {
309 late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
310
311 /* CU2 & CU3 disabled because of the dual CU design */
312 cu_mask_vs = 0xfff3;
313 cu_mask_gs = 0xfff3; /* NGG only */
314 }
315
316 late_alloc_wave64_gs = late_alloc_wave64;
317
318 /* Don't use late alloc for NGG on Navi14 due to a hw
319 * bug. If NGG is never used, enable all CUs.
320 */
321 if (!physical_device->use_ngg ||
322 physical_device->rad_info.family == CHIP_NAVI14) {
323 late_alloc_wave64_gs = 0;
324 cu_mask_gs = 0xffff;
325 }
326 } else {
327 if (!physical_device->rad_info.use_late_alloc) {
328 late_alloc_wave64 = 0;
329 } else if (num_cu_per_sh <= 4) {
330 /* Too few available compute units per SH.
331 * Disallowing VS to run on one CU could hurt
332 * us more than late VS allocation would help.
333 *
334 * 2 is the highest safe number that allows us
335 * to keep all CUs enabled.
336 */
337 late_alloc_wave64 = 2;
338 } else {
339 /* This is a good initial value, allowing 1
340 * late_alloc wave per SIMD on num_cu - 2.
341 */
342 late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
343 }
344
345 if (late_alloc_wave64 > 2)
346 cu_mask_vs = 0xfffe; /* 1 CU disabled */
347 }
348
349 radeon_set_sh_reg_idx(physical_device, cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
350 3, S_00B118_CU_EN(cu_mask_vs) |
351 S_00B118_WAVE_LIMIT(0x3F));
352 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
353 S_00B11C_LIMIT(late_alloc_wave64));
354
355 radeon_set_sh_reg_idx(physical_device, cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
356 3, S_00B21C_CU_EN(cu_mask_gs) | S_00B21C_WAVE_LIMIT(0x3F));
357
358 if (physical_device->rad_info.chip_class >= GFX10) {
359 radeon_set_sh_reg_idx(physical_device, cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
360 3, S_00B204_CU_EN(0xffff) |
361 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64_gs));
362 }
363
364 radeon_set_sh_reg_idx(physical_device, cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
365 3, S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
366 }
367
368 if (physical_device->rad_info.chip_class >= GFX10) {
369 /* Break up a pixel wave if it contains deallocs for more than
370 * half the parameter cache.
371 *
372 * To avoid a deadlock where pixel waves aren't launched
373 * because they're waiting for more pixels while the frontend
374 * is stuck waiting for PC space, the maximum allowed value is
375 * the size of the PC minus the largest possible allocation for
376 * a single primitive shader subgroup.
377 */
378 radeon_set_context_reg(cs, R_028C50_PA_SC_NGG_MODE_CNTL,
379 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
380 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
381
382 /* Enable CMASK/FMASK/HTILE/DCC caching in L2 for small chips. */
383 unsigned meta_write_policy, meta_read_policy;
384
385 /* TODO: investigate whether LRU improves performance on other chips too */
386 if (physical_device->rad_info.num_render_backends <= 4) {
387 meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */
388 meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */
389 } else {
390 meta_write_policy = V_02807C_CACHE_STREAM_WR; /* write combine */
391 meta_read_policy = V_02807C_CACHE_NOA_RD; /* don't cache reads */
392 }
393
394 radeon_set_context_reg(cs, R_02807C_DB_RMI_L2_CACHE_CONTROL,
395 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
396 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
397 S_02807C_HTILE_WR_POLICY(meta_write_policy) |
398 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
399 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
400 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
401 S_02807C_HTILE_RD_POLICY(meta_read_policy));
402
403 radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
404 S_028410_CMASK_WR_POLICY(meta_write_policy) |
405 S_028410_FMASK_WR_POLICY(meta_write_policy) |
406 S_028410_DCC_WR_POLICY(meta_write_policy) |
407 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
408 S_028410_CMASK_RD_POLICY(meta_read_policy) |
409 S_028410_FMASK_RD_POLICY(meta_read_policy) |
410 S_028410_DCC_RD_POLICY(meta_read_policy) |
411 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
412 radeon_set_context_reg(cs, R_028428_CB_COVERAGE_OUT_CONTROL, 0);
413
414 radeon_set_sh_reg(cs, R_00B0C0_SPI_SHADER_REQ_CTRL_PS,
415 S_00B0C0_SOFT_GROUPING_EN(1) |
416 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
417 radeon_set_sh_reg(cs, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
418
419 if (physical_device->rad_info.family == CHIP_NAVI10 ||
420 physical_device->rad_info.family == CHIP_NAVI12 ||
421 physical_device->rad_info.family == CHIP_NAVI14) {
422 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
423 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
424 radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
425 }
426
427 /* TODO: For culling, replace 128 with 256. */
428 radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC,
429 S_030980_OVERSUB_EN(physical_device->rad_info.use_late_alloc) |
430 S_030980_NUM_PC_LINES(128 * physical_device->rad_info.max_se - 1));
431 }
432
433 if (physical_device->rad_info.chip_class >= GFX9) {
434 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
435 S_028B50_ACCUM_ISOLINE(40) |
436 S_028B50_ACCUM_TRI(30) |
437 S_028B50_ACCUM_QUAD(24) |
438 S_028B50_DONUT_SPLIT(24) |
439 S_028B50_TRAP_SPLIT(6));
440 } else if (physical_device->rad_info.chip_class >= GFX8) {
441 uint32_t vgt_tess_distribution;
442
443 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
444 S_028B50_ACCUM_TRI(11) |
445 S_028B50_ACCUM_QUAD(11) |
446 S_028B50_DONUT_SPLIT(16);
447
448 if (physical_device->rad_info.family == CHIP_FIJI ||
449 physical_device->rad_info.family >= CHIP_POLARIS10)
450 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
451
452 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
453 vgt_tess_distribution);
454 } else if (!has_clear_state) {
455 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
456 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
457 }
458
459 if (physical_device->rad_info.chip_class >= GFX9) {
460 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
461 S_028C48_MAX_ALLOC_COUNT(physical_device->rad_info.pbb_max_alloc_count - 1) |
462 S_028C48_MAX_PRIM_PER_BATCH(1023));
463 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
464 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
465 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
466 }
467
468 unsigned tmp = (unsigned)(1.0 * 8.0);
469 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
470 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
471 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
472 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
473 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
474
475 if (!has_clear_state) {
476 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
477 S_028004_ZPASS_INCREMENT_DISABLE(1));
478 }
479
480 /* Enable the Polaris small primitive filter control.
481 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
482 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
483 * and AMDVLK doesn't have a workaround as well.
484 */
485 if (physical_device->rad_info.family >= CHIP_POLARIS10) {
486 unsigned small_prim_filter_cntl =
487 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
488 /* Workaround for a hw line bug. */
489 S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12);
490
491 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
492 small_prim_filter_cntl);
493 }
494
495 si_emit_compute(physical_device, cs);
496 }
497
498 void
499 cik_create_gfx_config(struct radv_device *device)
500 {
501 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX);
502 if (!cs)
503 return;
504
505 si_emit_graphics(device->physical_device, cs);
506
507 while (cs->cdw & 7) {
508 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
509 radeon_emit(cs, 0x80000000);
510 else
511 radeon_emit(cs, 0xffff1000);
512 }
513
514 device->gfx_init = device->ws->buffer_create(device->ws,
515 cs->cdw * 4, 4096,
516 RADEON_DOMAIN_GTT,
517 RADEON_FLAG_CPU_ACCESS|
518 RADEON_FLAG_NO_INTERPROCESS_SHARING |
519 RADEON_FLAG_READ_ONLY,
520 RADV_BO_PRIORITY_CS);
521 if (!device->gfx_init)
522 goto fail;
523
524 void *map = device->ws->buffer_map(device->gfx_init);
525 if (!map) {
526 device->ws->buffer_destroy(device->gfx_init);
527 device->gfx_init = NULL;
528 goto fail;
529 }
530 memcpy(map, cs->buf, cs->cdw * 4);
531
532 device->ws->buffer_unmap(device->gfx_init);
533 device->gfx_init_size_dw = cs->cdw;
534 fail:
535 device->ws->cs_destroy(cs);
536 }
537
538 static void
539 get_viewport_xform(const VkViewport *viewport,
540 float scale[3], float translate[3])
541 {
542 float x = viewport->x;
543 float y = viewport->y;
544 float half_width = 0.5f * viewport->width;
545 float half_height = 0.5f * viewport->height;
546 double n = viewport->minDepth;
547 double f = viewport->maxDepth;
548
549 scale[0] = half_width;
550 translate[0] = half_width + x;
551 scale[1] = half_height;
552 translate[1] = half_height + y;
553
554 scale[2] = (f - n);
555 translate[2] = n;
556 }
557
558 void
559 si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
560 int count, const VkViewport *viewports)
561 {
562 int i;
563
564 assert(count);
565 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
566 first_vp * 4 * 6, count * 6);
567
568 for (i = 0; i < count; i++) {
569 float scale[3], translate[3];
570
571
572 get_viewport_xform(&viewports[i], scale, translate);
573 radeon_emit(cs, fui(scale[0]));
574 radeon_emit(cs, fui(translate[0]));
575 radeon_emit(cs, fui(scale[1]));
576 radeon_emit(cs, fui(translate[1]));
577 radeon_emit(cs, fui(scale[2]));
578 radeon_emit(cs, fui(translate[2]));
579 }
580
581 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
582 first_vp * 4 * 2, count * 2);
583 for (i = 0; i < count; i++) {
584 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
585 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
586 radeon_emit(cs, fui(zmin));
587 radeon_emit(cs, fui(zmax));
588 }
589 }
590
591 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
592 {
593 float scale[3], translate[3];
594 VkRect2D rect;
595
596 get_viewport_xform(viewport, scale, translate);
597
598 rect.offset.x = translate[0] - fabs(scale[0]);
599 rect.offset.y = translate[1] - fabs(scale[1]);
600 rect.extent.width = ceilf(translate[0] + fabs(scale[0])) - rect.offset.x;
601 rect.extent.height = ceilf(translate[1] + fabs(scale[1])) - rect.offset.y;
602
603 return rect;
604 }
605
606 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
607 VkRect2D ret;
608 ret.offset.x = MAX2(a->offset.x, b->offset.x);
609 ret.offset.y = MAX2(a->offset.y, b->offset.y);
610 ret.extent.width = MIN2(a->offset.x + a->extent.width,
611 b->offset.x + b->extent.width) - ret.offset.x;
612 ret.extent.height = MIN2(a->offset.y + a->extent.height,
613 b->offset.y + b->extent.height) - ret.offset.y;
614 return ret;
615 }
616
617 void
618 si_write_scissors(struct radeon_cmdbuf *cs, int first,
619 int count, const VkRect2D *scissors,
620 const VkViewport *viewports, bool can_use_guardband)
621 {
622 int i;
623 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
624 const float max_range = 32767.0f;
625 if (!count)
626 return;
627
628 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
629 for (i = 0; i < count; i++) {
630 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
631 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
632
633 get_viewport_xform(viewports + i, scale, translate);
634 scale[0] = fabsf(scale[0]);
635 scale[1] = fabsf(scale[1]);
636
637 if (scale[0] < 0.5)
638 scale[0] = 0.5;
639 if (scale[1] < 0.5)
640 scale[1] = 0.5;
641
642 guardband_x = MIN2(guardband_x, (max_range - fabsf(translate[0])) / scale[0]);
643 guardband_y = MIN2(guardband_y, (max_range - fabsf(translate[1])) / scale[1]);
644
645 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
646 S_028250_TL_Y(scissor.offset.y) |
647 S_028250_WINDOW_OFFSET_DISABLE(1));
648 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
649 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
650 }
651 if (!can_use_guardband) {
652 guardband_x = 1.0;
653 guardband_y = 1.0;
654 }
655
656 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
657 radeon_emit(cs, fui(guardband_y));
658 radeon_emit(cs, fui(1.0));
659 radeon_emit(cs, fui(guardband_x));
660 radeon_emit(cs, fui(1.0));
661 }
662
663 static inline unsigned
664 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
665 {
666 if (num == 0)
667 return 0;
668
669 if (info->incr == 0)
670 return 0;
671
672 if (num < info->min)
673 return 0;
674
675 return 1 + ((num - info->min) / info->incr);
676 }
677
678 uint32_t
679 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
680 bool instanced_draw, bool indirect_draw,
681 bool count_from_stream_output,
682 uint32_t draw_vertex_count)
683 {
684 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
685 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
686 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
687 const unsigned max_primgroup_in_wave = 2;
688 /* SWITCH_ON_EOP(0) is always preferable. */
689 bool wd_switch_on_eop = false;
690 bool ia_switch_on_eop = false;
691 bool ia_switch_on_eoi = false;
692 bool partial_vs_wave = false;
693 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave;
694 bool multi_instances_smaller_than_primgroup;
695
696 multi_instances_smaller_than_primgroup = indirect_draw;
697 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
698 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
699 if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size)
700 multi_instances_smaller_than_primgroup = true;
701 }
702
703 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
704 partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
705
706 if (chip_class >= GFX7) {
707 wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.wd_switch_on_eop;
708
709 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
710 * We don't know that for indirect drawing, so treat it as
711 * always problematic. */
712 if (family == CHIP_HAWAII &&
713 (instanced_draw || indirect_draw))
714 wd_switch_on_eop = true;
715
716 /* Performance recommendation for 4 SE Gfx7-8 parts if
717 * instances are smaller than a primgroup.
718 * Assume indirect draws always use small instances.
719 * This is needed for good VS wave utilization.
720 */
721 if (chip_class <= GFX8 &&
722 info->max_se == 4 &&
723 multi_instances_smaller_than_primgroup)
724 wd_switch_on_eop = true;
725
726 /* Required on GFX7 and later. */
727 if (info->max_se > 2 && !wd_switch_on_eop)
728 ia_switch_on_eoi = true;
729
730 /* Required by Hawaii and, for some special cases, by GFX8. */
731 if (ia_switch_on_eoi &&
732 (family == CHIP_HAWAII ||
733 (chip_class == GFX8 &&
734 /* max primgroup in wave is always 2 - leave this for documentation */
735 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
736 partial_vs_wave = true;
737
738 /* Instancing bug on Bonaire. */
739 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
740 (instanced_draw || indirect_draw))
741 partial_vs_wave = true;
742
743 /* Hardware requirement when drawing primitives from a stream
744 * output buffer.
745 */
746 if (count_from_stream_output)
747 wd_switch_on_eop = true;
748
749 /* If the WD switch is false, the IA switch must be false too. */
750 assert(wd_switch_on_eop || !ia_switch_on_eop);
751 }
752 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
753 if (chip_class <= GFX8 && ia_switch_on_eoi)
754 partial_es_wave = true;
755
756 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
757 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
758 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
759 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
760 */
761 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
762 bool set_vgt_flush = indirect_draw;
763 if (!set_vgt_flush && instanced_draw) {
764 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
765 if (num_prims <= 1)
766 set_vgt_flush = true;
767 }
768 if (set_vgt_flush)
769 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
770 }
771 }
772
773 return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base |
774 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
775 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
776 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
777 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
778 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= GFX7 ? wd_switch_on_eop : 0);
779
780 }
781
782 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
783 enum chip_class chip_class,
784 bool is_mec,
785 unsigned event, unsigned event_flags,
786 unsigned dst_sel, unsigned data_sel,
787 uint64_t va,
788 uint32_t new_fence,
789 uint64_t gfx9_eop_bug_va)
790 {
791 unsigned op = EVENT_TYPE(event) |
792 EVENT_INDEX(event == V_028A90_CS_DONE ||
793 event == V_028A90_PS_DONE ? 6 : 5) |
794 event_flags;
795 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
796 unsigned sel = EOP_DST_SEL(dst_sel) |
797 EOP_DATA_SEL(data_sel);
798
799 /* Wait for write confirmation before writing data, but don't send
800 * an interrupt. */
801 if (data_sel != EOP_DATA_SEL_DISCARD)
802 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
803
804 if (chip_class >= GFX9 || is_gfx8_mec) {
805 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
806 * counters) must immediately precede every timestamp event to
807 * prevent a GPU hang on GFX9.
808 */
809 if (chip_class == GFX9 && !is_mec) {
810 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
811 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
812 radeon_emit(cs, gfx9_eop_bug_va);
813 radeon_emit(cs, gfx9_eop_bug_va >> 32);
814 }
815
816 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false));
817 radeon_emit(cs, op);
818 radeon_emit(cs, sel);
819 radeon_emit(cs, va); /* address lo */
820 radeon_emit(cs, va >> 32); /* address hi */
821 radeon_emit(cs, new_fence); /* immediate data lo */
822 radeon_emit(cs, 0); /* immediate data hi */
823 if (!is_gfx8_mec)
824 radeon_emit(cs, 0); /* unused */
825 } else {
826 if (chip_class == GFX7 ||
827 chip_class == GFX8) {
828 /* Two EOP events are required to make all engines go idle
829 * (and optional cache flushes executed) before the timestamp
830 * is written.
831 */
832 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
833 radeon_emit(cs, op);
834 radeon_emit(cs, va);
835 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
836 radeon_emit(cs, 0); /* immediate data */
837 radeon_emit(cs, 0); /* unused */
838 }
839
840 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
841 radeon_emit(cs, op);
842 radeon_emit(cs, va);
843 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
844 radeon_emit(cs, new_fence); /* immediate data */
845 radeon_emit(cs, 0); /* unused */
846 }
847 }
848
849 void
850 radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
851 uint32_t ref, uint32_t mask)
852 {
853 assert(op == WAIT_REG_MEM_EQUAL ||
854 op == WAIT_REG_MEM_NOT_EQUAL ||
855 op == WAIT_REG_MEM_GREATER_OR_EQUAL);
856
857 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false));
858 radeon_emit(cs, op | WAIT_REG_MEM_MEM_SPACE(1));
859 radeon_emit(cs, va);
860 radeon_emit(cs, va >> 32);
861 radeon_emit(cs, ref); /* reference value */
862 radeon_emit(cs, mask); /* mask */
863 radeon_emit(cs, 4); /* poll interval */
864 }
865
866 static void
867 si_emit_acquire_mem(struct radeon_cmdbuf *cs,
868 bool is_mec,
869 bool is_gfx9,
870 unsigned cp_coher_cntl)
871 {
872 if (is_mec || is_gfx9) {
873 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
874 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) |
875 PKT3_SHADER_TYPE_S(is_mec));
876 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
877 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
878 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
879 radeon_emit(cs, 0); /* CP_COHER_BASE */
880 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
881 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
882 } else {
883 /* ACQUIRE_MEM is only required on a compute ring. */
884 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false));
885 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
886 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
887 radeon_emit(cs, 0); /* CP_COHER_BASE */
888 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
889 }
890 }
891
892 static void
893 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
894 enum chip_class chip_class,
895 uint32_t *flush_cnt,
896 uint64_t flush_va,
897 bool is_mec,
898 enum radv_cmd_flush_bits flush_bits,
899 uint64_t gfx9_eop_bug_va)
900 {
901 uint32_t gcr_cntl = 0;
902 unsigned cb_db_event = 0;
903
904 /* We don't need these. */
905 assert(!(flush_bits & (RADV_CMD_FLAG_VGT_STREAMOUT_SYNC)));
906
907 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
908 gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
909 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE) {
910 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
911 * to FORWARD when both L1 and L2 are written out (WB or INV).
912 */
913 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
914 }
915 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE)
916 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
917 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
918 /* Writeback and invalidate everything in L2. */
919 gcr_cntl |= S_586_GL2_INV(1) | S_586_GL2_WB(1) |
920 S_586_GLM_INV(1) | S_586_GLM_WB(1);
921 } else if (flush_bits & RADV_CMD_FLAG_WB_L2) {
922 /* Writeback but do not invalidate.
923 * GLM doesn't support WB alone. If WB is set, INV must be set too.
924 */
925 gcr_cntl |= S_586_GL2_WB(1) |
926 S_586_GLM_WB(1) | S_586_GLM_INV(1);
927 }
928
929 /* TODO: Implement this new flag for GFX9+.
930 else if (flush_bits & RADV_CMD_FLAG_INV_L2_METADATA)
931 gcr_cntl |= S_586_GLM_INV(1) | S_586_GLM_WB(1);
932 */
933
934 if (flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
935 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_CB_META */
936 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
937 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
938 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
939 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
940 EVENT_INDEX(0));
941 }
942
943 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_DB_META ? */
944 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
945 /* Flush HTILE. Will wait for idle later. */
946 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
947 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) |
948 EVENT_INDEX(0));
949 }
950
951 /* First flush CB/DB, then L1/L2. */
952 gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
953
954 if ((flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) ==
955 (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
956 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
957 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
958 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
959 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
960 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
961 } else {
962 assert(0);
963 }
964 } else {
965 /* Wait for graphics shaders to go idle if requested. */
966 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
967 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
968 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
969 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
970 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
971 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
972 }
973 }
974
975 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
976 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
977 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
978 }
979
980 if (cb_db_event) {
981 /* CB/DB flush and invalidate (or possibly just a wait for a
982 * meta flush) via RELEASE_MEM.
983 *
984 * Combine this with other cache flushes when possible; this
985 * requires affected shaders to be idle, so do it after the
986 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
987 * implied).
988 */
989 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
990 unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
991 unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
992 unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
993 unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
994 assert(G_586_GL2_US(gcr_cntl) == 0);
995 assert(G_586_GL2_RANGE(gcr_cntl) == 0);
996 assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
997 unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
998 unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
999 unsigned gcr_seq = G_586_SEQ(gcr_cntl);
1000
1001 gcr_cntl &= C_586_GLM_WB &
1002 C_586_GLM_INV &
1003 C_586_GLV_INV &
1004 C_586_GL1_INV &
1005 C_586_GL2_INV &
1006 C_586_GL2_WB; /* keep SEQ */
1007
1008 assert(flush_cnt);
1009 (*flush_cnt)++;
1010
1011 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event,
1012 S_490_GLM_WB(glm_wb) |
1013 S_490_GLM_INV(glm_inv) |
1014 S_490_GLV_INV(glv_inv) |
1015 S_490_GL1_INV(gl1_inv) |
1016 S_490_GL2_INV(gl2_inv) |
1017 S_490_GL2_WB(gl2_wb) |
1018 S_490_SEQ(gcr_seq),
1019 EOP_DST_SEL_MEM,
1020 EOP_DATA_SEL_VALUE_32BIT,
1021 flush_va, *flush_cnt,
1022 gfx9_eop_bug_va);
1023
1024 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
1025 *flush_cnt, 0xffffffff);
1026 }
1027
1028 /* VGT state sync */
1029 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1030 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1031 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1032 }
1033
1034 /* Ignore fields that only modify the behavior of other fields. */
1035 if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
1036 /* Flush caches and wait for the caches to assert idle.
1037 * The cache flush is executed in the ME, but the PFP waits
1038 * for completion.
1039 */
1040 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
1041 radeon_emit(cs, 0); /* CP_COHER_CNTL */
1042 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1043 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1044 radeon_emit(cs, 0); /* CP_COHER_BASE */
1045 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1046 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1047 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
1048 } else if ((cb_db_event ||
1049 (flush_bits & (RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1050 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1051 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)))
1052 && !is_mec) {
1053 /* We need to ensure that PFP waits as well. */
1054 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1055 radeon_emit(cs, 0);
1056 }
1057
1058 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1059 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1060 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1061 EVENT_INDEX(0));
1062 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1063 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1064 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1065 EVENT_INDEX(0));
1066 }
1067 }
1068
1069 void
1070 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1071 enum chip_class chip_class,
1072 uint32_t *flush_cnt,
1073 uint64_t flush_va,
1074 bool is_mec,
1075 enum radv_cmd_flush_bits flush_bits,
1076 uint64_t gfx9_eop_bug_va)
1077 {
1078 unsigned cp_coher_cntl = 0;
1079 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1080 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
1081
1082 if (chip_class >= GFX10) {
1083 /* GFX10 cache flush handling is quite different. */
1084 gfx10_cs_emit_cache_flush(cs, chip_class, flush_cnt, flush_va,
1085 is_mec, flush_bits, gfx9_eop_bug_va);
1086 return;
1087 }
1088
1089 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
1090 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1091 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE)
1092 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1093
1094 if (chip_class <= GFX8) {
1095 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
1096 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
1097 S_0085F0_CB0_DEST_BASE_ENA(1) |
1098 S_0085F0_CB1_DEST_BASE_ENA(1) |
1099 S_0085F0_CB2_DEST_BASE_ENA(1) |
1100 S_0085F0_CB3_DEST_BASE_ENA(1) |
1101 S_0085F0_CB4_DEST_BASE_ENA(1) |
1102 S_0085F0_CB5_DEST_BASE_ENA(1) |
1103 S_0085F0_CB6_DEST_BASE_ENA(1) |
1104 S_0085F0_CB7_DEST_BASE_ENA(1);
1105
1106 /* Necessary for DCC */
1107 if (chip_class >= GFX8) {
1108 si_cs_emit_write_event_eop(cs,
1109 chip_class,
1110 is_mec,
1111 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
1112 0,
1113 EOP_DST_SEL_MEM,
1114 EOP_DATA_SEL_DISCARD,
1115 0, 0,
1116 gfx9_eop_bug_va);
1117 }
1118 }
1119 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
1120 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
1121 S_0085F0_DB_DEST_BASE_ENA(1);
1122 }
1123 }
1124
1125 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
1126 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1127 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1128 }
1129
1130 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
1131 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1132 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1133 }
1134
1135 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
1136 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1137 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1138 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
1139 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1140 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1141 }
1142
1143 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
1144 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1145 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1146 }
1147
1148 if (chip_class == GFX9 && flush_cb_db) {
1149 unsigned cb_db_event, tc_flags;
1150
1151 /* Set the CB/DB flush event. */
1152 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1153
1154 /* These are the only allowed combinations. If you need to
1155 * do multiple operations at once, do them separately.
1156 * All operations that invalidate L2 also seem to invalidate
1157 * metadata. Volatile (VOL) and WC flushes are not listed here.
1158 *
1159 * TC | TC_WB = writeback & invalidate L2 & L1
1160 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1161 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1162 * TC | TC_NC = invalidate L2 for MTYPE == NC
1163 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1164 * TCL1 = invalidate L1
1165 */
1166 tc_flags = EVENT_TC_ACTION_ENA |
1167 EVENT_TC_MD_ACTION_ENA;
1168
1169 /* Ideally flush TC together with CB/DB. */
1170 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
1171 /* Writeback and invalidate everything in L2 & L1. */
1172 tc_flags = EVENT_TC_ACTION_ENA |
1173 EVENT_TC_WB_ACTION_ENA;
1174
1175
1176 /* Clear the flags. */
1177 flush_bits &= ~(RADV_CMD_FLAG_INV_L2 |
1178 RADV_CMD_FLAG_WB_L2 |
1179 RADV_CMD_FLAG_INV_VCACHE);
1180 }
1181 assert(flush_cnt);
1182 (*flush_cnt)++;
1183
1184 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags,
1185 EOP_DST_SEL_MEM,
1186 EOP_DATA_SEL_VALUE_32BIT,
1187 flush_va, *flush_cnt,
1188 gfx9_eop_bug_va);
1189 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
1190 *flush_cnt, 0xffffffff);
1191 }
1192
1193 /* VGT state sync */
1194 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1195 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1196 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1197 }
1198
1199 /* VGT streamout state sync */
1200 if (flush_bits & RADV_CMD_FLAG_VGT_STREAMOUT_SYNC) {
1201 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1202 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1203 }
1204
1205 /* Make sure ME is idle (it executes most packets) before continuing.
1206 * This prevents read-after-write hazards between PFP and ME.
1207 */
1208 if ((cp_coher_cntl ||
1209 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1210 RADV_CMD_FLAG_INV_VCACHE |
1211 RADV_CMD_FLAG_INV_L2 |
1212 RADV_CMD_FLAG_WB_L2))) &&
1213 !is_mec) {
1214 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1215 radeon_emit(cs, 0);
1216 }
1217
1218 if ((flush_bits & RADV_CMD_FLAG_INV_L2) ||
1219 (chip_class <= GFX7 && (flush_bits & RADV_CMD_FLAG_WB_L2))) {
1220 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9,
1221 cp_coher_cntl |
1222 S_0085F0_TC_ACTION_ENA(1) |
1223 S_0085F0_TCL1_ACTION_ENA(1) |
1224 S_0301F0_TC_WB_ACTION_ENA(chip_class >= GFX8));
1225 cp_coher_cntl = 0;
1226 } else {
1227 if(flush_bits & RADV_CMD_FLAG_WB_L2) {
1228 /* WB = write-back
1229 * NC = apply to non-coherent MTYPEs
1230 * (i.e. MTYPE <= 1, which is what we use everywhere)
1231 *
1232 * WB doesn't work without NC.
1233 */
1234 si_emit_acquire_mem(cs, is_mec,
1235 chip_class == GFX9,
1236 cp_coher_cntl |
1237 S_0301F0_TC_WB_ACTION_ENA(1) |
1238 S_0301F0_TC_NC_ACTION_ENA(1));
1239 cp_coher_cntl = 0;
1240 }
1241 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE) {
1242 si_emit_acquire_mem(cs, is_mec,
1243 chip_class == GFX9,
1244 cp_coher_cntl |
1245 S_0085F0_TCL1_ACTION_ENA(1));
1246 cp_coher_cntl = 0;
1247 }
1248 }
1249
1250 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1251 * Therefore, it should be last. Done in PFP.
1252 */
1253 if (cp_coher_cntl)
1254 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9, cp_coher_cntl);
1255
1256 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1257 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1258 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1259 EVENT_INDEX(0));
1260 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1261 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1262 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1263 EVENT_INDEX(0));
1264 }
1265 }
1266
1267 void
1268 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
1269 {
1270 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1271
1272 if (is_compute)
1273 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1274 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1275 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1276 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1277 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1278 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1279 RADV_CMD_FLAG_VGT_FLUSH |
1280 RADV_CMD_FLAG_START_PIPELINE_STATS |
1281 RADV_CMD_FLAG_STOP_PIPELINE_STATS);
1282
1283 if (!cmd_buffer->state.flush_bits)
1284 return;
1285
1286 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1287
1288 si_cs_emit_cache_flush(cmd_buffer->cs,
1289 cmd_buffer->device->physical_device->rad_info.chip_class,
1290 &cmd_buffer->gfx9_fence_idx,
1291 cmd_buffer->gfx9_fence_va,
1292 radv_cmd_buffer_uses_mec(cmd_buffer),
1293 cmd_buffer->state.flush_bits,
1294 cmd_buffer->gfx9_eop_bug_va);
1295
1296
1297 if (unlikely(cmd_buffer->device->trace_bo))
1298 radv_cmd_buffer_trace_emit(cmd_buffer);
1299
1300 /* Clear the caches that have been flushed to avoid syncing too much
1301 * when there is some pending active queries.
1302 */
1303 cmd_buffer->active_query_flush_bits &= ~cmd_buffer->state.flush_bits;
1304
1305 cmd_buffer->state.flush_bits = 0;
1306
1307 /* If the driver used a compute shader for resetting a query pool, it
1308 * should be finished at this point.
1309 */
1310 cmd_buffer->pending_reset_query = false;
1311 }
1312
1313 /* sets the CP predication state using a boolean stored at va */
1314 void
1315 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1316 bool draw_visible, uint64_t va)
1317 {
1318 uint32_t op = 0;
1319
1320 if (va) {
1321 op = PRED_OP(PREDICATION_OP_BOOL64);
1322
1323 /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
1324 * zero, all rendering commands are discarded. Otherwise, they
1325 * are discarded if the value is non zero.
1326 */
1327 op |= draw_visible ? PREDICATION_DRAW_VISIBLE :
1328 PREDICATION_DRAW_NOT_VISIBLE;
1329 }
1330 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1331 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1332 radeon_emit(cmd_buffer->cs, op);
1333 radeon_emit(cmd_buffer->cs, va);
1334 radeon_emit(cmd_buffer->cs, va >> 32);
1335 } else {
1336 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1337 radeon_emit(cmd_buffer->cs, va);
1338 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1339 }
1340 }
1341
1342 /* Set this if you want the 3D engine to wait until CP DMA is done.
1343 * It should be set on the last CP DMA packet. */
1344 #define CP_DMA_SYNC (1 << 0)
1345
1346 /* Set this if the source data was used as a destination in a previous CP DMA
1347 * packet. It's for preventing a read-after-write (RAW) hazard between two
1348 * CP DMA packets. */
1349 #define CP_DMA_RAW_WAIT (1 << 1)
1350 #define CP_DMA_USE_L2 (1 << 2)
1351 #define CP_DMA_CLEAR (1 << 3)
1352
1353 /* Alignment for optimal performance. */
1354 #define SI_CPDMA_ALIGNMENT 32
1355
1356 /* The max number of bytes that can be copied per packet. */
1357 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1358 {
1359 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1360 S_414_BYTE_COUNT_GFX9(~0u) :
1361 S_414_BYTE_COUNT_GFX6(~0u);
1362
1363 /* make it aligned for optimal performance */
1364 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1365 }
1366
1367 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1368 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1369 * clear value.
1370 */
1371 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1372 uint64_t dst_va, uint64_t src_va,
1373 unsigned size, unsigned flags)
1374 {
1375 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1376 uint32_t header = 0, command = 0;
1377
1378 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1379
1380 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1381 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1382 command |= S_414_BYTE_COUNT_GFX9(size);
1383 else
1384 command |= S_414_BYTE_COUNT_GFX6(size);
1385
1386 /* Sync flags. */
1387 if (flags & CP_DMA_SYNC)
1388 header |= S_411_CP_SYNC(1);
1389 else {
1390 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1391 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1392 else
1393 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1394 }
1395
1396 if (flags & CP_DMA_RAW_WAIT)
1397 command |= S_414_RAW_WAIT(1);
1398
1399 /* Src and dst flags. */
1400 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1401 !(flags & CP_DMA_CLEAR) &&
1402 src_va == dst_va)
1403 header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
1404 else if (flags & CP_DMA_USE_L2)
1405 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
1406
1407 if (flags & CP_DMA_CLEAR)
1408 header |= S_411_SRC_SEL(V_411_DATA);
1409 else if (flags & CP_DMA_USE_L2)
1410 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1411
1412 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1413 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1414 radeon_emit(cs, header);
1415 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1416 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1417 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1418 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1419 radeon_emit(cs, command);
1420 } else {
1421 assert(!(flags & CP_DMA_USE_L2));
1422 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1423 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1424 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1425 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1426 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1427 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1428 radeon_emit(cs, command);
1429 }
1430
1431 /* CP DMA is executed in ME, but index buffers are read by PFP.
1432 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1433 * indices. If we wanted to execute CP DMA in PFP, this packet
1434 * should precede it.
1435 */
1436 if (flags & CP_DMA_SYNC) {
1437 if (cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1438 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1439 radeon_emit(cs, 0);
1440 }
1441
1442 /* CP will see the sync flag and wait for all DMAs to complete. */
1443 cmd_buffer->state.dma_is_busy = false;
1444 }
1445
1446 if (unlikely(cmd_buffer->device->trace_bo))
1447 radv_cmd_buffer_trace_emit(cmd_buffer);
1448 }
1449
1450 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1451 unsigned size)
1452 {
1453 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1454 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1455
1456 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1457 aligned_size, CP_DMA_USE_L2);
1458 }
1459
1460 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1461 uint64_t remaining_size, unsigned *flags)
1462 {
1463
1464 /* Flush the caches for the first copy only.
1465 * Also wait for the previous CP DMA operations.
1466 */
1467 if (cmd_buffer->state.flush_bits) {
1468 si_emit_cache_flush(cmd_buffer);
1469 *flags |= CP_DMA_RAW_WAIT;
1470 }
1471
1472 /* Do the synchronization after the last dma, so that all data
1473 * is written to memory.
1474 */
1475 if (byte_count == remaining_size)
1476 *flags |= CP_DMA_SYNC;
1477 }
1478
1479 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1480 {
1481 uint64_t va;
1482 uint32_t offset;
1483 unsigned dma_flags = 0;
1484 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1485 void *ptr;
1486
1487 assert(size < SI_CPDMA_ALIGNMENT);
1488
1489 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1490
1491 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1492 va += offset;
1493
1494 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1495
1496 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1497 dma_flags);
1498 }
1499
1500 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1501 uint64_t src_va, uint64_t dest_va,
1502 uint64_t size)
1503 {
1504 uint64_t main_src_va, main_dest_va;
1505 uint64_t skipped_size = 0, realign_size = 0;
1506
1507 /* Assume that we are not going to sync after the last DMA operation. */
1508 cmd_buffer->state.dma_is_busy = true;
1509
1510 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1511 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1512 /* If the size is not aligned, we must add a dummy copy at the end
1513 * just to align the internal counter. Otherwise, the DMA engine
1514 * would slow down by an order of magnitude for following copies.
1515 */
1516 if (size % SI_CPDMA_ALIGNMENT)
1517 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1518
1519 /* If the copy begins unaligned, we must start copying from the next
1520 * aligned block and the skipped part should be copied after everything
1521 * else has been copied. Only the src alignment matters, not dst.
1522 */
1523 if (src_va % SI_CPDMA_ALIGNMENT) {
1524 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1525 /* The main part will be skipped if the size is too small. */
1526 skipped_size = MIN2(skipped_size, size);
1527 size -= skipped_size;
1528 }
1529 }
1530 main_src_va = src_va + skipped_size;
1531 main_dest_va = dest_va + skipped_size;
1532
1533 while (size) {
1534 unsigned dma_flags = 0;
1535 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1536
1537 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1538 /* DMA operations via L2 are coherent and faster.
1539 * TODO: GFX7-GFX9 should also support this but it
1540 * requires tests/benchmarks.
1541 */
1542 dma_flags |= CP_DMA_USE_L2;
1543 }
1544
1545 si_cp_dma_prepare(cmd_buffer, byte_count,
1546 size + skipped_size + realign_size,
1547 &dma_flags);
1548
1549 dma_flags &= ~CP_DMA_SYNC;
1550
1551 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1552 byte_count, dma_flags);
1553
1554 size -= byte_count;
1555 main_src_va += byte_count;
1556 main_dest_va += byte_count;
1557 }
1558
1559 if (skipped_size) {
1560 unsigned dma_flags = 0;
1561
1562 si_cp_dma_prepare(cmd_buffer, skipped_size,
1563 size + skipped_size + realign_size,
1564 &dma_flags);
1565
1566 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1567 skipped_size, dma_flags);
1568 }
1569 if (realign_size)
1570 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1571 }
1572
1573 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1574 uint64_t size, unsigned value)
1575 {
1576
1577 if (!size)
1578 return;
1579
1580 assert(va % 4 == 0 && size % 4 == 0);
1581
1582 /* Assume that we are not going to sync after the last DMA operation. */
1583 cmd_buffer->state.dma_is_busy = true;
1584
1585 while (size) {
1586 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1587 unsigned dma_flags = CP_DMA_CLEAR;
1588
1589 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1590 /* DMA operations via L2 are coherent and faster.
1591 * TODO: GFX7-GFX9 should also support this but it
1592 * requires tests/benchmarks.
1593 */
1594 dma_flags |= CP_DMA_USE_L2;
1595 }
1596
1597 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1598
1599 /* Emit the clear packet. */
1600 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1601 dma_flags);
1602
1603 size -= byte_count;
1604 va += byte_count;
1605 }
1606 }
1607
1608 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
1609 {
1610 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX7)
1611 return;
1612
1613 if (!cmd_buffer->state.dma_is_busy)
1614 return;
1615
1616 /* Issue a dummy DMA that copies zero bytes.
1617 *
1618 * The DMA engine will see that there's no work to do and skip this
1619 * DMA request, however, the CP will see the sync flag and still wait
1620 * for all DMAs to complete.
1621 */
1622 si_emit_cp_dma(cmd_buffer, 0, 0, 0, CP_DMA_SYNC);
1623
1624 cmd_buffer->state.dma_is_busy = false;
1625 }
1626
1627 /* For MSAA sample positions. */
1628 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1629 ((((unsigned)(s0x) & 0xf) << 0) | (((unsigned)(s0y) & 0xf) << 4) | \
1630 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1631 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1632 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1633
1634 /* For obtaining location coordinates from registers */
1635 #define SEXT4(x) ((int)((x) | ((x) & 0x8 ? 0xfffffff0 : 0)))
1636 #define GET_SFIELD(reg, index) SEXT4(((reg) >> ((index) * 4)) & 0xf)
1637 #define GET_SX(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2)
1638 #define GET_SY(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2 + 1)
1639
1640 /* 1x MSAA */
1641 static const uint32_t sample_locs_1x =
1642 FILL_SREG(0, 0, 0, 0, 0, 0, 0, 0);
1643 static const unsigned max_dist_1x = 0;
1644 static const uint64_t centroid_priority_1x = 0x0000000000000000ull;
1645
1646 /* 2xMSAA */
1647 static const uint32_t sample_locs_2x =
1648 FILL_SREG(4,4, -4, -4, 0, 0, 0, 0);
1649 static const unsigned max_dist_2x = 4;
1650 static const uint64_t centroid_priority_2x = 0x1010101010101010ull;
1651
1652 /* 4xMSAA */
1653 static const uint32_t sample_locs_4x =
1654 FILL_SREG(-2,-6, 6, -2, -6, 2, 2, 6);
1655 static const unsigned max_dist_4x = 6;
1656 static const uint64_t centroid_priority_4x = 0x3210321032103210ull;
1657
1658 /* 8xMSAA */
1659 static const uint32_t sample_locs_8x[] = {
1660 FILL_SREG( 1,-3, -1, 3, 5, 1, -3,-5),
1661 FILL_SREG(-5, 5, -7,-1, 3, 7, 7,-7),
1662 /* The following are unused by hardware, but we emit them to IBs
1663 * instead of multiple SET_CONTEXT_REG packets. */
1664 0,
1665 0,
1666 };
1667 static const unsigned max_dist_8x = 7;
1668 static const uint64_t centroid_priority_8x = 0x7654321076543210ull;
1669
1670 unsigned radv_get_default_max_sample_dist(int log_samples)
1671 {
1672 unsigned max_dist[] = {
1673 max_dist_1x,
1674 max_dist_2x,
1675 max_dist_4x,
1676 max_dist_8x,
1677 };
1678 return max_dist[log_samples];
1679 }
1680
1681 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples)
1682 {
1683 switch (nr_samples) {
1684 default:
1685 case 1:
1686 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1687 radeon_emit(cs, (uint32_t)centroid_priority_1x);
1688 radeon_emit(cs, centroid_priority_1x >> 32);
1689 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_1x);
1690 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_1x);
1691 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_1x);
1692 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_1x);
1693 break;
1694 case 2:
1695 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1696 radeon_emit(cs, (uint32_t)centroid_priority_2x);
1697 radeon_emit(cs, centroid_priority_2x >> 32);
1698 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x);
1699 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x);
1700 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x);
1701 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x);
1702 break;
1703 case 4:
1704 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1705 radeon_emit(cs, (uint32_t)centroid_priority_4x);
1706 radeon_emit(cs, centroid_priority_4x >> 32);
1707 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x);
1708 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x);
1709 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x);
1710 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x);
1711 break;
1712 case 8:
1713 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1714 radeon_emit(cs, (uint32_t)centroid_priority_8x);
1715 radeon_emit(cs, centroid_priority_8x >> 32);
1716 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1717 radeon_emit_array(cs, sample_locs_8x, 4);
1718 radeon_emit_array(cs, sample_locs_8x, 4);
1719 radeon_emit_array(cs, sample_locs_8x, 4);
1720 radeon_emit_array(cs, sample_locs_8x, 2);
1721 break;
1722 }
1723 }
1724
1725 static void radv_get_sample_position(struct radv_device *device,
1726 unsigned sample_count,
1727 unsigned sample_index, float *out_value)
1728 {
1729 const uint32_t *sample_locs;
1730
1731 switch (sample_count) {
1732 case 1:
1733 default:
1734 sample_locs = &sample_locs_1x;
1735 break;
1736 case 2:
1737 sample_locs = &sample_locs_2x;
1738 break;
1739 case 4:
1740 sample_locs = &sample_locs_4x;
1741 break;
1742 case 8:
1743 sample_locs = sample_locs_8x;
1744 break;
1745 }
1746
1747 out_value[0] = (GET_SX(sample_locs, sample_index) + 8) / 16.0f;
1748 out_value[1] = (GET_SY(sample_locs, sample_index) + 8) / 16.0f;
1749 }
1750
1751 void radv_device_init_msaa(struct radv_device *device)
1752 {
1753 int i;
1754
1755 radv_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1756
1757 for (i = 0; i < 2; i++)
1758 radv_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1759 for (i = 0; i < 4; i++)
1760 radv_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1761 for (i = 0; i < 8; i++)
1762 radv_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1763 }