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[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for AMD GCN */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "radv_util.h"
35 #include "main/macros.h"
36
37 static void
38 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
39 struct radeon_cmdbuf *cs,
40 unsigned raster_config,
41 unsigned raster_config_1)
42 {
43 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
44 unsigned raster_config_se[4];
45 unsigned se;
46
47 ac_get_harvested_configs(&physical_device->rad_info,
48 raster_config,
49 &raster_config_1,
50 raster_config_se);
51
52 for (se = 0; se < num_se; se++) {
53 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
54 if (physical_device->rad_info.chip_class < GFX7)
55 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
56 S_00802C_SE_INDEX(se) |
57 S_00802C_SH_BROADCAST_WRITES(1) |
58 S_00802C_INSTANCE_BROADCAST_WRITES(1));
59 else
60 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
61 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
62 S_030800_INSTANCE_BROADCAST_WRITES(1));
63 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
64 }
65
66 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
67 if (physical_device->rad_info.chip_class < GFX7)
68 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
69 S_00802C_SE_BROADCAST_WRITES(1) |
70 S_00802C_SH_BROADCAST_WRITES(1) |
71 S_00802C_INSTANCE_BROADCAST_WRITES(1));
72 else
73 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
74 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
75 S_030800_INSTANCE_BROADCAST_WRITES(1));
76
77 if (physical_device->rad_info.chip_class >= GFX7)
78 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
79 }
80
81 void
82 si_emit_compute(struct radv_physical_device *physical_device,
83 struct radeon_cmdbuf *cs)
84 {
85 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
86 radeon_emit(cs, 0);
87 radeon_emit(cs, 0);
88 radeon_emit(cs, 0);
89
90 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
91 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
92 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
93 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
94 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
95
96 if (physical_device->rad_info.chip_class >= GFX7) {
97 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
98 radeon_set_sh_reg_seq(cs,
99 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
100 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
101 S_00B858_SH1_CU_EN(0xffff));
102 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
103 S_00B858_SH1_CU_EN(0xffff));
104 }
105
106 if (physical_device->rad_info.chip_class >= GFX10)
107 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
108
109 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
110 * and is now per pipe, so it should be handled in the
111 * kernel if we want to use something other than the default value,
112 * which is now 0x22f.
113 */
114 if (physical_device->rad_info.chip_class <= GFX6) {
115 /* XXX: This should be:
116 * (number of compute units) * 4 * (waves per simd) - 1 */
117
118 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
119 0x190 /* Default value */);
120 }
121 }
122
123 /* 12.4 fixed-point */
124 static unsigned radv_pack_float_12p4(float x)
125 {
126 return x <= 0 ? 0 :
127 x >= 4096 ? 0xffff : x * 16;
128 }
129
130 static void
131 si_set_raster_config(struct radv_physical_device *physical_device,
132 struct radeon_cmdbuf *cs)
133 {
134 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
135 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
136 unsigned raster_config, raster_config_1;
137
138 ac_get_raster_config(&physical_device->rad_info,
139 &raster_config,
140 &raster_config_1, NULL);
141
142 /* Always use the default config when all backends are enabled
143 * (or when we failed to determine the enabled backends).
144 */
145 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
146 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
147 raster_config);
148 if (physical_device->rad_info.chip_class >= GFX7)
149 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
150 raster_config_1);
151 } else {
152 si_write_harvested_raster_configs(physical_device, cs,
153 raster_config,
154 raster_config_1);
155 }
156 }
157
158 void
159 si_emit_graphics(struct radv_physical_device *physical_device,
160 struct radeon_cmdbuf *cs)
161 {
162 bool has_clear_state = physical_device->rad_info.has_clear_state;
163 int i;
164
165 /* Since amdgpu version 3.6.0, CONTEXT_CONTROL is emitted by the kernel */
166 if (physical_device->rad_info.drm_minor < 6) {
167 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
168 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
169 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
170 }
171
172 if (has_clear_state) {
173 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
174 radeon_emit(cs, 0);
175 }
176
177 if (physical_device->rad_info.chip_class <= GFX8)
178 si_set_raster_config(physical_device, cs);
179
180 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
181 if (!has_clear_state)
182 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
183
184 /* FIXME calculate these values somehow ??? */
185 if (physical_device->rad_info.chip_class <= GFX8) {
186 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
187 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
188 }
189
190 if (!has_clear_state) {
191 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
192 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
193 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
194 }
195
196 if (physical_device->rad_info.chip_class <= GFX9)
197 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
198 if (!has_clear_state)
199 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
200 if (physical_device->rad_info.chip_class < GFX7)
201 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
202 S_008A14_CLIP_VTX_REORDER_ENA(1));
203
204 if (!has_clear_state)
205 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
206
207 /* CLEAR_STATE doesn't clear these correctly on certain generations.
208 * I don't know why. Deduced by trial and error.
209 */
210 if (physical_device->rad_info.chip_class <= GFX7 || !has_clear_state) {
211 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
212 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
213 S_028204_WINDOW_OFFSET_DISABLE(1));
214 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
215 S_028240_WINDOW_OFFSET_DISABLE(1));
216 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
217 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
218 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
219 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
220 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
221 }
222
223 if (!has_clear_state) {
224 for (i = 0; i < 16; i++) {
225 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
226 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
227 }
228 }
229
230 if (!has_clear_state) {
231 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
232 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
233 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on GFX6 */
234 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
235 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
236 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
237 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
238 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
239 }
240
241 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
242 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
243 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
244
245 if (physical_device->rad_info.chip_class >= GFX10) {
246 radeon_set_context_reg(cs, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0);
247 radeon_set_uconfig_reg(cs, R_030964_GE_MAX_VTX_INDX, ~0);
248 radeon_set_uconfig_reg(cs, R_030924_GE_MIN_VTX_INDX, 0);
249 radeon_set_uconfig_reg(cs, R_030928_GE_INDX_OFFSET, 0);
250 radeon_set_uconfig_reg(cs, R_03097C_GE_STEREO_CNTL, 0);
251 radeon_set_uconfig_reg(cs, R_030988_GE_USER_VGPR_EN, 0);
252 } else if (physical_device->rad_info.chip_class == GFX9) {
253 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
254 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
255 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
256 } else {
257 /* These registers, when written, also overwrite the
258 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
259 * them. It would be an issue if there was another UMD
260 * changing them.
261 */
262 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
263 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
264 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
265 }
266
267 if (physical_device->rad_info.chip_class >= GFX7) {
268 if (physical_device->rad_info.chip_class >= GFX10) {
269 /* Logical CUs 16 - 31 */
270 radeon_set_sh_reg_idx(physical_device, cs, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
271 3, S_00B404_CU_EN(0xffff));
272 radeon_set_sh_reg_idx(physical_device, cs, R_00B104_SPI_SHADER_PGM_RSRC4_VS,
273 3, S_00B104_CU_EN(0xffff));
274 radeon_set_sh_reg_idx(physical_device, cs, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
275 3, S_00B004_CU_EN(0xffff));
276 }
277
278 if (physical_device->rad_info.chip_class >= GFX9) {
279 radeon_set_sh_reg_idx(physical_device, cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
280 3, S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
281 } else {
282 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
283 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
284 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
285 S_00B41C_WAVE_LIMIT(0x3F));
286 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
287 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
288 /* If this is 0, Bonaire can hang even if GS isn't being used.
289 * Other chips are unaffected. These are suboptimal values,
290 * but we don't use on-chip GS.
291 */
292 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
293 S_028A44_ES_VERTS_PER_SUBGRP(64) |
294 S_028A44_GS_PRIMS_PER_SUBGRP(4));
295 }
296
297 /* Compute LATE_ALLOC_VS.LIMIT. */
298 unsigned num_cu_per_sh = physical_device->rad_info.num_good_cu_per_sh;
299 unsigned late_alloc_limit; /* The limit is per SH. */
300
301 if (physical_device->rad_info.family == CHIP_KABINI) {
302 late_alloc_limit = 0; /* Potential hang on Kabini. */
303 } else if (num_cu_per_sh <= 4) {
304 /* Too few available compute units per SH. Disallowing
305 * VS to run on one CU could hurt us more than late VS
306 * allocation would help.
307 *
308 * 2 is the highest safe number that allows us to keep
309 * all CUs enabled.
310 */
311 late_alloc_limit = 2;
312 } else {
313 /* This is a good initial value, allowing 1 late_alloc
314 * wave per SIMD on num_cu - 2.
315 */
316 late_alloc_limit = (num_cu_per_sh - 2) * 4;
317 }
318
319 unsigned late_alloc_limit_gs = late_alloc_limit;
320 unsigned cu_mask_vs = 0xffff;
321 unsigned cu_mask_gs = 0xffff;
322
323 if (late_alloc_limit > 2) {
324 if (physical_device->rad_info.chip_class >= GFX10) {
325 /* CU2 & CU3 disabled because of the dual CU design */
326 cu_mask_vs = 0xfff3;
327 cu_mask_gs = 0xfff3; /* NGG only */
328 } else {
329 cu_mask_vs = 0xfffe; /* 1 CU disabled */
330 }
331 }
332
333 /* Don't use late alloc for NGG on Navi14 due to a hw bug. */
334 if (physical_device->rad_info.family == CHIP_NAVI14) {
335 late_alloc_limit_gs = 0;
336 cu_mask_gs = 0xffff;
337 }
338
339 radeon_set_sh_reg_idx(physical_device, cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
340 3, S_00B118_CU_EN(cu_mask_vs) |
341 S_00B118_WAVE_LIMIT(0x3F));
342 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
343 S_00B11C_LIMIT(late_alloc_limit));
344
345 radeon_set_sh_reg_idx(physical_device, cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
346 3, S_00B21C_CU_EN(cu_mask_gs) | S_00B21C_WAVE_LIMIT(0x3F));
347
348 if (physical_device->rad_info.chip_class >= GFX10) {
349 radeon_set_sh_reg_idx(physical_device, cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
350 3, S_00B204_CU_EN(0xffff) |
351 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_limit_gs));
352 }
353
354 radeon_set_sh_reg_idx(physical_device, cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
355 3, S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
356 }
357
358 if (physical_device->rad_info.chip_class >= GFX10) {
359 /* Break up a pixel wave if it contains deallocs for more than
360 * half the parameter cache.
361 *
362 * To avoid a deadlock where pixel waves aren't launched
363 * because they're waiting for more pixels while the frontend
364 * is stuck waiting for PC space, the maximum allowed value is
365 * the size of the PC minus the largest possible allocation for
366 * a single primitive shader subgroup.
367 */
368 radeon_set_context_reg(cs, R_028C50_PA_SC_NGG_MODE_CNTL,
369 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
370 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
371 radeon_set_context_reg(cs, R_02807C_DB_RMI_L2_CACHE_CONTROL,
372 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
373 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
374 S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
375 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
376 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
377 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
378 S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD));
379
380 radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
381 S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
382 S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
383 S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR) |
384 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
385 S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
386 S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
387 S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD) |
388 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
389 radeon_set_context_reg(cs, R_028428_CB_COVERAGE_OUT_CONTROL, 0);
390
391 radeon_set_sh_reg(cs, R_00B0C0_SPI_SHADER_REQ_CTRL_PS,
392 S_00B0C0_SOFT_GROUPING_EN(1) |
393 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
394 radeon_set_sh_reg(cs, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
395
396 if (physical_device->rad_info.family == CHIP_NAVI10 ||
397 physical_device->rad_info.family == CHIP_NAVI12 ||
398 physical_device->rad_info.family == CHIP_NAVI14) {
399 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
400 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
401 radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
402 }
403
404 /* TODO: For culling, replace 128 with 256. */
405 radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC,
406 S_030980_OVERSUB_EN(1) |
407 S_030980_NUM_PC_LINES(128 * physical_device->rad_info.max_se - 1));
408 }
409
410 if (physical_device->rad_info.chip_class >= GFX8) {
411 uint32_t vgt_tess_distribution;
412
413 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
414 S_028B50_ACCUM_TRI(11) |
415 S_028B50_ACCUM_QUAD(11) |
416 S_028B50_DONUT_SPLIT(16);
417
418 if (physical_device->rad_info.family == CHIP_FIJI ||
419 physical_device->rad_info.family >= CHIP_POLARIS10)
420 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
421
422 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
423 vgt_tess_distribution);
424 } else if (!has_clear_state) {
425 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
426 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
427 }
428
429 if (physical_device->rad_info.chip_class >= GFX9) {
430 unsigned num_se = physical_device->rad_info.max_se;
431 unsigned pc_lines = 0;
432 unsigned max_alloc_count = 0;
433
434 switch (physical_device->rad_info.family) {
435 case CHIP_VEGA10:
436 case CHIP_VEGA12:
437 case CHIP_VEGA20:
438 pc_lines = 4096;
439 break;
440 case CHIP_RAVEN:
441 case CHIP_RAVEN2:
442 case CHIP_RENOIR:
443 case CHIP_NAVI10:
444 case CHIP_NAVI12:
445 pc_lines = 1024;
446 break;
447 case CHIP_NAVI14:
448 pc_lines = 512;
449 break;
450 default:
451 assert(0);
452 }
453
454 if (physical_device->rad_info.chip_class >= GFX10) {
455 max_alloc_count = pc_lines / 3;
456 } else {
457 max_alloc_count = MIN2(128, pc_lines / (4 * num_se));
458 }
459
460 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
461 S_028C48_MAX_ALLOC_COUNT(max_alloc_count - 1) |
462 S_028C48_MAX_PRIM_PER_BATCH(1023));
463 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
464 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
465 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
466 }
467
468 unsigned tmp = (unsigned)(1.0 * 8.0);
469 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
470 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
471 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
472 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
473 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
474
475 if (!has_clear_state) {
476 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
477 S_028004_ZPASS_INCREMENT_DISABLE(1));
478 }
479
480 /* Enable the Polaris small primitive filter control.
481 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
482 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
483 * and AMDVLK doesn't have a workaround as well.
484 */
485 if (physical_device->rad_info.family >= CHIP_POLARIS10) {
486 unsigned small_prim_filter_cntl =
487 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
488 /* Workaround for a hw line bug. */
489 S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12);
490
491 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
492 small_prim_filter_cntl);
493 }
494
495 si_emit_compute(physical_device, cs);
496 }
497
498 void
499 cik_create_gfx_config(struct radv_device *device)
500 {
501 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX);
502 if (!cs)
503 return;
504
505 si_emit_graphics(device->physical_device, cs);
506
507 while (cs->cdw & 7) {
508 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
509 radeon_emit(cs, 0x80000000);
510 else
511 radeon_emit(cs, 0xffff1000);
512 }
513
514 device->gfx_init = device->ws->buffer_create(device->ws,
515 cs->cdw * 4, 4096,
516 RADEON_DOMAIN_GTT,
517 RADEON_FLAG_CPU_ACCESS|
518 RADEON_FLAG_NO_INTERPROCESS_SHARING |
519 RADEON_FLAG_READ_ONLY,
520 RADV_BO_PRIORITY_CS);
521 if (!device->gfx_init)
522 goto fail;
523
524 void *map = device->ws->buffer_map(device->gfx_init);
525 if (!map) {
526 device->ws->buffer_destroy(device->gfx_init);
527 device->gfx_init = NULL;
528 goto fail;
529 }
530 memcpy(map, cs->buf, cs->cdw * 4);
531
532 device->ws->buffer_unmap(device->gfx_init);
533 device->gfx_init_size_dw = cs->cdw;
534 fail:
535 device->ws->cs_destroy(cs);
536 }
537
538 static void
539 get_viewport_xform(const VkViewport *viewport,
540 float scale[3], float translate[3])
541 {
542 float x = viewport->x;
543 float y = viewport->y;
544 float half_width = 0.5f * viewport->width;
545 float half_height = 0.5f * viewport->height;
546 double n = viewport->minDepth;
547 double f = viewport->maxDepth;
548
549 scale[0] = half_width;
550 translate[0] = half_width + x;
551 scale[1] = half_height;
552 translate[1] = half_height + y;
553
554 scale[2] = (f - n);
555 translate[2] = n;
556 }
557
558 void
559 si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
560 int count, const VkViewport *viewports)
561 {
562 int i;
563
564 assert(count);
565 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
566 first_vp * 4 * 6, count * 6);
567
568 for (i = 0; i < count; i++) {
569 float scale[3], translate[3];
570
571
572 get_viewport_xform(&viewports[i], scale, translate);
573 radeon_emit(cs, fui(scale[0]));
574 radeon_emit(cs, fui(translate[0]));
575 radeon_emit(cs, fui(scale[1]));
576 radeon_emit(cs, fui(translate[1]));
577 radeon_emit(cs, fui(scale[2]));
578 radeon_emit(cs, fui(translate[2]));
579 }
580
581 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
582 first_vp * 4 * 2, count * 2);
583 for (i = 0; i < count; i++) {
584 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
585 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
586 radeon_emit(cs, fui(zmin));
587 radeon_emit(cs, fui(zmax));
588 }
589 }
590
591 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
592 {
593 float scale[3], translate[3];
594 VkRect2D rect;
595
596 get_viewport_xform(viewport, scale, translate);
597
598 rect.offset.x = translate[0] - fabs(scale[0]);
599 rect.offset.y = translate[1] - fabs(scale[1]);
600 rect.extent.width = ceilf(translate[0] + fabs(scale[0])) - rect.offset.x;
601 rect.extent.height = ceilf(translate[1] + fabs(scale[1])) - rect.offset.y;
602
603 return rect;
604 }
605
606 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
607 VkRect2D ret;
608 ret.offset.x = MAX2(a->offset.x, b->offset.x);
609 ret.offset.y = MAX2(a->offset.y, b->offset.y);
610 ret.extent.width = MIN2(a->offset.x + a->extent.width,
611 b->offset.x + b->extent.width) - ret.offset.x;
612 ret.extent.height = MIN2(a->offset.y + a->extent.height,
613 b->offset.y + b->extent.height) - ret.offset.y;
614 return ret;
615 }
616
617 void
618 si_write_scissors(struct radeon_cmdbuf *cs, int first,
619 int count, const VkRect2D *scissors,
620 const VkViewport *viewports, bool can_use_guardband)
621 {
622 int i;
623 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
624 const float max_range = 32767.0f;
625 if (!count)
626 return;
627
628 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
629 for (i = 0; i < count; i++) {
630 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
631 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
632
633 get_viewport_xform(viewports + i, scale, translate);
634 scale[0] = fabsf(scale[0]);
635 scale[1] = fabsf(scale[1]);
636
637 if (scale[0] < 0.5)
638 scale[0] = 0.5;
639 if (scale[1] < 0.5)
640 scale[1] = 0.5;
641
642 guardband_x = MIN2(guardband_x, (max_range - fabsf(translate[0])) / scale[0]);
643 guardband_y = MIN2(guardband_y, (max_range - fabsf(translate[1])) / scale[1]);
644
645 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
646 S_028250_TL_Y(scissor.offset.y) |
647 S_028250_WINDOW_OFFSET_DISABLE(1));
648 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
649 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
650 }
651 if (!can_use_guardband) {
652 guardband_x = 1.0;
653 guardband_y = 1.0;
654 }
655
656 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
657 radeon_emit(cs, fui(guardband_y));
658 radeon_emit(cs, fui(1.0));
659 radeon_emit(cs, fui(guardband_x));
660 radeon_emit(cs, fui(1.0));
661 }
662
663 static inline unsigned
664 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
665 {
666 if (num == 0)
667 return 0;
668
669 if (info->incr == 0)
670 return 0;
671
672 if (num < info->min)
673 return 0;
674
675 return 1 + ((num - info->min) / info->incr);
676 }
677
678 uint32_t
679 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
680 bool instanced_draw, bool indirect_draw,
681 bool count_from_stream_output,
682 uint32_t draw_vertex_count)
683 {
684 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
685 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
686 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
687 const unsigned max_primgroup_in_wave = 2;
688 /* SWITCH_ON_EOP(0) is always preferable. */
689 bool wd_switch_on_eop = false;
690 bool ia_switch_on_eop = false;
691 bool ia_switch_on_eoi = false;
692 bool partial_vs_wave = false;
693 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave;
694 bool multi_instances_smaller_than_primgroup;
695
696 multi_instances_smaller_than_primgroup = indirect_draw;
697 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
698 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
699 if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size)
700 multi_instances_smaller_than_primgroup = true;
701 }
702
703 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
704 partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
705
706 if (chip_class >= GFX7) {
707 wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.wd_switch_on_eop;
708
709 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
710 * We don't know that for indirect drawing, so treat it as
711 * always problematic. */
712 if (family == CHIP_HAWAII &&
713 (instanced_draw || indirect_draw))
714 wd_switch_on_eop = true;
715
716 /* Performance recommendation for 4 SE Gfx7-8 parts if
717 * instances are smaller than a primgroup.
718 * Assume indirect draws always use small instances.
719 * This is needed for good VS wave utilization.
720 */
721 if (chip_class <= GFX8 &&
722 info->max_se == 4 &&
723 multi_instances_smaller_than_primgroup)
724 wd_switch_on_eop = true;
725
726 /* Required on GFX7 and later. */
727 if (info->max_se > 2 && !wd_switch_on_eop)
728 ia_switch_on_eoi = true;
729
730 /* Required by Hawaii and, for some special cases, by GFX8. */
731 if (ia_switch_on_eoi &&
732 (family == CHIP_HAWAII ||
733 (chip_class == GFX8 &&
734 /* max primgroup in wave is always 2 - leave this for documentation */
735 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
736 partial_vs_wave = true;
737
738 /* Instancing bug on Bonaire. */
739 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
740 (instanced_draw || indirect_draw))
741 partial_vs_wave = true;
742
743 /* Hardware requirement when drawing primitives from a stream
744 * output buffer.
745 */
746 if (count_from_stream_output)
747 wd_switch_on_eop = true;
748
749 /* If the WD switch is false, the IA switch must be false too. */
750 assert(wd_switch_on_eop || !ia_switch_on_eop);
751 }
752 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
753 if (chip_class <= GFX8 && ia_switch_on_eoi)
754 partial_es_wave = true;
755
756 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
757 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
758 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
759 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
760 */
761 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
762 bool set_vgt_flush = indirect_draw;
763 if (!set_vgt_flush && instanced_draw) {
764 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
765 if (num_prims <= 1)
766 set_vgt_flush = true;
767 }
768 if (set_vgt_flush)
769 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
770 }
771 }
772
773 return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base |
774 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
775 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
776 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
777 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
778 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= GFX7 ? wd_switch_on_eop : 0);
779
780 }
781
782 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
783 enum chip_class chip_class,
784 bool is_mec,
785 unsigned event, unsigned event_flags,
786 unsigned dst_sel, unsigned data_sel,
787 uint64_t va,
788 uint32_t new_fence,
789 uint64_t gfx9_eop_bug_va)
790 {
791 unsigned op = EVENT_TYPE(event) |
792 EVENT_INDEX(event == V_028A90_CS_DONE ||
793 event == V_028A90_PS_DONE ? 6 : 5) |
794 event_flags;
795 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
796 unsigned sel = EOP_DST_SEL(dst_sel) |
797 EOP_DATA_SEL(data_sel);
798
799 /* Wait for write confirmation before writing data, but don't send
800 * an interrupt. */
801 if (data_sel != EOP_DATA_SEL_DISCARD)
802 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
803
804 if (chip_class >= GFX9 || is_gfx8_mec) {
805 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
806 * counters) must immediately precede every timestamp event to
807 * prevent a GPU hang on GFX9.
808 */
809 if (chip_class == GFX9 && !is_mec) {
810 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
811 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
812 radeon_emit(cs, gfx9_eop_bug_va);
813 radeon_emit(cs, gfx9_eop_bug_va >> 32);
814 }
815
816 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false));
817 radeon_emit(cs, op);
818 radeon_emit(cs, sel);
819 radeon_emit(cs, va); /* address lo */
820 radeon_emit(cs, va >> 32); /* address hi */
821 radeon_emit(cs, new_fence); /* immediate data lo */
822 radeon_emit(cs, 0); /* immediate data hi */
823 if (!is_gfx8_mec)
824 radeon_emit(cs, 0); /* unused */
825 } else {
826 if (chip_class == GFX7 ||
827 chip_class == GFX8) {
828 /* Two EOP events are required to make all engines go idle
829 * (and optional cache flushes executed) before the timestamp
830 * is written.
831 */
832 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
833 radeon_emit(cs, op);
834 radeon_emit(cs, va);
835 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
836 radeon_emit(cs, 0); /* immediate data */
837 radeon_emit(cs, 0); /* unused */
838 }
839
840 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
841 radeon_emit(cs, op);
842 radeon_emit(cs, va);
843 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
844 radeon_emit(cs, new_fence); /* immediate data */
845 radeon_emit(cs, 0); /* unused */
846 }
847 }
848
849 void
850 radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
851 uint32_t ref, uint32_t mask)
852 {
853 assert(op == WAIT_REG_MEM_EQUAL ||
854 op == WAIT_REG_MEM_NOT_EQUAL ||
855 op == WAIT_REG_MEM_GREATER_OR_EQUAL);
856
857 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false));
858 radeon_emit(cs, op | WAIT_REG_MEM_MEM_SPACE(1));
859 radeon_emit(cs, va);
860 radeon_emit(cs, va >> 32);
861 radeon_emit(cs, ref); /* reference value */
862 radeon_emit(cs, mask); /* mask */
863 radeon_emit(cs, 4); /* poll interval */
864 }
865
866 static void
867 si_emit_acquire_mem(struct radeon_cmdbuf *cs,
868 bool is_mec,
869 bool is_gfx9,
870 unsigned cp_coher_cntl)
871 {
872 if (is_mec || is_gfx9) {
873 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
874 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) |
875 PKT3_SHADER_TYPE_S(is_mec));
876 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
877 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
878 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
879 radeon_emit(cs, 0); /* CP_COHER_BASE */
880 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
881 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
882 } else {
883 /* ACQUIRE_MEM is only required on a compute ring. */
884 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false));
885 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
886 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
887 radeon_emit(cs, 0); /* CP_COHER_BASE */
888 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
889 }
890 }
891
892 static void
893 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
894 enum chip_class chip_class,
895 uint32_t *flush_cnt,
896 uint64_t flush_va,
897 bool is_mec,
898 enum radv_cmd_flush_bits flush_bits,
899 uint64_t gfx9_eop_bug_va)
900 {
901 uint32_t gcr_cntl = 0;
902 unsigned cb_db_event = 0;
903
904 /* We don't need these. */
905 assert(!(flush_bits & (RADV_CMD_FLAG_VGT_STREAMOUT_SYNC)));
906
907 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
908 gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
909 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE) {
910 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
911 * to FORWARD when both L1 and L2 are written out (WB or INV).
912 */
913 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
914 }
915 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE)
916 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
917 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
918 /* Writeback and invalidate everything in L2. */
919 gcr_cntl |= S_586_GL2_INV(1) | S_586_GLM_INV(1);
920 } else if (flush_bits & RADV_CMD_FLAG_WB_L2) {
921 /* Writeback but do not invalidate. */
922 gcr_cntl |= S_586_GL2_WB(1);
923 }
924
925 /* TODO: Implement this new flag for GFX9+.
926 if (flush_bits & RADV_CMD_FLAG_INV_L2_METADATA)
927 gcr_cntl |= S_586_GLM_INV(1);
928 */
929
930 if (flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
931 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_CB_META */
932 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
933 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
934 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
935 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
936 EVENT_INDEX(0));
937 }
938
939 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_DB_META ? */
940 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
941 /* Flush HTILE. Will wait for idle later. */
942 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
943 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) |
944 EVENT_INDEX(0));
945 }
946
947 /* First flush CB/DB, then L1/L2. */
948 gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
949
950 if ((flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) ==
951 (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
952 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
953 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
954 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
955 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
956 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
957 } else {
958 assert(0);
959 }
960 } else {
961 /* Wait for graphics shaders to go idle if requested. */
962 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
963 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
964 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
965 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
966 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
967 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
968 }
969 }
970
971 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
972 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
973 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
974 }
975
976 if (cb_db_event) {
977 /* CB/DB flush and invalidate (or possibly just a wait for a
978 * meta flush) via RELEASE_MEM.
979 *
980 * Combine this with other cache flushes when possible; this
981 * requires affected shaders to be idle, so do it after the
982 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
983 * implied).
984 */
985 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
986 unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
987 unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
988 unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
989 unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
990 assert(G_586_GL2_US(gcr_cntl) == 0);
991 assert(G_586_GL2_RANGE(gcr_cntl) == 0);
992 assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
993 unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
994 unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
995 unsigned gcr_seq = G_586_SEQ(gcr_cntl);
996
997 gcr_cntl &= C_586_GLM_WB &
998 C_586_GLM_INV &
999 C_586_GLV_INV &
1000 C_586_GL1_INV &
1001 C_586_GL2_INV &
1002 C_586_GL2_WB; /* keep SEQ */
1003
1004 assert(flush_cnt);
1005 (*flush_cnt)++;
1006
1007 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event,
1008 S_490_GLM_WB(glm_wb) |
1009 S_490_GLM_INV(glm_inv) |
1010 S_490_GLV_INV(glv_inv) |
1011 S_490_GL1_INV(gl1_inv) |
1012 S_490_GL2_INV(gl2_inv) |
1013 S_490_GL2_WB(gl2_wb) |
1014 S_490_SEQ(gcr_seq),
1015 EOP_DST_SEL_MEM,
1016 EOP_DATA_SEL_VALUE_32BIT,
1017 flush_va, *flush_cnt,
1018 gfx9_eop_bug_va);
1019
1020 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
1021 *flush_cnt, 0xffffffff);
1022 }
1023
1024 /* VGT state sync */
1025 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1026 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1027 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1028 }
1029
1030 /* Ignore fields that only modify the behavior of other fields. */
1031 if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
1032 /* Flush caches and wait for the caches to assert idle.
1033 * The cache flush is executed in the ME, but the PFP waits
1034 * for completion.
1035 */
1036 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
1037 radeon_emit(cs, 0); /* CP_COHER_CNTL */
1038 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1039 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1040 radeon_emit(cs, 0); /* CP_COHER_BASE */
1041 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1042 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1043 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
1044 } else if ((cb_db_event ||
1045 (flush_bits & (RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1046 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1047 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)))
1048 && !is_mec) {
1049 /* We need to ensure that PFP waits as well. */
1050 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1051 radeon_emit(cs, 0);
1052 }
1053
1054 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1055 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1056 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1057 EVENT_INDEX(0));
1058 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1059 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1060 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1061 EVENT_INDEX(0));
1062 }
1063 }
1064
1065 void
1066 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1067 enum chip_class chip_class,
1068 uint32_t *flush_cnt,
1069 uint64_t flush_va,
1070 bool is_mec,
1071 enum radv_cmd_flush_bits flush_bits,
1072 uint64_t gfx9_eop_bug_va)
1073 {
1074 unsigned cp_coher_cntl = 0;
1075 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1076 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
1077
1078 if (chip_class >= GFX10) {
1079 /* GFX10 cache flush handling is quite different. */
1080 gfx10_cs_emit_cache_flush(cs, chip_class, flush_cnt, flush_va,
1081 is_mec, flush_bits, gfx9_eop_bug_va);
1082 return;
1083 }
1084
1085 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
1086 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1087 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE)
1088 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1089
1090 if (chip_class <= GFX8) {
1091 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
1092 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
1093 S_0085F0_CB0_DEST_BASE_ENA(1) |
1094 S_0085F0_CB1_DEST_BASE_ENA(1) |
1095 S_0085F0_CB2_DEST_BASE_ENA(1) |
1096 S_0085F0_CB3_DEST_BASE_ENA(1) |
1097 S_0085F0_CB4_DEST_BASE_ENA(1) |
1098 S_0085F0_CB5_DEST_BASE_ENA(1) |
1099 S_0085F0_CB6_DEST_BASE_ENA(1) |
1100 S_0085F0_CB7_DEST_BASE_ENA(1);
1101
1102 /* Necessary for DCC */
1103 if (chip_class >= GFX8) {
1104 si_cs_emit_write_event_eop(cs,
1105 chip_class,
1106 is_mec,
1107 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
1108 0,
1109 EOP_DST_SEL_MEM,
1110 EOP_DATA_SEL_DISCARD,
1111 0, 0,
1112 gfx9_eop_bug_va);
1113 }
1114 }
1115 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
1116 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
1117 S_0085F0_DB_DEST_BASE_ENA(1);
1118 }
1119 }
1120
1121 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
1122 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1123 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1124 }
1125
1126 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
1127 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1128 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1129 }
1130
1131 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
1132 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1133 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1134 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
1135 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1136 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1137 }
1138
1139 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
1140 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1141 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1142 }
1143
1144 if (chip_class == GFX9 && flush_cb_db) {
1145 unsigned cb_db_event, tc_flags;
1146
1147 /* Set the CB/DB flush event. */
1148 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1149
1150 /* These are the only allowed combinations. If you need to
1151 * do multiple operations at once, do them separately.
1152 * All operations that invalidate L2 also seem to invalidate
1153 * metadata. Volatile (VOL) and WC flushes are not listed here.
1154 *
1155 * TC | TC_WB = writeback & invalidate L2 & L1
1156 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1157 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1158 * TC | TC_NC = invalidate L2 for MTYPE == NC
1159 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1160 * TCL1 = invalidate L1
1161 */
1162 tc_flags = EVENT_TC_ACTION_ENA |
1163 EVENT_TC_MD_ACTION_ENA;
1164
1165 /* Ideally flush TC together with CB/DB. */
1166 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
1167 /* Writeback and invalidate everything in L2 & L1. */
1168 tc_flags = EVENT_TC_ACTION_ENA |
1169 EVENT_TC_WB_ACTION_ENA;
1170
1171
1172 /* Clear the flags. */
1173 flush_bits &= ~(RADV_CMD_FLAG_INV_L2 |
1174 RADV_CMD_FLAG_WB_L2 |
1175 RADV_CMD_FLAG_INV_VCACHE);
1176 }
1177 assert(flush_cnt);
1178 (*flush_cnt)++;
1179
1180 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags,
1181 EOP_DST_SEL_MEM,
1182 EOP_DATA_SEL_VALUE_32BIT,
1183 flush_va, *flush_cnt,
1184 gfx9_eop_bug_va);
1185 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
1186 *flush_cnt, 0xffffffff);
1187 }
1188
1189 /* VGT state sync */
1190 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1191 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1192 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1193 }
1194
1195 /* VGT streamout state sync */
1196 if (flush_bits & RADV_CMD_FLAG_VGT_STREAMOUT_SYNC) {
1197 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1198 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1199 }
1200
1201 /* Make sure ME is idle (it executes most packets) before continuing.
1202 * This prevents read-after-write hazards between PFP and ME.
1203 */
1204 if ((cp_coher_cntl ||
1205 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1206 RADV_CMD_FLAG_INV_VCACHE |
1207 RADV_CMD_FLAG_INV_L2 |
1208 RADV_CMD_FLAG_WB_L2))) &&
1209 !is_mec) {
1210 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1211 radeon_emit(cs, 0);
1212 }
1213
1214 if ((flush_bits & RADV_CMD_FLAG_INV_L2) ||
1215 (chip_class <= GFX7 && (flush_bits & RADV_CMD_FLAG_WB_L2))) {
1216 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9,
1217 cp_coher_cntl |
1218 S_0085F0_TC_ACTION_ENA(1) |
1219 S_0085F0_TCL1_ACTION_ENA(1) |
1220 S_0301F0_TC_WB_ACTION_ENA(chip_class >= GFX8));
1221 cp_coher_cntl = 0;
1222 } else {
1223 if(flush_bits & RADV_CMD_FLAG_WB_L2) {
1224 /* WB = write-back
1225 * NC = apply to non-coherent MTYPEs
1226 * (i.e. MTYPE <= 1, which is what we use everywhere)
1227 *
1228 * WB doesn't work without NC.
1229 */
1230 si_emit_acquire_mem(cs, is_mec,
1231 chip_class == GFX9,
1232 cp_coher_cntl |
1233 S_0301F0_TC_WB_ACTION_ENA(1) |
1234 S_0301F0_TC_NC_ACTION_ENA(1));
1235 cp_coher_cntl = 0;
1236 }
1237 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE) {
1238 si_emit_acquire_mem(cs, is_mec,
1239 chip_class == GFX9,
1240 cp_coher_cntl |
1241 S_0085F0_TCL1_ACTION_ENA(1));
1242 cp_coher_cntl = 0;
1243 }
1244 }
1245
1246 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1247 * Therefore, it should be last. Done in PFP.
1248 */
1249 if (cp_coher_cntl)
1250 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9, cp_coher_cntl);
1251
1252 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1253 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1254 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1255 EVENT_INDEX(0));
1256 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1257 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1258 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1259 EVENT_INDEX(0));
1260 }
1261 }
1262
1263 void
1264 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
1265 {
1266 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1267
1268 if (is_compute)
1269 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1270 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1271 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1272 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1273 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1274 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1275 RADV_CMD_FLAG_VGT_FLUSH |
1276 RADV_CMD_FLAG_START_PIPELINE_STATS |
1277 RADV_CMD_FLAG_STOP_PIPELINE_STATS);
1278
1279 if (!cmd_buffer->state.flush_bits)
1280 return;
1281
1282 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1283
1284 si_cs_emit_cache_flush(cmd_buffer->cs,
1285 cmd_buffer->device->physical_device->rad_info.chip_class,
1286 &cmd_buffer->gfx9_fence_idx,
1287 cmd_buffer->gfx9_fence_va,
1288 radv_cmd_buffer_uses_mec(cmd_buffer),
1289 cmd_buffer->state.flush_bits,
1290 cmd_buffer->gfx9_eop_bug_va);
1291
1292
1293 if (unlikely(cmd_buffer->device->trace_bo))
1294 radv_cmd_buffer_trace_emit(cmd_buffer);
1295
1296 /* Clear the caches that have been flushed to avoid syncing too much
1297 * when there is some pending active queries.
1298 */
1299 cmd_buffer->active_query_flush_bits &= ~cmd_buffer->state.flush_bits;
1300
1301 cmd_buffer->state.flush_bits = 0;
1302
1303 /* If the driver used a compute shader for resetting a query pool, it
1304 * should be finished at this point.
1305 */
1306 cmd_buffer->pending_reset_query = false;
1307 }
1308
1309 /* sets the CP predication state using a boolean stored at va */
1310 void
1311 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1312 bool draw_visible, uint64_t va)
1313 {
1314 uint32_t op = 0;
1315
1316 if (va) {
1317 op = PRED_OP(PREDICATION_OP_BOOL64);
1318
1319 /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
1320 * zero, all rendering commands are discarded. Otherwise, they
1321 * are discarded if the value is non zero.
1322 */
1323 op |= draw_visible ? PREDICATION_DRAW_VISIBLE :
1324 PREDICATION_DRAW_NOT_VISIBLE;
1325 }
1326 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1327 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1328 radeon_emit(cmd_buffer->cs, op);
1329 radeon_emit(cmd_buffer->cs, va);
1330 radeon_emit(cmd_buffer->cs, va >> 32);
1331 } else {
1332 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1333 radeon_emit(cmd_buffer->cs, va);
1334 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1335 }
1336 }
1337
1338 /* Set this if you want the 3D engine to wait until CP DMA is done.
1339 * It should be set on the last CP DMA packet. */
1340 #define CP_DMA_SYNC (1 << 0)
1341
1342 /* Set this if the source data was used as a destination in a previous CP DMA
1343 * packet. It's for preventing a read-after-write (RAW) hazard between two
1344 * CP DMA packets. */
1345 #define CP_DMA_RAW_WAIT (1 << 1)
1346 #define CP_DMA_USE_L2 (1 << 2)
1347 #define CP_DMA_CLEAR (1 << 3)
1348
1349 /* Alignment for optimal performance. */
1350 #define SI_CPDMA_ALIGNMENT 32
1351
1352 /* The max number of bytes that can be copied per packet. */
1353 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1354 {
1355 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1356 S_414_BYTE_COUNT_GFX9(~0u) :
1357 S_414_BYTE_COUNT_GFX6(~0u);
1358
1359 /* make it aligned for optimal performance */
1360 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1361 }
1362
1363 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1364 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1365 * clear value.
1366 */
1367 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1368 uint64_t dst_va, uint64_t src_va,
1369 unsigned size, unsigned flags)
1370 {
1371 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1372 uint32_t header = 0, command = 0;
1373
1374 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1375
1376 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1377 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1378 command |= S_414_BYTE_COUNT_GFX9(size);
1379 else
1380 command |= S_414_BYTE_COUNT_GFX6(size);
1381
1382 /* Sync flags. */
1383 if (flags & CP_DMA_SYNC)
1384 header |= S_411_CP_SYNC(1);
1385 else {
1386 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1387 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1388 else
1389 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1390 }
1391
1392 if (flags & CP_DMA_RAW_WAIT)
1393 command |= S_414_RAW_WAIT(1);
1394
1395 /* Src and dst flags. */
1396 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1397 !(flags & CP_DMA_CLEAR) &&
1398 src_va == dst_va)
1399 header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
1400 else if (flags & CP_DMA_USE_L2)
1401 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
1402
1403 if (flags & CP_DMA_CLEAR)
1404 header |= S_411_SRC_SEL(V_411_DATA);
1405 else if (flags & CP_DMA_USE_L2)
1406 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1407
1408 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1409 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1410 radeon_emit(cs, header);
1411 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1412 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1413 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1414 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1415 radeon_emit(cs, command);
1416 } else {
1417 assert(!(flags & CP_DMA_USE_L2));
1418 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1419 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1420 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1421 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1422 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1423 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1424 radeon_emit(cs, command);
1425 }
1426
1427 /* CP DMA is executed in ME, but index buffers are read by PFP.
1428 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1429 * indices. If we wanted to execute CP DMA in PFP, this packet
1430 * should precede it.
1431 */
1432 if (flags & CP_DMA_SYNC) {
1433 if (cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1434 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1435 radeon_emit(cs, 0);
1436 }
1437
1438 /* CP will see the sync flag and wait for all DMAs to complete. */
1439 cmd_buffer->state.dma_is_busy = false;
1440 }
1441
1442 if (unlikely(cmd_buffer->device->trace_bo))
1443 radv_cmd_buffer_trace_emit(cmd_buffer);
1444 }
1445
1446 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1447 unsigned size)
1448 {
1449 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1450 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1451
1452 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1453 aligned_size, CP_DMA_USE_L2);
1454 }
1455
1456 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1457 uint64_t remaining_size, unsigned *flags)
1458 {
1459
1460 /* Flush the caches for the first copy only.
1461 * Also wait for the previous CP DMA operations.
1462 */
1463 if (cmd_buffer->state.flush_bits) {
1464 si_emit_cache_flush(cmd_buffer);
1465 *flags |= CP_DMA_RAW_WAIT;
1466 }
1467
1468 /* Do the synchronization after the last dma, so that all data
1469 * is written to memory.
1470 */
1471 if (byte_count == remaining_size)
1472 *flags |= CP_DMA_SYNC;
1473 }
1474
1475 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1476 {
1477 uint64_t va;
1478 uint32_t offset;
1479 unsigned dma_flags = 0;
1480 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1481 void *ptr;
1482
1483 assert(size < SI_CPDMA_ALIGNMENT);
1484
1485 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1486
1487 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1488 va += offset;
1489
1490 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1491
1492 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1493 dma_flags);
1494 }
1495
1496 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1497 uint64_t src_va, uint64_t dest_va,
1498 uint64_t size)
1499 {
1500 uint64_t main_src_va, main_dest_va;
1501 uint64_t skipped_size = 0, realign_size = 0;
1502
1503 /* Assume that we are not going to sync after the last DMA operation. */
1504 cmd_buffer->state.dma_is_busy = true;
1505
1506 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1507 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1508 /* If the size is not aligned, we must add a dummy copy at the end
1509 * just to align the internal counter. Otherwise, the DMA engine
1510 * would slow down by an order of magnitude for following copies.
1511 */
1512 if (size % SI_CPDMA_ALIGNMENT)
1513 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1514
1515 /* If the copy begins unaligned, we must start copying from the next
1516 * aligned block and the skipped part should be copied after everything
1517 * else has been copied. Only the src alignment matters, not dst.
1518 */
1519 if (src_va % SI_CPDMA_ALIGNMENT) {
1520 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1521 /* The main part will be skipped if the size is too small. */
1522 skipped_size = MIN2(skipped_size, size);
1523 size -= skipped_size;
1524 }
1525 }
1526 main_src_va = src_va + skipped_size;
1527 main_dest_va = dest_va + skipped_size;
1528
1529 while (size) {
1530 unsigned dma_flags = 0;
1531 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1532
1533 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1534 /* DMA operations via L2 are coherent and faster.
1535 * TODO: GFX7-GFX9 should also support this but it
1536 * requires tests/benchmarks.
1537 */
1538 dma_flags |= CP_DMA_USE_L2;
1539 }
1540
1541 si_cp_dma_prepare(cmd_buffer, byte_count,
1542 size + skipped_size + realign_size,
1543 &dma_flags);
1544
1545 dma_flags &= ~CP_DMA_SYNC;
1546
1547 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1548 byte_count, dma_flags);
1549
1550 size -= byte_count;
1551 main_src_va += byte_count;
1552 main_dest_va += byte_count;
1553 }
1554
1555 if (skipped_size) {
1556 unsigned dma_flags = 0;
1557
1558 si_cp_dma_prepare(cmd_buffer, skipped_size,
1559 size + skipped_size + realign_size,
1560 &dma_flags);
1561
1562 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1563 skipped_size, dma_flags);
1564 }
1565 if (realign_size)
1566 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1567 }
1568
1569 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1570 uint64_t size, unsigned value)
1571 {
1572
1573 if (!size)
1574 return;
1575
1576 assert(va % 4 == 0 && size % 4 == 0);
1577
1578 /* Assume that we are not going to sync after the last DMA operation. */
1579 cmd_buffer->state.dma_is_busy = true;
1580
1581 while (size) {
1582 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1583 unsigned dma_flags = CP_DMA_CLEAR;
1584
1585 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1586 /* DMA operations via L2 are coherent and faster.
1587 * TODO: GFX7-GFX9 should also support this but it
1588 * requires tests/benchmarks.
1589 */
1590 dma_flags |= CP_DMA_USE_L2;
1591 }
1592
1593 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1594
1595 /* Emit the clear packet. */
1596 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1597 dma_flags);
1598
1599 size -= byte_count;
1600 va += byte_count;
1601 }
1602 }
1603
1604 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
1605 {
1606 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX7)
1607 return;
1608
1609 if (!cmd_buffer->state.dma_is_busy)
1610 return;
1611
1612 /* Issue a dummy DMA that copies zero bytes.
1613 *
1614 * The DMA engine will see that there's no work to do and skip this
1615 * DMA request, however, the CP will see the sync flag and still wait
1616 * for all DMAs to complete.
1617 */
1618 si_emit_cp_dma(cmd_buffer, 0, 0, 0, CP_DMA_SYNC);
1619
1620 cmd_buffer->state.dma_is_busy = false;
1621 }
1622
1623 /* For MSAA sample positions. */
1624 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1625 ((((unsigned)(s0x) & 0xf) << 0) | (((unsigned)(s0y) & 0xf) << 4) | \
1626 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1627 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1628 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1629
1630 /* For obtaining location coordinates from registers */
1631 #define SEXT4(x) ((int)((x) | ((x) & 0x8 ? 0xfffffff0 : 0)))
1632 #define GET_SFIELD(reg, index) SEXT4(((reg) >> ((index) * 4)) & 0xf)
1633 #define GET_SX(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2)
1634 #define GET_SY(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2 + 1)
1635
1636 /* 1x MSAA */
1637 static const uint32_t sample_locs_1x =
1638 FILL_SREG(0, 0, 0, 0, 0, 0, 0, 0);
1639 static const unsigned max_dist_1x = 0;
1640 static const uint64_t centroid_priority_1x = 0x0000000000000000ull;
1641
1642 /* 2xMSAA */
1643 static const uint32_t sample_locs_2x =
1644 FILL_SREG(4,4, -4, -4, 0, 0, 0, 0);
1645 static const unsigned max_dist_2x = 4;
1646 static const uint64_t centroid_priority_2x = 0x1010101010101010ull;
1647
1648 /* 4xMSAA */
1649 static const uint32_t sample_locs_4x =
1650 FILL_SREG(-2,-6, 6, -2, -6, 2, 2, 6);
1651 static const unsigned max_dist_4x = 6;
1652 static const uint64_t centroid_priority_4x = 0x3210321032103210ull;
1653
1654 /* 8xMSAA */
1655 static const uint32_t sample_locs_8x[] = {
1656 FILL_SREG( 1,-3, -1, 3, 5, 1, -3,-5),
1657 FILL_SREG(-5, 5, -7,-1, 3, 7, 7,-7),
1658 /* The following are unused by hardware, but we emit them to IBs
1659 * instead of multiple SET_CONTEXT_REG packets. */
1660 0,
1661 0,
1662 };
1663 static const unsigned max_dist_8x = 7;
1664 static const uint64_t centroid_priority_8x = 0x7654321076543210ull;
1665
1666 unsigned radv_get_default_max_sample_dist(int log_samples)
1667 {
1668 unsigned max_dist[] = {
1669 max_dist_1x,
1670 max_dist_2x,
1671 max_dist_4x,
1672 max_dist_8x,
1673 };
1674 return max_dist[log_samples];
1675 }
1676
1677 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples)
1678 {
1679 switch (nr_samples) {
1680 default:
1681 case 1:
1682 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1683 radeon_emit(cs, (uint32_t)centroid_priority_1x);
1684 radeon_emit(cs, centroid_priority_1x >> 32);
1685 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_1x);
1686 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_1x);
1687 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_1x);
1688 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_1x);
1689 break;
1690 case 2:
1691 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1692 radeon_emit(cs, (uint32_t)centroid_priority_2x);
1693 radeon_emit(cs, centroid_priority_2x >> 32);
1694 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x);
1695 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x);
1696 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x);
1697 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x);
1698 break;
1699 case 4:
1700 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1701 radeon_emit(cs, (uint32_t)centroid_priority_4x);
1702 radeon_emit(cs, centroid_priority_4x >> 32);
1703 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x);
1704 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x);
1705 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x);
1706 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x);
1707 break;
1708 case 8:
1709 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1710 radeon_emit(cs, (uint32_t)centroid_priority_8x);
1711 radeon_emit(cs, centroid_priority_8x >> 32);
1712 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1713 radeon_emit_array(cs, sample_locs_8x, 4);
1714 radeon_emit_array(cs, sample_locs_8x, 4);
1715 radeon_emit_array(cs, sample_locs_8x, 4);
1716 radeon_emit_array(cs, sample_locs_8x, 2);
1717 break;
1718 }
1719 }
1720
1721 static void radv_get_sample_position(struct radv_device *device,
1722 unsigned sample_count,
1723 unsigned sample_index, float *out_value)
1724 {
1725 const uint32_t *sample_locs;
1726
1727 switch (sample_count) {
1728 case 1:
1729 default:
1730 sample_locs = &sample_locs_1x;
1731 break;
1732 case 2:
1733 sample_locs = &sample_locs_2x;
1734 break;
1735 case 4:
1736 sample_locs = &sample_locs_4x;
1737 break;
1738 case 8:
1739 sample_locs = sample_locs_8x;
1740 break;
1741 }
1742
1743 out_value[0] = (GET_SX(sample_locs, sample_index) + 8) / 16.0f;
1744 out_value[1] = (GET_SY(sample_locs, sample_index) + 8) / 16.0f;
1745 }
1746
1747 void radv_device_init_msaa(struct radv_device *device)
1748 {
1749 int i;
1750
1751 radv_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1752
1753 for (i = 0; i < 2; i++)
1754 radv_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1755 for (i = 0; i < 4; i++)
1756 radv_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1757 for (i = 0; i < 8; i++)
1758 radv_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1759 }