2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
6 * Copyright © 2015 Advanced Micro Devices, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 /* command buffer handling for SI */
30 #include "radv_private.h"
33 #include "radv_util.h"
34 #include "main/macros.h"
36 #define SI_GS_PER_ES 128
39 si_write_harvested_raster_configs(struct radv_physical_device
*physical_device
,
40 struct radeon_winsys_cs
*cs
,
41 unsigned raster_config
,
42 unsigned raster_config_1
)
44 unsigned sh_per_se
= MAX2(physical_device
->rad_info
.max_sh_per_se
, 1);
45 unsigned num_se
= MAX2(physical_device
->rad_info
.max_se
, 1);
46 unsigned rb_mask
= physical_device
->rad_info
.enabled_rb_mask
;
47 unsigned num_rb
= MIN2(physical_device
->rad_info
.num_render_backends
, 16);
48 unsigned rb_per_pkr
= MIN2(num_rb
/ num_se
/ sh_per_se
, 2);
49 unsigned rb_per_se
= num_rb
/ num_se
;
53 se_mask
[0] = ((1 << rb_per_se
) - 1) & rb_mask
;
54 se_mask
[1] = (se_mask
[0] << rb_per_se
) & rb_mask
;
55 se_mask
[2] = (se_mask
[1] << rb_per_se
) & rb_mask
;
56 se_mask
[3] = (se_mask
[2] << rb_per_se
) & rb_mask
;
58 assert(num_se
== 1 || num_se
== 2 || num_se
== 4);
59 assert(sh_per_se
== 1 || sh_per_se
== 2);
60 assert(rb_per_pkr
== 1 || rb_per_pkr
== 2);
62 /* XXX: I can't figure out what the *_XSEL and *_YSEL
63 * fields are for, so I'm leaving them as their default
66 if ((num_se
> 2) && ((!se_mask
[0] && !se_mask
[1]) ||
67 (!se_mask
[2] && !se_mask
[3]))) {
68 raster_config_1
&= C_028354_SE_PAIR_MAP
;
70 if (!se_mask
[0] && !se_mask
[1]) {
72 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3
);
75 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0
);
79 for (se
= 0; se
< num_se
; se
++) {
80 unsigned raster_config_se
= raster_config
;
81 unsigned pkr0_mask
= ((1 << rb_per_pkr
) - 1) << (se
* rb_per_se
);
82 unsigned pkr1_mask
= pkr0_mask
<< rb_per_pkr
;
83 int idx
= (se
/ 2) * 2;
85 if ((num_se
> 1) && (!se_mask
[idx
] || !se_mask
[idx
+ 1])) {
86 raster_config_se
&= C_028350_SE_MAP
;
90 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3
);
93 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0
);
99 if (rb_per_se
> 2 && (!pkr0_mask
|| !pkr1_mask
)) {
100 raster_config_se
&= C_028350_PKR_MAP
;
104 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3
);
107 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0
);
111 if (rb_per_se
>= 2) {
112 unsigned rb0_mask
= 1 << (se
* rb_per_se
);
113 unsigned rb1_mask
= rb0_mask
<< 1;
117 if (!rb0_mask
|| !rb1_mask
) {
118 raster_config_se
&= C_028350_RB_MAP_PKR0
;
122 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3
);
125 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0
);
130 rb0_mask
= 1 << (se
* rb_per_se
+ rb_per_pkr
);
131 rb1_mask
= rb0_mask
<< 1;
134 if (!rb0_mask
|| !rb1_mask
) {
135 raster_config_se
&= C_028350_RB_MAP_PKR1
;
139 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3
);
142 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0
);
148 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
149 if (physical_device
->rad_info
.chip_class
< CIK
)
150 radeon_set_config_reg(cs
, GRBM_GFX_INDEX
,
151 SE_INDEX(se
) | SH_BROADCAST_WRITES
|
152 INSTANCE_BROADCAST_WRITES
);
154 radeon_set_uconfig_reg(cs
, R_030800_GRBM_GFX_INDEX
,
155 S_030800_SE_INDEX(se
) | S_030800_SH_BROADCAST_WRITES(1) |
156 S_030800_INSTANCE_BROADCAST_WRITES(1));
157 radeon_set_context_reg(cs
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
);
158 if (physical_device
->rad_info
.chip_class
>= CIK
)
159 radeon_set_context_reg(cs
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
162 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
163 if (physical_device
->rad_info
.chip_class
< CIK
)
164 radeon_set_config_reg(cs
, GRBM_GFX_INDEX
,
165 SE_BROADCAST_WRITES
| SH_BROADCAST_WRITES
|
166 INSTANCE_BROADCAST_WRITES
);
168 radeon_set_uconfig_reg(cs
, R_030800_GRBM_GFX_INDEX
,
169 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
170 S_030800_INSTANCE_BROADCAST_WRITES(1));
174 si_emit_compute(struct radv_physical_device
*physical_device
,
175 struct radeon_winsys_cs
*cs
)
177 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
182 radeon_set_sh_reg_seq(cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
, 3);
184 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
185 radeon_emit(cs
, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
186 radeon_emit(cs
, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
188 if (physical_device
->rad_info
.chip_class
>= CIK
) {
189 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
190 radeon_set_sh_reg_seq(cs
,
191 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2
, 2);
192 radeon_emit(cs
, S_00B864_SH0_CU_EN(0xffff) |
193 S_00B864_SH1_CU_EN(0xffff));
194 radeon_emit(cs
, S_00B868_SH0_CU_EN(0xffff) |
195 S_00B868_SH1_CU_EN(0xffff));
198 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
199 * and is now per pipe, so it should be handled in the
200 * kernel if we want to use something other than the default value,
201 * which is now 0x22f.
203 if (physical_device
->rad_info
.chip_class
<= SI
) {
204 /* XXX: This should be:
205 * (number of compute units) * 4 * (waves per simd) - 1 */
207 radeon_set_sh_reg(cs
, R_00B82C_COMPUTE_MAX_WAVE_ID
,
208 0x190 /* Default value */);
213 si_init_compute(struct radv_cmd_buffer
*cmd_buffer
)
215 struct radv_physical_device
*physical_device
= cmd_buffer
->device
->physical_device
;
216 si_emit_compute(physical_device
, cmd_buffer
->cs
);
220 si_emit_config(struct radv_physical_device
*physical_device
,
221 struct radeon_winsys_cs
*cs
)
223 unsigned num_rb
= MIN2(physical_device
->rad_info
.num_render_backends
, 16);
224 unsigned rb_mask
= physical_device
->rad_info
.enabled_rb_mask
;
225 unsigned raster_config
, raster_config_1
;
228 radeon_emit(cs
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
229 radeon_emit(cs
, CONTEXT_CONTROL_LOAD_ENABLE(1));
230 radeon_emit(cs
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
232 radeon_set_context_reg(cs
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
233 radeon_set_context_reg(cs
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
235 /* FIXME calculate these values somehow ??? */
236 radeon_set_context_reg(cs
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
237 radeon_set_context_reg(cs
, R_028A58_VGT_ES_PER_GS
, 0x40);
238 radeon_set_context_reg(cs
, R_028A5C_VGT_GS_PER_VS
, 0x2);
240 radeon_set_context_reg(cs
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
241 radeon_set_context_reg(cs
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
243 radeon_set_context_reg(cs
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
244 radeon_set_context_reg(cs
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
245 if (physical_device
->rad_info
.chip_class
< CIK
)
246 radeon_set_config_reg(cs
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
247 S_008A14_CLIP_VTX_REORDER_ENA(1));
249 radeon_set_context_reg(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 0x76543210);
250 radeon_set_context_reg(cs
, R_028BD8_PA_SC_CENTROID_PRIORITY_1
, 0xfedcba98);
252 radeon_set_context_reg(cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, 0);
254 for (i
= 0; i
< 16; i
++) {
255 radeon_set_context_reg(cs
, R_0282D0_PA_SC_VPORT_ZMIN_0
+ i
*8, 0);
256 radeon_set_context_reg(cs
, R_0282D4_PA_SC_VPORT_ZMAX_0
+ i
*8, fui(1.0));
259 switch (physical_device
->rad_info
.family
) {
262 raster_config
= 0x2a00126a;
263 raster_config_1
= 0x00000000;
266 raster_config
= 0x0000124a;
267 raster_config_1
= 0x00000000;
270 raster_config
= 0x00000082;
271 raster_config_1
= 0x00000000;
274 raster_config
= 0x00000000;
275 raster_config_1
= 0x00000000;
278 raster_config
= 0x16000012;
279 raster_config_1
= 0x00000000;
282 raster_config
= 0x3a00161a;
283 raster_config_1
= 0x0000002e;
286 if (physical_device
->rad_info
.cik_macrotile_mode_array
[0] == 0x000000e8) {
287 /* old kernels with old tiling config */
288 raster_config
= 0x16000012;
289 raster_config_1
= 0x0000002a;
291 raster_config
= 0x3a00161a;
292 raster_config_1
= 0x0000002e;
296 raster_config
= 0x16000012;
297 raster_config_1
= 0x0000002a;
301 raster_config
= 0x16000012;
302 raster_config_1
= 0x00000000;
305 raster_config
= 0x16000012;
306 raster_config_1
= 0x0000002a;
310 raster_config
= 0x00000000;
312 raster_config
= 0x00000002;
313 raster_config_1
= 0x00000000;
316 raster_config
= 0x00000002;
317 raster_config_1
= 0x00000000;
320 /* KV should be 0x00000002, but that causes problems with radeon */
321 raster_config
= 0x00000000; /* 0x00000002 */
322 raster_config_1
= 0x00000000;
327 raster_config
= 0x00000000;
328 raster_config_1
= 0x00000000;
332 "radeonsi: Unknown GPU, using 0 for raster_config\n");
333 raster_config
= 0x00000000;
334 raster_config_1
= 0x00000000;
338 /* Always use the default config when all backends are enabled
339 * (or when we failed to determine the enabled backends).
341 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
342 radeon_set_context_reg(cs
, R_028350_PA_SC_RASTER_CONFIG
,
344 if (physical_device
->rad_info
.chip_class
>= CIK
)
345 radeon_set_context_reg(cs
, R_028354_PA_SC_RASTER_CONFIG_1
,
348 si_write_harvested_raster_configs(physical_device
, cs
, raster_config
, raster_config_1
);
351 radeon_set_context_reg(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
352 radeon_set_context_reg(cs
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
353 radeon_set_context_reg(cs
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
354 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
355 radeon_set_context_reg(cs
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
356 radeon_set_context_reg(cs
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
357 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
359 radeon_set_context_reg(cs
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
360 radeon_set_context_reg(cs
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
361 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
362 radeon_set_context_reg(cs
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
363 radeon_set_context_reg(cs
, R_028820_PA_CL_NANINF_CNTL
, 0);
365 radeon_set_context_reg(cs
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
366 radeon_set_context_reg(cs
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
367 radeon_set_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
368 radeon_set_context_reg(cs
, R_02800C_DB_RENDER_OVERRIDE
,
369 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
370 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
));
372 radeon_set_context_reg(cs
, R_028400_VGT_MAX_VTX_INDX
, ~0);
373 radeon_set_context_reg(cs
, R_028404_VGT_MIN_VTX_INDX
, 0);
374 radeon_set_context_reg(cs
, R_028408_VGT_INDX_OFFSET
, 0);
376 if (physical_device
->rad_info
.chip_class
>= CIK
) {
377 /* If this is 0, Bonaire can hang even if GS isn't being used.
378 * Other chips are unaffected. These are suboptimal values,
379 * but we don't use on-chip GS.
381 radeon_set_context_reg(cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
382 S_028A44_ES_VERTS_PER_SUBGRP(64) |
383 S_028A44_GS_PRIMS_PER_SUBGRP(4));
385 radeon_set_sh_reg(cs
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
, S_00B51C_CU_EN(0xffff));
386 radeon_set_sh_reg(cs
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
, 0);
387 radeon_set_sh_reg(cs
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
, S_00B31C_CU_EN(0xffff));
388 radeon_set_sh_reg(cs
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
, S_00B21C_CU_EN(0xffff));
390 if (physical_device
->rad_info
.num_good_compute_units
/
391 (physical_device
->rad_info
.max_se
* physical_device
->rad_info
.max_sh_per_se
) <= 4) {
392 /* Too few available compute units per SH. Disallowing
393 * VS to run on CU0 could hurt us more than late VS
394 * allocation would help.
396 * LATE_ALLOC_VS = 2 is the highest safe number.
398 radeon_set_sh_reg(cs
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
, S_00B118_CU_EN(0xffff));
399 radeon_set_sh_reg(cs
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(2));
401 /* Set LATE_ALLOC_VS == 31. It should be less than
402 * the number of scratch waves. Limitations:
403 * - VS can't execute on CU0.
404 * - If HS writes outputs to LDS, LS can't execute on CU0.
406 radeon_set_sh_reg(cs
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
, S_00B118_CU_EN(0xfffe));
407 radeon_set_sh_reg(cs
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(31));
410 radeon_set_sh_reg(cs
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
, S_00B01C_CU_EN(0xffff));
413 if (physical_device
->rad_info
.chip_class
>= VI
) {
414 uint32_t vgt_tess_distribution
;
415 radeon_set_context_reg(cs
, R_028424_CB_DCC_CONTROL
,
416 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
417 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
418 if (physical_device
->rad_info
.family
< CHIP_POLARIS10
)
419 radeon_set_context_reg(cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 30);
420 radeon_set_context_reg(cs
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 32);
422 vgt_tess_distribution
= S_028B50_ACCUM_ISOLINE(32) |
423 S_028B50_ACCUM_TRI(11) |
424 S_028B50_ACCUM_QUAD(11) |
425 S_028B50_DONUT_SPLIT(16);
427 if (physical_device
->rad_info
.family
== CHIP_FIJI
||
428 physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
429 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
431 radeon_set_context_reg(cs
, R_028B50_VGT_TESS_DISTRIBUTION
,
432 vgt_tess_distribution
);
434 radeon_set_context_reg(cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
435 radeon_set_context_reg(cs
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
438 if (physical_device
->rad_info
.family
== CHIP_STONEY
)
439 radeon_set_context_reg(cs
, R_028C40_PA_SC_SHADER_CONTROL
, 0);
441 si_emit_compute(physical_device
, cs
);
444 void si_init_config(struct radv_cmd_buffer
*cmd_buffer
)
446 struct radv_physical_device
*physical_device
= cmd_buffer
->device
->physical_device
;
448 si_emit_config(physical_device
, cmd_buffer
->cs
);
452 cik_create_gfx_config(struct radv_device
*device
)
454 struct radeon_winsys_cs
*cs
= device
->ws
->cs_create(device
->ws
, RING_GFX
);
458 si_emit_config(device
->physical_device
, cs
);
460 while (cs
->cdw
& 7) {
461 if (device
->physical_device
->rad_info
.gfx_ib_pad_with_type2
)
462 radeon_emit(cs
, 0x80000000);
464 radeon_emit(cs
, 0xffff1000);
467 device
->gfx_init
= device
->ws
->buffer_create(device
->ws
,
470 RADEON_FLAG_CPU_ACCESS
);
471 if (!device
->gfx_init
)
474 void *map
= device
->ws
->buffer_map(device
->gfx_init
);
476 device
->ws
->buffer_destroy(device
->gfx_init
);
477 device
->gfx_init
= NULL
;
480 memcpy(map
, cs
->buf
, cs
->cdw
* 4);
482 device
->ws
->buffer_unmap(device
->gfx_init
);
483 device
->gfx_init_size_dw
= cs
->cdw
;
485 device
->ws
->cs_destroy(cs
);
489 get_viewport_xform(const VkViewport
*viewport
,
490 float scale
[3], float translate
[3])
492 float x
= viewport
->x
;
493 float y
= viewport
->y
;
494 float half_width
= 0.5f
* viewport
->width
;
495 float half_height
= 0.5f
* viewport
->height
;
496 double n
= viewport
->minDepth
;
497 double f
= viewport
->maxDepth
;
499 scale
[0] = half_width
;
500 translate
[0] = half_width
+ x
;
501 scale
[1] = half_height
;
502 translate
[1] = half_height
+ y
;
509 si_write_viewport(struct radeon_winsys_cs
*cs
, int first_vp
,
510 int count
, const VkViewport
*viewports
)
515 radeon_set_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE
+
516 first_vp
* 4 * 6, count
* 6);
518 for (i
= 0; i
< count
; i
++) {
519 float scale
[3], translate
[3];
522 get_viewport_xform(&viewports
[i
], scale
, translate
);
523 radeon_emit(cs
, fui(scale
[0]));
524 radeon_emit(cs
, fui(translate
[0]));
525 radeon_emit(cs
, fui(scale
[1]));
526 radeon_emit(cs
, fui(translate
[1]));
527 radeon_emit(cs
, fui(scale
[2]));
528 radeon_emit(cs
, fui(translate
[2]));
531 radeon_set_context_reg_seq(cs
, R_0282D0_PA_SC_VPORT_ZMIN_0
+
532 first_vp
* 4 * 2, count
* 2);
533 for (i
= 0; i
< count
; i
++) {
534 float zmin
= MIN2(viewports
[i
].minDepth
, viewports
[i
].maxDepth
);
535 float zmax
= MAX2(viewports
[i
].minDepth
, viewports
[i
].maxDepth
);
536 radeon_emit(cs
, fui(zmin
));
537 radeon_emit(cs
, fui(zmax
));
541 static VkRect2D
si_scissor_from_viewport(const VkViewport
*viewport
)
543 float scale
[3], translate
[3];
546 get_viewport_xform(viewport
, scale
, translate
);
548 rect
.offset
.x
= translate
[0] - abs(scale
[0]);
549 rect
.offset
.y
= translate
[1] - abs(scale
[1]);
550 rect
.extent
.width
= ceilf(translate
[0] + abs(scale
[0])) - rect
.offset
.x
;
551 rect
.extent
.height
= ceilf(translate
[1] + abs(scale
[1])) - rect
.offset
.y
;
556 static VkRect2D
si_intersect_scissor(const VkRect2D
*a
, const VkRect2D
*b
) {
558 ret
.offset
.x
= MAX2(a
->offset
.x
, b
->offset
.x
);
559 ret
.offset
.y
= MAX2(a
->offset
.y
, b
->offset
.y
);
560 ret
.extent
.width
= MIN2(a
->offset
.x
+ a
->extent
.width
,
561 b
->offset
.x
+ b
->extent
.width
) - ret
.offset
.x
;
562 ret
.extent
.height
= MIN2(a
->offset
.y
+ a
->extent
.height
,
563 b
->offset
.y
+ b
->extent
.height
) - ret
.offset
.y
;
568 si_write_scissors(struct radeon_winsys_cs
*cs
, int first
,
569 int count
, const VkRect2D
*scissors
,
570 const VkViewport
*viewports
, bool can_use_guardband
)
573 float scale
[3], translate
[3], guardband_x
= INFINITY
, guardband_y
= INFINITY
;
574 const float max_range
= 32767.0f
;
577 radeon_set_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
+ first
* 4 * 2, count
* 2);
578 for (i
= 0; i
< count
; i
++) {
579 VkRect2D viewport_scissor
= si_scissor_from_viewport(viewports
+ i
);
580 VkRect2D scissor
= si_intersect_scissor(&scissors
[i
], &viewport_scissor
);
582 get_viewport_xform(viewports
+ i
, scale
, translate
);
583 scale
[0] = abs(scale
[0]);
584 scale
[1] = abs(scale
[1]);
591 guardband_x
= MIN2(guardband_x
, (max_range
- abs(translate
[0])) / scale
[0]);
592 guardband_y
= MIN2(guardband_y
, (max_range
- abs(translate
[1])) / scale
[1]);
594 radeon_emit(cs
, S_028250_TL_X(scissor
.offset
.x
) |
595 S_028250_TL_Y(scissor
.offset
.y
) |
596 S_028250_WINDOW_OFFSET_DISABLE(1));
597 radeon_emit(cs
, S_028254_BR_X(scissor
.offset
.x
+ scissor
.extent
.width
) |
598 S_028254_BR_Y(scissor
.offset
.y
+ scissor
.extent
.height
));
600 if (!can_use_guardband
) {
605 radeon_set_context_reg_seq(cs
, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 4);
606 radeon_emit(cs
, fui(guardband_y
));
607 radeon_emit(cs
, fui(1.0));
608 radeon_emit(cs
, fui(guardband_x
));
609 radeon_emit(cs
, fui(1.0));
612 static inline unsigned
613 radv_prims_for_vertices(struct radv_prim_vertex_count
*info
, unsigned num
)
624 return 1 + ((num
- info
->min
) / info
->incr
);
628 si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
629 bool instanced_draw
, bool indirect_draw
,
630 uint32_t draw_vertex_count
)
632 enum chip_class chip_class
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
;
633 enum radeon_family family
= cmd_buffer
->device
->physical_device
->rad_info
.family
;
634 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
635 unsigned prim
= cmd_buffer
->state
.pipeline
->graphics
.prim
;
636 unsigned primgroup_size
= 128; /* recommended without a GS */
637 unsigned max_primgroup_in_wave
= 2;
638 /* SWITCH_ON_EOP(0) is always preferable. */
639 bool wd_switch_on_eop
= false;
640 bool ia_switch_on_eop
= false;
641 bool ia_switch_on_eoi
= false;
642 bool partial_vs_wave
= false;
643 bool partial_es_wave
= false;
644 uint32_t num_prims
= radv_prims_for_vertices(&cmd_buffer
->state
.pipeline
->graphics
.prim_vertex_count
, draw_vertex_count
);
645 bool multi_instances_smaller_than_primgroup
;
647 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
648 primgroup_size
= cmd_buffer
->state
.pipeline
->graphics
.tess
.num_patches
;
649 else if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
650 primgroup_size
= 64; /* recommended with a GS */
652 multi_instances_smaller_than_primgroup
= indirect_draw
|| (instanced_draw
&&
653 num_prims
< primgroup_size
);
654 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
)) {
655 /* SWITCH_ON_EOI must be set if PrimID is used. */
656 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.uses_prim_id
||
657 cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.uses_prim_id
)
658 ia_switch_on_eoi
= true;
660 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
661 if ((family
== CHIP_TAHITI
||
662 family
== CHIP_PITCAIRN
||
663 family
== CHIP_BONAIRE
) &&
664 radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
665 partial_vs_wave
= true;
667 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
668 if (cmd_buffer
->device
->has_distributed_tess
) {
669 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
)) {
670 partial_es_wave
= true;
672 if (family
== CHIP_TONGA
||
673 family
== CHIP_FIJI
||
674 family
== CHIP_POLARIS10
||
675 family
== CHIP_POLARIS11
||
676 family
== CHIP_POLARIS12
)
677 partial_vs_wave
= true;
679 partial_vs_wave
= true;
683 /* TODO linestipple */
685 if (chip_class
>= CIK
) {
686 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
687 * 4 shader engines. Set 1 to pass the assertion below.
688 * The other cases are hardware requirements. */
689 if (info
->max_se
< 4 ||
690 prim
== V_008958_DI_PT_POLYGON
||
691 prim
== V_008958_DI_PT_LINELOOP
||
692 prim
== V_008958_DI_PT_TRIFAN
||
693 prim
== V_008958_DI_PT_TRISTRIP_ADJ
||
694 (cmd_buffer
->state
.pipeline
->graphics
.prim_restart_enable
&&
695 (family
< CHIP_POLARIS10
||
696 (prim
!= V_008958_DI_PT_POINTLIST
&&
697 prim
!= V_008958_DI_PT_LINESTRIP
&&
698 prim
!= V_008958_DI_PT_TRISTRIP
))))
699 wd_switch_on_eop
= true;
701 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
702 * We don't know that for indirect drawing, so treat it as
703 * always problematic. */
704 if (family
== CHIP_HAWAII
&&
705 (instanced_draw
|| indirect_draw
))
706 wd_switch_on_eop
= true;
708 /* Performance recommendation for 4 SE Gfx7-8 parts if
709 * instances are smaller than a primgroup.
710 * Assume indirect draws always use small instances.
711 * This is needed for good VS wave utilization.
713 if (chip_class
<= VI
&&
715 multi_instances_smaller_than_primgroup
)
716 wd_switch_on_eop
= true;
718 /* Required on CIK and later. */
719 if (info
->max_se
> 2 && !wd_switch_on_eop
)
720 ia_switch_on_eoi
= true;
722 /* Required by Hawaii and, for some special cases, by VI. */
723 if (ia_switch_on_eoi
&&
724 (family
== CHIP_HAWAII
||
726 (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
) || max_primgroup_in_wave
!= 2))))
727 partial_vs_wave
= true;
729 /* Instancing bug on Bonaire. */
730 if (family
== CHIP_BONAIRE
&& ia_switch_on_eoi
&&
731 (instanced_draw
|| indirect_draw
))
732 partial_vs_wave
= true;
734 /* If the WD switch is false, the IA switch must be false too. */
735 assert(wd_switch_on_eop
|| !ia_switch_on_eop
);
737 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
738 if (ia_switch_on_eoi
)
739 partial_es_wave
= true;
741 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
)) {
742 /* GS requirement. */
743 if (SI_GS_PER_ES
/ primgroup_size
>= cmd_buffer
->device
->gs_table_depth
- 3)
744 partial_es_wave
= true;
746 /* Hw bug with single-primitive instances and SWITCH_ON_EOI
747 * on multi-SE chips. */
748 if (info
->max_se
>= 2 && ia_switch_on_eoi
&&
749 ((instanced_draw
|| indirect_draw
) &&
751 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_FLUSH
;
754 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
755 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi
) |
756 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
757 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave
) |
758 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1) |
759 S_028AA8_WD_SWITCH_ON_EOP(chip_class
>= CIK
? wd_switch_on_eop
: 0) |
760 S_028AA8_MAX_PRIMGRP_IN_WAVE(chip_class
>= VI
?
761 max_primgroup_in_wave
: 0);
765 void si_cs_emit_write_event_eop(struct radeon_winsys_cs
*cs
,
766 enum chip_class chip_class
,
768 unsigned event
, unsigned event_flags
,
774 unsigned op
= EVENT_TYPE(event
) |
779 radeon_emit(cs
, PKT3(PKT3_RELEASE_MEM
, 5, 0));
781 radeon_emit(cs
, EOP_DATA_SEL(data_sel
));
782 radeon_emit(cs
, va
); /* address lo */
783 radeon_emit(cs
, va
>> 32); /* address hi */
784 radeon_emit(cs
, new_fence
); /* immediate data lo */
785 radeon_emit(cs
, 0); /* immediate data hi */
787 if (chip_class
== CIK
||
789 /* Two EOP events are required to make all engines go idle
790 * (and optional cache flushes executed) before the timestamp
793 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, 0));
796 radeon_emit(cs
, ((va
>> 32) & 0xffff) | EOP_DATA_SEL(data_sel
));
797 radeon_emit(cs
, old_fence
); /* immediate data */
798 radeon_emit(cs
, 0); /* unused */
801 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, 0));
804 radeon_emit(cs
, ((va
>> 32) & 0xffff) | EOP_DATA_SEL(data_sel
));
805 radeon_emit(cs
, new_fence
); /* immediate data */
806 radeon_emit(cs
, 0); /* unused */
811 si_emit_wait_fence(struct radeon_winsys_cs
*cs
,
812 uint64_t va
, uint32_t ref
,
815 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
816 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
| WAIT_REG_MEM_MEM_SPACE(1));
818 radeon_emit(cs
, va
>> 32);
819 radeon_emit(cs
, ref
); /* reference value */
820 radeon_emit(cs
, mask
); /* mask */
821 radeon_emit(cs
, 4); /* poll interval */
825 si_emit_acquire_mem(struct radeon_winsys_cs
*cs
,
827 unsigned cp_coher_cntl
)
830 radeon_emit(cs
, PKT3(PKT3_ACQUIRE_MEM
, 5, 0) |
831 PKT3_SHADER_TYPE_S(1));
832 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
833 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
834 radeon_emit(cs
, 0xff); /* CP_COHER_SIZE_HI */
835 radeon_emit(cs
, 0); /* CP_COHER_BASE */
836 radeon_emit(cs
, 0); /* CP_COHER_BASE_HI */
837 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
839 /* ACQUIRE_MEM is only required on a compute ring. */
840 radeon_emit(cs
, PKT3(PKT3_SURFACE_SYNC
, 3, 0));
841 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
842 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
843 radeon_emit(cs
, 0); /* CP_COHER_BASE */
844 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
849 si_cs_emit_cache_flush(struct radeon_winsys_cs
*cs
,
850 enum chip_class chip_class
,
852 enum radv_cmd_flush_bits flush_bits
)
854 unsigned cp_coher_cntl
= 0;
856 if (flush_bits
& RADV_CMD_FLAG_INV_ICACHE
)
857 cp_coher_cntl
|= S_0085F0_SH_ICACHE_ACTION_ENA(1);
858 if (flush_bits
& RADV_CMD_FLAG_INV_SMEM_L1
)
859 cp_coher_cntl
|= S_0085F0_SH_KCACHE_ACTION_ENA(1);
861 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_CB
) {
862 cp_coher_cntl
|= S_0085F0_CB_ACTION_ENA(1) |
863 S_0085F0_CB0_DEST_BASE_ENA(1) |
864 S_0085F0_CB1_DEST_BASE_ENA(1) |
865 S_0085F0_CB2_DEST_BASE_ENA(1) |
866 S_0085F0_CB3_DEST_BASE_ENA(1) |
867 S_0085F0_CB4_DEST_BASE_ENA(1) |
868 S_0085F0_CB5_DEST_BASE_ENA(1) |
869 S_0085F0_CB6_DEST_BASE_ENA(1) |
870 S_0085F0_CB7_DEST_BASE_ENA(1);
872 /* Necessary for DCC */
873 if (chip_class
>= VI
) {
874 si_cs_emit_write_event_eop(cs
,
877 V_028A90_FLUSH_AND_INV_CB_DATA_TS
,
882 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_DB
) {
883 cp_coher_cntl
|= S_0085F0_DB_ACTION_ENA(1) |
884 S_0085F0_DB_DEST_BASE_ENA(1);
887 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
) {
888 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
889 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META
) | EVENT_INDEX(0));
892 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
) {
893 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
894 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META
) | EVENT_INDEX(0));
897 if (!(flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
898 RADV_CMD_FLAG_FLUSH_AND_INV_DB
))) {
899 if (flush_bits
& RADV_CMD_FLAG_PS_PARTIAL_FLUSH
) {
900 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
901 radeon_emit(cs
, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
902 } else if (flush_bits
& RADV_CMD_FLAG_VS_PARTIAL_FLUSH
) {
903 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
904 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
908 if (flush_bits
& RADV_CMD_FLAG_CS_PARTIAL_FLUSH
) {
909 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
910 radeon_emit(cs
, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
914 if (flush_bits
& RADV_CMD_FLAG_VGT_FLUSH
) {
915 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
916 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
919 /* Make sure ME is idle (it executes most packets) before continuing.
920 * This prevents read-after-write hazards between PFP and ME.
922 if ((cp_coher_cntl
|| (flush_bits
& RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) &&
924 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
928 if ((flush_bits
& RADV_CMD_FLAG_INV_GLOBAL_L2
) ||
929 (chip_class
<= CIK
&& (flush_bits
& RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
))) {
930 cp_coher_cntl
|= S_0085F0_TC_ACTION_ENA(1);
931 if (chip_class
>= VI
)
932 cp_coher_cntl
|= S_0301F0_TC_WB_ACTION_ENA(1);
933 } else if(flush_bits
& RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
) {
934 cp_coher_cntl
|= S_0301F0_TC_WB_ACTION_ENA(1) |
935 S_0301F0_TC_NC_ACTION_ENA(1);
937 /* L2 writeback doesn't combine with L1 invalidate */
938 si_emit_acquire_mem(cs
, is_mec
, cp_coher_cntl
);
943 if (flush_bits
& RADV_CMD_FLAG_INV_VMEM_L1
)
944 cp_coher_cntl
|= S_0085F0_TCL1_ACTION_ENA(1);
946 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
947 * Therefore, it should be last. Done in PFP.
950 si_emit_acquire_mem(cs
, is_mec
, cp_coher_cntl
);
954 si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
)
956 bool is_compute
= cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
;
959 cmd_buffer
->state
.flush_bits
&= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
960 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
961 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
962 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
|
963 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
964 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
|
965 RADV_CMD_FLAG_VGT_FLUSH
);
967 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 128);
969 si_cs_emit_cache_flush(cmd_buffer
->cs
,
970 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
971 radv_cmd_buffer_uses_mec(cmd_buffer
),
972 cmd_buffer
->state
.flush_bits
);
975 if (cmd_buffer
->state
.flush_bits
)
976 radv_cmd_buffer_trace_emit(cmd_buffer
);
977 cmd_buffer
->state
.flush_bits
= 0;
981 /* Set this if you want the 3D engine to wait until CP DMA is done.
982 * It should be set on the last CP DMA packet. */
983 #define CP_DMA_SYNC (1 << 0)
985 /* Set this if the source data was used as a destination in a previous CP DMA
986 * packet. It's for preventing a read-after-write (RAW) hazard between two
988 #define CP_DMA_RAW_WAIT (1 << 1)
989 #define CP_DMA_USE_L2 (1 << 2)
990 #define CP_DMA_CLEAR (1 << 3)
992 /* Alignment for optimal performance. */
993 #define SI_CPDMA_ALIGNMENT 32
995 /* The max number of bytes that can be copied per packet. */
996 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer
*cmd_buffer
)
998 unsigned max
= S_414_BYTE_COUNT_GFX6(~0u);
1000 /* make it aligned for optimal performance */
1001 return max
& ~(SI_CPDMA_ALIGNMENT
- 1);
1004 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1005 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1008 static void si_emit_cp_dma(struct radv_cmd_buffer
*cmd_buffer
,
1009 uint64_t dst_va
, uint64_t src_va
,
1010 unsigned size
, unsigned flags
)
1012 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
1013 uint32_t header
= 0, command
= 0;
1016 assert(size
<= cp_dma_max_byte_count(cmd_buffer
));
1018 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 9);
1020 command
|= S_414_BYTE_COUNT_GFX6(size
);
1023 if (flags
& CP_DMA_SYNC
)
1024 header
|= S_411_CP_SYNC(1);
1026 command
|= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1029 if (flags
& CP_DMA_RAW_WAIT
)
1030 command
|= S_414_RAW_WAIT(1);
1032 /* Src and dst flags. */
1033 if (flags
& CP_DMA_USE_L2
)
1034 header
|= S_411_DSL_SEL(V_411_DST_ADDR_TC_L2
);
1036 if (flags
& CP_DMA_CLEAR
)
1037 header
|= S_411_SRC_SEL(V_411_DATA
);
1038 else if (flags
& CP_DMA_USE_L2
)
1039 header
|= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2
);
1041 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1042 radeon_emit(cs
, PKT3(PKT3_DMA_DATA
, 5, 0));
1043 radeon_emit(cs
, header
);
1044 radeon_emit(cs
, src_va
); /* SRC_ADDR_LO [31:0] */
1045 radeon_emit(cs
, src_va
>> 32); /* SRC_ADDR_HI [31:0] */
1046 radeon_emit(cs
, dst_va
); /* DST_ADDR_LO [31:0] */
1047 radeon_emit(cs
, dst_va
>> 32); /* DST_ADDR_HI [31:0] */
1048 radeon_emit(cs
, command
);
1050 header
|= S_411_SRC_ADDR_HI(src_va
>> 32);
1051 radeon_emit(cs
, PKT3(PKT3_CP_DMA
, 4, 0));
1052 radeon_emit(cs
, src_va
); /* SRC_ADDR_LO [31:0] */
1053 radeon_emit(cs
, header
); /* SRC_ADDR_HI [15:0] + flags. */
1054 radeon_emit(cs
, dst_va
); /* DST_ADDR_LO [31:0] */
1055 radeon_emit(cs
, (dst_va
>> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1056 radeon_emit(cs
, command
);
1059 /* CP DMA is executed in ME, but index buffers are read by PFP.
1060 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1061 * indices. If we wanted to execute CP DMA in PFP, this packet
1062 * should precede it.
1064 if ((flags
& CP_DMA_SYNC
) && cmd_buffer
->queue_family_index
== RADV_QUEUE_GENERAL
) {
1065 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1069 radv_cmd_buffer_trace_emit(cmd_buffer
);
1072 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1075 uint64_t aligned_va
= va
& ~(SI_CPDMA_ALIGNMENT
- 1);
1076 uint64_t aligned_size
= ((va
+ size
+ SI_CPDMA_ALIGNMENT
-1) & ~(SI_CPDMA_ALIGNMENT
- 1)) - aligned_va
;
1078 si_emit_cp_dma(cmd_buffer
, aligned_va
, aligned_va
,
1079 aligned_size
, CP_DMA_USE_L2
);
1082 static void si_cp_dma_prepare(struct radv_cmd_buffer
*cmd_buffer
, uint64_t byte_count
,
1083 uint64_t remaining_size
, unsigned *flags
)
1086 /* Flush the caches for the first copy only.
1087 * Also wait for the previous CP DMA operations.
1089 if (cmd_buffer
->state
.flush_bits
) {
1090 si_emit_cache_flush(cmd_buffer
);
1091 *flags
|= CP_DMA_RAW_WAIT
;
1094 /* Do the synchronization after the last dma, so that all data
1095 * is written to memory.
1097 if (byte_count
== remaining_size
)
1098 *flags
|= CP_DMA_SYNC
;
1101 static void si_cp_dma_realign_engine(struct radv_cmd_buffer
*cmd_buffer
, unsigned size
)
1105 unsigned dma_flags
= 0;
1106 unsigned buf_size
= SI_CPDMA_ALIGNMENT
* 2;
1109 assert(size
< SI_CPDMA_ALIGNMENT
);
1111 radv_cmd_buffer_upload_alloc(cmd_buffer
, buf_size
, SI_CPDMA_ALIGNMENT
, &offset
, &ptr
);
1113 va
= cmd_buffer
->device
->ws
->buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1116 si_cp_dma_prepare(cmd_buffer
, size
, size
, &dma_flags
);
1118 si_emit_cp_dma(cmd_buffer
, va
, va
+ SI_CPDMA_ALIGNMENT
, size
,
1122 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1123 uint64_t src_va
, uint64_t dest_va
,
1126 uint64_t main_src_va
, main_dest_va
;
1127 uint64_t skipped_size
= 0, realign_size
= 0;
1130 if (cmd_buffer
->device
->physical_device
->rad_info
.family
<= CHIP_CARRIZO
||
1131 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_STONEY
) {
1132 /* If the size is not aligned, we must add a dummy copy at the end
1133 * just to align the internal counter. Otherwise, the DMA engine
1134 * would slow down by an order of magnitude for following copies.
1136 if (size
% SI_CPDMA_ALIGNMENT
)
1137 realign_size
= SI_CPDMA_ALIGNMENT
- (size
% SI_CPDMA_ALIGNMENT
);
1139 /* If the copy begins unaligned, we must start copying from the next
1140 * aligned block and the skipped part should be copied after everything
1141 * else has been copied. Only the src alignment matters, not dst.
1143 if (src_va
% SI_CPDMA_ALIGNMENT
) {
1144 skipped_size
= SI_CPDMA_ALIGNMENT
- (src_va
% SI_CPDMA_ALIGNMENT
);
1145 /* The main part will be skipped if the size is too small. */
1146 skipped_size
= MIN2(skipped_size
, size
);
1147 size
-= skipped_size
;
1150 main_src_va
= src_va
+ skipped_size
;
1151 main_dest_va
= dest_va
+ skipped_size
;
1154 unsigned dma_flags
= 0;
1155 unsigned byte_count
= MIN2(size
, cp_dma_max_byte_count(cmd_buffer
));
1157 si_cp_dma_prepare(cmd_buffer
, byte_count
,
1158 size
+ skipped_size
+ realign_size
,
1161 si_emit_cp_dma(cmd_buffer
, main_dest_va
, main_src_va
,
1162 byte_count
, dma_flags
);
1165 main_src_va
+= byte_count
;
1166 main_dest_va
+= byte_count
;
1170 unsigned dma_flags
= 0;
1172 si_cp_dma_prepare(cmd_buffer
, skipped_size
,
1173 size
+ skipped_size
+ realign_size
,
1176 si_emit_cp_dma(cmd_buffer
, dest_va
, src_va
,
1177 skipped_size
, dma_flags
);
1180 si_cp_dma_realign_engine(cmd_buffer
, realign_size
);
1183 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1184 uint64_t size
, unsigned value
)
1190 assert(va
% 4 == 0 && size
% 4 == 0);
1193 unsigned byte_count
= MIN2(size
, cp_dma_max_byte_count(cmd_buffer
));
1194 unsigned dma_flags
= CP_DMA_CLEAR
;
1196 si_cp_dma_prepare(cmd_buffer
, byte_count
, size
, &dma_flags
);
1198 /* Emit the clear packet. */
1199 si_emit_cp_dma(cmd_buffer
, va
, value
, byte_count
,
1207 /* For MSAA sample positions. */
1208 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1209 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
1210 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1211 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1212 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1216 * There are two locations (4, 4), (-4, -4). */
1217 const uint32_t eg_sample_locs_2x
[4] = {
1218 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1219 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1220 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1221 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1223 const unsigned eg_max_dist_2x
= 4;
1225 * There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
1226 const uint32_t eg_sample_locs_4x
[4] = {
1227 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1228 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1229 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1230 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1232 const unsigned eg_max_dist_4x
= 6;
1235 static const uint32_t cm_sample_locs_8x
[] = {
1236 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1237 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1238 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1239 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1240 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1241 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1242 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1243 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1245 static const unsigned cm_max_dist_8x
= 8;
1246 /* Cayman 16xMSAA */
1247 static const uint32_t cm_sample_locs_16x
[] = {
1248 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1249 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1250 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1251 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1252 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1253 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1254 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1255 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1256 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1257 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1258 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1259 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1260 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1261 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1262 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1263 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1265 static const unsigned cm_max_dist_16x
= 8;
1267 unsigned radv_cayman_get_maxdist(int log_samples
)
1269 unsigned max_dist
[] = {
1276 return max_dist
[log_samples
];
1279 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
)
1281 switch (nr_samples
) {
1284 radeon_set_context_reg(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 0);
1285 radeon_set_context_reg(cs
, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, 0);
1286 radeon_set_context_reg(cs
, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, 0);
1287 radeon_set_context_reg(cs
, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, 0);
1290 radeon_set_context_reg(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, eg_sample_locs_2x
[0]);
1291 radeon_set_context_reg(cs
, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, eg_sample_locs_2x
[1]);
1292 radeon_set_context_reg(cs
, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, eg_sample_locs_2x
[2]);
1293 radeon_set_context_reg(cs
, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, eg_sample_locs_2x
[3]);
1296 radeon_set_context_reg(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, eg_sample_locs_4x
[0]);
1297 radeon_set_context_reg(cs
, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, eg_sample_locs_4x
[1]);
1298 radeon_set_context_reg(cs
, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, eg_sample_locs_4x
[2]);
1299 radeon_set_context_reg(cs
, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, eg_sample_locs_4x
[3]);
1302 radeon_set_context_reg_seq(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 14);
1303 radeon_emit(cs
, cm_sample_locs_8x
[0]);
1304 radeon_emit(cs
, cm_sample_locs_8x
[4]);
1307 radeon_emit(cs
, cm_sample_locs_8x
[1]);
1308 radeon_emit(cs
, cm_sample_locs_8x
[5]);
1311 radeon_emit(cs
, cm_sample_locs_8x
[2]);
1312 radeon_emit(cs
, cm_sample_locs_8x
[6]);
1315 radeon_emit(cs
, cm_sample_locs_8x
[3]);
1316 radeon_emit(cs
, cm_sample_locs_8x
[7]);
1319 radeon_set_context_reg_seq(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 16);
1320 radeon_emit(cs
, cm_sample_locs_16x
[0]);
1321 radeon_emit(cs
, cm_sample_locs_16x
[4]);
1322 radeon_emit(cs
, cm_sample_locs_16x
[8]);
1323 radeon_emit(cs
, cm_sample_locs_16x
[12]);
1324 radeon_emit(cs
, cm_sample_locs_16x
[1]);
1325 radeon_emit(cs
, cm_sample_locs_16x
[5]);
1326 radeon_emit(cs
, cm_sample_locs_16x
[9]);
1327 radeon_emit(cs
, cm_sample_locs_16x
[13]);
1328 radeon_emit(cs
, cm_sample_locs_16x
[2]);
1329 radeon_emit(cs
, cm_sample_locs_16x
[6]);
1330 radeon_emit(cs
, cm_sample_locs_16x
[10]);
1331 radeon_emit(cs
, cm_sample_locs_16x
[14]);
1332 radeon_emit(cs
, cm_sample_locs_16x
[3]);
1333 radeon_emit(cs
, cm_sample_locs_16x
[7]);
1334 radeon_emit(cs
, cm_sample_locs_16x
[11]);
1335 radeon_emit(cs
, cm_sample_locs_16x
[15]);
1340 static void radv_cayman_get_sample_position(struct radv_device
*device
,
1341 unsigned sample_count
,
1342 unsigned sample_index
, float *out_value
)
1348 switch (sample_count
) {
1351 out_value
[0] = out_value
[1] = 0.5;
1354 offset
= 4 * (sample_index
* 2);
1355 val
.idx
= (eg_sample_locs_2x
[0] >> offset
) & 0xf;
1356 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1357 val
.idx
= (eg_sample_locs_2x
[0] >> (offset
+ 4)) & 0xf;
1358 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1361 offset
= 4 * (sample_index
* 2);
1362 val
.idx
= (eg_sample_locs_4x
[0] >> offset
) & 0xf;
1363 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1364 val
.idx
= (eg_sample_locs_4x
[0] >> (offset
+ 4)) & 0xf;
1365 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1368 offset
= 4 * (sample_index
% 4 * 2);
1369 index
= (sample_index
/ 4) * 4;
1370 val
.idx
= (cm_sample_locs_8x
[index
] >> offset
) & 0xf;
1371 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1372 val
.idx
= (cm_sample_locs_8x
[index
] >> (offset
+ 4)) & 0xf;
1373 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1376 offset
= 4 * (sample_index
% 4 * 2);
1377 index
= (sample_index
/ 4) * 4;
1378 val
.idx
= (cm_sample_locs_16x
[index
] >> offset
) & 0xf;
1379 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1380 val
.idx
= (cm_sample_locs_16x
[index
] >> (offset
+ 4)) & 0xf;
1381 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1386 void radv_device_init_msaa(struct radv_device
*device
)
1389 radv_cayman_get_sample_position(device
, 1, 0, device
->sample_locations_1x
[0]);
1391 for (i
= 0; i
< 2; i
++)
1392 radv_cayman_get_sample_position(device
, 2, i
, device
->sample_locations_2x
[i
]);
1393 for (i
= 0; i
< 4; i
++)
1394 radv_cayman_get_sample_position(device
, 4, i
, device
->sample_locations_4x
[i
]);
1395 for (i
= 0; i
< 8; i
++)
1396 radv_cayman_get_sample_position(device
, 8, i
, device
->sample_locations_8x
[i
]);
1397 for (i
= 0; i
< 16; i
++)
1398 radv_cayman_get_sample_position(device
, 16, i
, device
->sample_locations_16x
[i
]);