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radv: add ia_multi_vgt_param tessellation support.
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for SI */
29
30 #include "radv_private.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "radv_util.h"
34 #include "main/macros.h"
35
36 #define SI_GS_PER_ES 128
37
38 static void
39 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
40 struct radeon_winsys_cs *cs,
41 unsigned raster_config,
42 unsigned raster_config_1)
43 {
44 unsigned sh_per_se = MAX2(physical_device->rad_info.max_sh_per_se, 1);
45 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
46 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
47 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
48 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
49 unsigned rb_per_se = num_rb / num_se;
50 unsigned se_mask[4];
51 unsigned se;
52
53 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
54 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
55 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
56 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
57
58 assert(num_se == 1 || num_se == 2 || num_se == 4);
59 assert(sh_per_se == 1 || sh_per_se == 2);
60 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
61
62 /* XXX: I can't figure out what the *_XSEL and *_YSEL
63 * fields are for, so I'm leaving them as their default
64 * values. */
65
66 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
67 (!se_mask[2] && !se_mask[3]))) {
68 raster_config_1 &= C_028354_SE_PAIR_MAP;
69
70 if (!se_mask[0] && !se_mask[1]) {
71 raster_config_1 |=
72 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
73 } else {
74 raster_config_1 |=
75 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
76 }
77 }
78
79 for (se = 0; se < num_se; se++) {
80 unsigned raster_config_se = raster_config;
81 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
82 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
83 int idx = (se / 2) * 2;
84
85 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
86 raster_config_se &= C_028350_SE_MAP;
87
88 if (!se_mask[idx]) {
89 raster_config_se |=
90 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
91 } else {
92 raster_config_se |=
93 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
94 }
95 }
96
97 pkr0_mask &= rb_mask;
98 pkr1_mask &= rb_mask;
99 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
100 raster_config_se &= C_028350_PKR_MAP;
101
102 if (!pkr0_mask) {
103 raster_config_se |=
104 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
105 } else {
106 raster_config_se |=
107 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
108 }
109 }
110
111 if (rb_per_se >= 2) {
112 unsigned rb0_mask = 1 << (se * rb_per_se);
113 unsigned rb1_mask = rb0_mask << 1;
114
115 rb0_mask &= rb_mask;
116 rb1_mask &= rb_mask;
117 if (!rb0_mask || !rb1_mask) {
118 raster_config_se &= C_028350_RB_MAP_PKR0;
119
120 if (!rb0_mask) {
121 raster_config_se |=
122 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
123 } else {
124 raster_config_se |=
125 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
126 }
127 }
128
129 if (rb_per_se > 2) {
130 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
131 rb1_mask = rb0_mask << 1;
132 rb0_mask &= rb_mask;
133 rb1_mask &= rb_mask;
134 if (!rb0_mask || !rb1_mask) {
135 raster_config_se &= C_028350_RB_MAP_PKR1;
136
137 if (!rb0_mask) {
138 raster_config_se |=
139 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
140 } else {
141 raster_config_se |=
142 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
143 }
144 }
145 }
146 }
147
148 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
149 if (physical_device->rad_info.chip_class < CIK)
150 radeon_set_config_reg(cs, GRBM_GFX_INDEX,
151 SE_INDEX(se) | SH_BROADCAST_WRITES |
152 INSTANCE_BROADCAST_WRITES);
153 else
154 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
155 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
156 S_030800_INSTANCE_BROADCAST_WRITES(1));
157 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
158 if (physical_device->rad_info.chip_class >= CIK)
159 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
160 }
161
162 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
163 if (physical_device->rad_info.chip_class < CIK)
164 radeon_set_config_reg(cs, GRBM_GFX_INDEX,
165 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
166 INSTANCE_BROADCAST_WRITES);
167 else
168 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
169 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
170 S_030800_INSTANCE_BROADCAST_WRITES(1));
171 }
172
173 static void
174 si_emit_compute(struct radv_physical_device *physical_device,
175 struct radeon_winsys_cs *cs)
176 {
177 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
178 radeon_emit(cs, 0);
179 radeon_emit(cs, 0);
180 radeon_emit(cs, 0);
181
182 radeon_set_sh_reg_seq(cs, R_00B854_COMPUTE_RESOURCE_LIMITS, 3);
183 radeon_emit(cs, 0);
184 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
185 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
186 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
187
188 if (physical_device->rad_info.chip_class >= CIK) {
189 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
190 radeon_set_sh_reg_seq(cs,
191 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
192 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
193 S_00B864_SH1_CU_EN(0xffff));
194 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
195 S_00B868_SH1_CU_EN(0xffff));
196 }
197
198 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
199 * and is now per pipe, so it should be handled in the
200 * kernel if we want to use something other than the default value,
201 * which is now 0x22f.
202 */
203 if (physical_device->rad_info.chip_class <= SI) {
204 /* XXX: This should be:
205 * (number of compute units) * 4 * (waves per simd) - 1 */
206
207 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
208 0x190 /* Default value */);
209 }
210 }
211
212 void
213 si_init_compute(struct radv_cmd_buffer *cmd_buffer)
214 {
215 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
216 si_emit_compute(physical_device, cmd_buffer->cs);
217 }
218
219 static void
220 si_emit_config(struct radv_physical_device *physical_device,
221 struct radeon_winsys_cs *cs)
222 {
223 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
224 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
225 unsigned raster_config, raster_config_1;
226 int i;
227
228 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
229 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
230 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
231
232 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
233 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
234
235 /* FIXME calculate these values somehow ??? */
236 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
237 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
238 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
239
240 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
241 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
242
243 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
244 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
245 if (physical_device->rad_info.chip_class < CIK)
246 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
247 S_008A14_CLIP_VTX_REORDER_ENA(1));
248
249 radeon_set_context_reg(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
250 radeon_set_context_reg(cs, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
251
252 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
253
254 for (i = 0; i < 16; i++) {
255 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
256 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
257 }
258
259 switch (physical_device->rad_info.family) {
260 case CHIP_TAHITI:
261 case CHIP_PITCAIRN:
262 raster_config = 0x2a00126a;
263 raster_config_1 = 0x00000000;
264 break;
265 case CHIP_VERDE:
266 raster_config = 0x0000124a;
267 raster_config_1 = 0x00000000;
268 break;
269 case CHIP_OLAND:
270 raster_config = 0x00000082;
271 raster_config_1 = 0x00000000;
272 break;
273 case CHIP_HAINAN:
274 raster_config = 0x00000000;
275 raster_config_1 = 0x00000000;
276 break;
277 case CHIP_BONAIRE:
278 raster_config = 0x16000012;
279 raster_config_1 = 0x00000000;
280 break;
281 case CHIP_HAWAII:
282 raster_config = 0x3a00161a;
283 raster_config_1 = 0x0000002e;
284 break;
285 case CHIP_FIJI:
286 if (physical_device->rad_info.cik_macrotile_mode_array[0] == 0x000000e8) {
287 /* old kernels with old tiling config */
288 raster_config = 0x16000012;
289 raster_config_1 = 0x0000002a;
290 } else {
291 raster_config = 0x3a00161a;
292 raster_config_1 = 0x0000002e;
293 }
294 break;
295 case CHIP_POLARIS10:
296 raster_config = 0x16000012;
297 raster_config_1 = 0x0000002a;
298 break;
299 case CHIP_POLARIS11:
300 raster_config = 0x16000012;
301 raster_config_1 = 0x00000000;
302 break;
303 case CHIP_TONGA:
304 raster_config = 0x16000012;
305 raster_config_1 = 0x0000002a;
306 break;
307 case CHIP_ICELAND:
308 if (num_rb == 1)
309 raster_config = 0x00000000;
310 else
311 raster_config = 0x00000002;
312 raster_config_1 = 0x00000000;
313 break;
314 case CHIP_CARRIZO:
315 raster_config = 0x00000002;
316 raster_config_1 = 0x00000000;
317 break;
318 case CHIP_KAVERI:
319 /* KV should be 0x00000002, but that causes problems with radeon */
320 raster_config = 0x00000000; /* 0x00000002 */
321 raster_config_1 = 0x00000000;
322 break;
323 case CHIP_KABINI:
324 case CHIP_MULLINS:
325 case CHIP_STONEY:
326 raster_config = 0x00000000;
327 raster_config_1 = 0x00000000;
328 break;
329 default:
330 fprintf(stderr,
331 "radeonsi: Unknown GPU, using 0 for raster_config\n");
332 raster_config = 0x00000000;
333 raster_config_1 = 0x00000000;
334 break;
335 }
336
337 /* Always use the default config when all backends are enabled
338 * (or when we failed to determine the enabled backends).
339 */
340 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
341 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
342 raster_config);
343 if (physical_device->rad_info.chip_class >= CIK)
344 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
345 raster_config_1);
346 } else {
347 si_write_harvested_raster_configs(physical_device, cs, raster_config, raster_config_1);
348 }
349
350 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
351 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
352 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
353 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
354 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
355 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
356 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
357
358 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
359 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
360 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
361 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
362 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
363
364 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
365 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
366 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
367 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
368 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
369 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
370
371 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
372 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
373 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
374
375 if (physical_device->rad_info.chip_class >= CIK) {
376 /* If this is 0, Bonaire can hang even if GS isn't being used.
377 * Other chips are unaffected. These are suboptimal values,
378 * but we don't use on-chip GS.
379 */
380 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
381 S_028A44_ES_VERTS_PER_SUBGRP(64) |
382 S_028A44_GS_PRIMS_PER_SUBGRP(4));
383
384 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
385 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
386 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
387 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
388
389 if (physical_device->rad_info.num_good_compute_units /
390 (physical_device->rad_info.max_se * physical_device->rad_info.max_sh_per_se) <= 4) {
391 /* Too few available compute units per SH. Disallowing
392 * VS to run on CU0 could hurt us more than late VS
393 * allocation would help.
394 *
395 * LATE_ALLOC_VS = 2 is the highest safe number.
396 */
397 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
398 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
399 } else {
400 /* Set LATE_ALLOC_VS == 31. It should be less than
401 * the number of scratch waves. Limitations:
402 * - VS can't execute on CU0.
403 * - If HS writes outputs to LDS, LS can't execute on CU0.
404 */
405 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
406 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
407 }
408
409 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
410 }
411
412 if (physical_device->rad_info.chip_class >= VI) {
413 uint32_t vgt_tess_distribution;
414 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
415 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
416 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
417 if (physical_device->rad_info.family < CHIP_POLARIS10)
418 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
419 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
420
421 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
422 S_028B50_ACCUM_TRI(11) |
423 S_028B50_ACCUM_QUAD(11) |
424 S_028B50_DONUT_SPLIT(16);
425
426 if (physical_device->rad_info.family == CHIP_FIJI ||
427 physical_device->rad_info.family >= CHIP_POLARIS10)
428 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
429
430 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
431 vgt_tess_distribution);
432 } else {
433 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
434 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
435 }
436
437 if (physical_device->rad_info.family == CHIP_STONEY)
438 radeon_set_context_reg(cs, R_028C40_PA_SC_SHADER_CONTROL, 0);
439
440 si_emit_compute(physical_device, cs);
441 }
442
443 void si_init_config(struct radv_cmd_buffer *cmd_buffer)
444 {
445 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
446
447 si_emit_config(physical_device, cmd_buffer->cs);
448 }
449
450 void
451 cik_create_gfx_config(struct radv_device *device)
452 {
453 struct radeon_winsys_cs *cs = device->ws->cs_create(device->ws, RING_GFX);
454 if (!cs)
455 return;
456
457 si_emit_config(device->physical_device, cs);
458
459 while (cs->cdw & 7) {
460 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
461 radeon_emit(cs, 0x80000000);
462 else
463 radeon_emit(cs, 0xffff1000);
464 }
465
466 device->gfx_init = device->ws->buffer_create(device->ws,
467 cs->cdw * 4, 4096,
468 RADEON_DOMAIN_GTT,
469 RADEON_FLAG_CPU_ACCESS);
470 if (!device->gfx_init)
471 goto fail;
472
473 void *map = device->ws->buffer_map(device->gfx_init);
474 if (!map) {
475 device->ws->buffer_destroy(device->gfx_init);
476 device->gfx_init = NULL;
477 goto fail;
478 }
479 memcpy(map, cs->buf, cs->cdw * 4);
480
481 device->ws->buffer_unmap(device->gfx_init);
482 device->gfx_init_size_dw = cs->cdw;
483 fail:
484 device->ws->cs_destroy(cs);
485 }
486
487 static void
488 get_viewport_xform(const VkViewport *viewport,
489 float scale[3], float translate[3])
490 {
491 float x = viewport->x;
492 float y = viewport->y;
493 float half_width = 0.5f * viewport->width;
494 float half_height = 0.5f * viewport->height;
495 double n = viewport->minDepth;
496 double f = viewport->maxDepth;
497
498 scale[0] = half_width;
499 translate[0] = half_width + x;
500 scale[1] = half_height;
501 translate[1] = half_height + y;
502
503 scale[2] = (f - n);
504 translate[2] = n;
505 }
506
507 static void
508 get_viewport_xform_scissor(const VkRect2D *scissor,
509 float scale[2], float translate[2])
510 {
511 float x = scissor->offset.x;
512 float y = scissor->offset.y;
513 float half_width = 0.5f * scissor->extent.width;
514 float half_height = 0.5f * scissor->extent.height;
515
516 scale[0] = half_width;
517 translate[0] = half_width + x;
518 scale[1] = half_height;
519 translate[1] = half_height + y;
520
521 }
522
523 void
524 si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
525 int count, const VkViewport *viewports)
526 {
527 int i;
528
529 assert(count);
530 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
531 first_vp * 4 * 6, count * 6);
532
533 for (i = 0; i < count; i++) {
534 float scale[3], translate[3];
535
536
537 get_viewport_xform(&viewports[i], scale, translate);
538 radeon_emit(cs, fui(scale[0]));
539 radeon_emit(cs, fui(translate[0]));
540 radeon_emit(cs, fui(scale[1]));
541 radeon_emit(cs, fui(translate[1]));
542 radeon_emit(cs, fui(scale[2]));
543 radeon_emit(cs, fui(translate[2]));
544 }
545
546 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
547 first_vp * 4 * 2, count * 2);
548 for (i = 0; i < count; i++) {
549 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
550 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
551 radeon_emit(cs, fui(zmin));
552 radeon_emit(cs, fui(zmax));
553 }
554 }
555
556 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
557 {
558 float scale[3], translate[3];
559 VkRect2D rect;
560
561 get_viewport_xform(viewport, scale, translate);
562
563 rect.offset.x = translate[0] - abs(scale[0]);
564 rect.offset.y = translate[1] - abs(scale[1]);
565 rect.extent.width = ceilf(translate[0] + abs(scale[0])) - rect.offset.x;
566 rect.extent.height = ceilf(translate[1] + abs(scale[1])) - rect.offset.y;
567
568 return rect;
569 }
570
571 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
572 VkRect2D ret;
573 ret.offset.x = MAX2(a->offset.x, b->offset.x);
574 ret.offset.y = MAX2(a->offset.y, b->offset.y);
575 ret.extent.width = MIN2(a->offset.x + a->extent.width,
576 b->offset.x + b->extent.width) - ret.offset.x;
577 ret.extent.height = MIN2(a->offset.y + a->extent.height,
578 b->offset.y + b->extent.height) - ret.offset.y;
579 return ret;
580 }
581
582 static VkRect2D si_union_scissor(const VkRect2D *a, const VkRect2D *b) {
583 VkRect2D ret;
584 ret.offset.x = MIN2(a->offset.x, b->offset.x);
585 ret.offset.y = MIN2(a->offset.y, b->offset.y);
586 ret.extent.width = MAX2(a->offset.x + a->extent.width,
587 b->offset.x + b->extent.width) - ret.offset.x;
588 ret.extent.height = MAX2(a->offset.y + a->extent.height,
589 b->offset.y + b->extent.height) - ret.offset.y;
590 return ret;
591 }
592
593
594 void
595 si_write_scissors(struct radeon_winsys_cs *cs, int first,
596 int count, const VkRect2D *scissors,
597 const VkViewport *viewports, bool can_use_guardband)
598 {
599 int i;
600 VkRect2D merged;
601 float scale[2], translate[2], guardband_x = 1.0, guardband_y = 1.0;
602 const float max_range = 32767.0f;
603 assert(count);
604
605 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
606 for (i = 0; i < count; i++) {
607 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
608 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
609
610 if (i)
611 merged = si_union_scissor(&merged, &scissor);
612 else
613 merged = scissor;
614
615 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
616 S_028250_TL_Y(scissor.offset.y) |
617 S_028250_WINDOW_OFFSET_DISABLE(1));
618 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
619 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
620 }
621
622 get_viewport_xform_scissor(&merged, scale, translate);
623
624 if (can_use_guardband) {
625 guardband_x = (max_range - abs(translate[0])) / scale[0];
626 guardband_y = (max_range - abs(translate[1])) / scale[1];
627 }
628
629 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
630 radeon_emit(cs, fui(guardband_x));
631 radeon_emit(cs, fui(1.0));
632 radeon_emit(cs, fui(guardband_y));
633 radeon_emit(cs, fui(1.0));
634 }
635
636 static inline unsigned
637 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
638 {
639 if (num == 0)
640 return 0;
641
642 if (info->incr == 0)
643 return 0;
644
645 if (num < info->min)
646 return 0;
647
648 return 1 + ((num - info->min) / info->incr);
649 }
650
651 uint32_t
652 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
653 bool instanced_draw, bool indirect_draw,
654 uint32_t draw_vertex_count)
655 {
656 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
657 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
658 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
659 unsigned prim = cmd_buffer->state.pipeline->graphics.prim;
660 unsigned primgroup_size = 128; /* recommended without a GS */
661 unsigned max_primgroup_in_wave = 2;
662 /* SWITCH_ON_EOP(0) is always preferable. */
663 bool wd_switch_on_eop = false;
664 bool ia_switch_on_eop = false;
665 bool ia_switch_on_eoi = false;
666 bool partial_vs_wave = false;
667 bool partial_es_wave = false;
668 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
669 bool multi_instances_smaller_than_primgroup;
670
671 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
672 primgroup_size = cmd_buffer->state.pipeline->graphics.tess.num_patches;
673 else if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
674 primgroup_size = 64; /* recommended with a GS */
675
676 multi_instances_smaller_than_primgroup = indirect_draw || (instanced_draw &&
677 num_prims < primgroup_size);
678 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline)) {
679 /* SWITCH_ON_EOI must be set if PrimID is used. */
680 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.uses_prim_id ||
681 cmd_buffer->state.pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.uses_prim_id)
682 ia_switch_on_eoi = true;
683
684 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
685 if ((family == CHIP_TAHITI ||
686 family == CHIP_PITCAIRN ||
687 family == CHIP_BONAIRE) &&
688 radv_pipeline_has_gs(cmd_buffer->state.pipeline))
689 partial_vs_wave = true;
690
691 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
692 if (cmd_buffer->device->has_distributed_tess) {
693 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
694 partial_es_wave = true;
695
696 if (family == CHIP_TONGA ||
697 family == CHIP_FIJI ||
698 family == CHIP_POLARIS10 ||
699 family == CHIP_POLARIS11)
700 partial_vs_wave = true;
701 } else {
702 partial_vs_wave = true;
703 }
704 }
705 }
706 /* TODO linestipple */
707
708 if (chip_class >= CIK) {
709 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
710 * 4 shader engines. Set 1 to pass the assertion below.
711 * The other cases are hardware requirements. */
712 if (info->max_se < 4 ||
713 prim == V_008958_DI_PT_POLYGON ||
714 prim == V_008958_DI_PT_LINELOOP ||
715 prim == V_008958_DI_PT_TRIFAN ||
716 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
717 (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
718 (family < CHIP_POLARIS10 ||
719 (prim != V_008958_DI_PT_POINTLIST &&
720 prim != V_008958_DI_PT_LINESTRIP &&
721 prim != V_008958_DI_PT_TRISTRIP))))
722 wd_switch_on_eop = true;
723
724 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
725 * We don't know that for indirect drawing, so treat it as
726 * always problematic. */
727 if (family == CHIP_HAWAII &&
728 (instanced_draw || indirect_draw))
729 wd_switch_on_eop = true;
730
731 /* Performance recommendation for 4 SE Gfx7-8 parts if
732 * instances are smaller than a primgroup.
733 * Assume indirect draws always use small instances.
734 * This is needed for good VS wave utilization.
735 */
736 if (chip_class <= VI &&
737 info->max_se == 4 &&
738 multi_instances_smaller_than_primgroup)
739 wd_switch_on_eop = true;
740
741 /* Required on CIK and later. */
742 if (info->max_se > 2 && !wd_switch_on_eop)
743 ia_switch_on_eoi = true;
744
745 /* Required by Hawaii and, for some special cases, by VI. */
746 if (ia_switch_on_eoi &&
747 (family == CHIP_HAWAII ||
748 (chip_class == VI &&
749 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
750 partial_vs_wave = true;
751
752 /* Instancing bug on Bonaire. */
753 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
754 (instanced_draw || indirect_draw))
755 partial_vs_wave = true;
756
757 /* If the WD switch is false, the IA switch must be false too. */
758 assert(wd_switch_on_eop || !ia_switch_on_eop);
759 }
760 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
761 if (ia_switch_on_eoi)
762 partial_es_wave = true;
763
764 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
765 /* GS requirement. */
766 if (SI_GS_PER_ES / primgroup_size >= cmd_buffer->device->gs_table_depth - 3)
767 partial_es_wave = true;
768
769 /* Hw bug with single-primitive instances and SWITCH_ON_EOI
770 * on multi-SE chips. */
771 if (info->max_se >= 2 && ia_switch_on_eoi &&
772 ((instanced_draw || indirect_draw) &&
773 num_prims <= 1))
774 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
775 }
776
777 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
778 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
779 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
780 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
781 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
782 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop : 0) |
783 S_028AA8_MAX_PRIMGRP_IN_WAVE(chip_class >= VI ?
784 max_primgroup_in_wave : 0);
785
786 }
787
788 static void
789 si_emit_acquire_mem(struct radeon_winsys_cs *cs,
790 bool is_mec,
791 unsigned cp_coher_cntl)
792 {
793 if (is_mec) {
794 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0) |
795 PKT3_SHADER_TYPE_S(1));
796 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
797 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
798 radeon_emit(cs, 0xff); /* CP_COHER_SIZE_HI */
799 radeon_emit(cs, 0); /* CP_COHER_BASE */
800 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
801 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
802 } else {
803 /* ACQUIRE_MEM is only required on a compute ring. */
804 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
805 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
806 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
807 radeon_emit(cs, 0); /* CP_COHER_BASE */
808 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
809 }
810 }
811
812 void
813 si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
814 enum chip_class chip_class,
815 bool is_mec,
816 enum radv_cmd_flush_bits flush_bits)
817 {
818 unsigned cp_coher_cntl = 0;
819
820 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
821 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
822 if (flush_bits & RADV_CMD_FLAG_INV_SMEM_L1)
823 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
824
825 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
826 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
827 S_0085F0_CB0_DEST_BASE_ENA(1) |
828 S_0085F0_CB1_DEST_BASE_ENA(1) |
829 S_0085F0_CB2_DEST_BASE_ENA(1) |
830 S_0085F0_CB3_DEST_BASE_ENA(1) |
831 S_0085F0_CB4_DEST_BASE_ENA(1) |
832 S_0085F0_CB5_DEST_BASE_ENA(1) |
833 S_0085F0_CB6_DEST_BASE_ENA(1) |
834 S_0085F0_CB7_DEST_BASE_ENA(1);
835
836 /* Necessary for DCC */
837 if (chip_class >= VI) {
838 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
839 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_DATA_TS) |
840 EVENT_INDEX(5));
841 radeon_emit(cs, 0);
842 radeon_emit(cs, 0);
843 radeon_emit(cs, 0);
844 radeon_emit(cs, 0);
845 }
846 }
847
848 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
849 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
850 S_0085F0_DB_DEST_BASE_ENA(1);
851 }
852
853 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
854 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
855 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
856 }
857
858 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
859 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
860 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
861 }
862
863 if (!(flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
864 RADV_CMD_FLAG_FLUSH_AND_INV_DB))) {
865 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
866 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
867 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
868 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
869 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
870 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
871 }
872 }
873
874 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
875 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
876 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
877 }
878
879 /* VGT state sync */
880 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
881 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
882 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
883 }
884
885 /* Make sure ME is idle (it executes most packets) before continuing.
886 * This prevents read-after-write hazards between PFP and ME.
887 */
888 if ((cp_coher_cntl || (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) &&
889 !is_mec) {
890 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
891 radeon_emit(cs, 0);
892 }
893
894 if ((flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) ||
895 (chip_class <= CIK && (flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) {
896 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
897 if (chip_class >= VI)
898 cp_coher_cntl |= S_0301F0_TC_WB_ACTION_ENA(1);
899 } else if(flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2) {
900 cp_coher_cntl |= S_0301F0_TC_WB_ACTION_ENA(1) |
901 S_0301F0_TC_NC_ACTION_ENA(1);
902
903 /* L2 writeback doesn't combine with L1 invalidate */
904 si_emit_acquire_mem(cs, is_mec, cp_coher_cntl);
905
906 cp_coher_cntl = 0;
907 }
908
909 if (flush_bits & RADV_CMD_FLAG_INV_VMEM_L1)
910 cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
911
912 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
913 * Therefore, it should be last. Done in PFP.
914 */
915 if (cp_coher_cntl)
916 si_emit_acquire_mem(cs, is_mec, cp_coher_cntl);
917 }
918
919 void
920 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
921 {
922 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
923
924 if (is_compute)
925 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
926 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
927 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
928 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
929 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
930 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
931 RADV_CMD_FLAG_VGT_FLUSH);
932
933 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
934
935 si_cs_emit_cache_flush(cmd_buffer->cs,
936 cmd_buffer->device->physical_device->rad_info.chip_class,
937 radv_cmd_buffer_uses_mec(cmd_buffer),
938 cmd_buffer->state.flush_bits);
939
940
941 if (cmd_buffer->state.flush_bits)
942 radv_cmd_buffer_trace_emit(cmd_buffer);
943 cmd_buffer->state.flush_bits = 0;
944 }
945
946
947 /* Set this if you want the 3D engine to wait until CP DMA is done.
948 * It should be set on the last CP DMA packet. */
949 #define R600_CP_DMA_SYNC (1 << 0) /* R600+ */
950
951 /* Set this if the source data was used as a destination in a previous CP DMA
952 * packet. It's for preventing a read-after-write (RAW) hazard between two
953 * CP DMA packets. */
954 #define SI_CP_DMA_RAW_WAIT (1 << 1) /* SI+ */
955 #define CIK_CP_DMA_USE_L2 (1 << 2)
956
957 /* Alignment for optimal performance. */
958 #define CP_DMA_ALIGNMENT 32
959 /* The max number of bytes to copy per packet. */
960 #define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - CP_DMA_ALIGNMENT)
961
962 static void si_emit_cp_dma_copy_buffer(struct radv_cmd_buffer *cmd_buffer,
963 uint64_t dst_va, uint64_t src_va,
964 unsigned size, unsigned flags)
965 {
966 struct radeon_winsys_cs *cs = cmd_buffer->cs;
967 uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? S_411_CP_SYNC(1) : 0;
968 uint32_t wr_confirm = !(flags & R600_CP_DMA_SYNC) ? S_414_DISABLE_WR_CONFIRM_GFX6(1) : 0;
969 uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? S_414_RAW_WAIT(1) : 0;
970 uint32_t sel = flags & CIK_CP_DMA_USE_L2 ?
971 S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2) |
972 S_411_DSL_SEL(V_411_DST_ADDR_TC_L2) : 0;
973
974 assert(size);
975 assert((size & ((1<<21)-1)) == size);
976
977 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
978
979 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
980 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
981 radeon_emit(cs, sync_flag | sel); /* CP_SYNC [31] */
982 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
983 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
984 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
985 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
986 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
987 } else {
988 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
989 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
990 radeon_emit(cs, sync_flag | ((src_va >> 32) & 0xffff)); /* CP_SYNC [31] | SRC_ADDR_HI [15:0] */
991 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
992 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
993 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
994 }
995
996 /* CP DMA is executed in ME, but index buffers are read by PFP.
997 * This ensures that ME (CP DMA) is idle before PFP starts fetching
998 * indices. If we wanted to execute CP DMA in PFP, this packet
999 * should precede it.
1000 */
1001 if (sync_flag && cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1002 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1003 radeon_emit(cs, 0);
1004 }
1005
1006 radv_cmd_buffer_trace_emit(cmd_buffer);
1007 }
1008
1009 /* Emit a CP DMA packet to clear a buffer. The size must fit in bits [20:0]. */
1010 static void si_emit_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer,
1011 uint64_t dst_va, unsigned size,
1012 uint32_t clear_value, unsigned flags)
1013 {
1014 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1015 uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? S_411_CP_SYNC(1) : 0;
1016 uint32_t wr_confirm = !(flags & R600_CP_DMA_SYNC) ? S_414_DISABLE_WR_CONFIRM_GFX6(1) : 0;
1017 uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? S_414_RAW_WAIT(1) : 0;
1018 uint32_t dst_sel = flags & CIK_CP_DMA_USE_L2 ? S_411_DSL_SEL(V_411_DST_ADDR_TC_L2) : 0;
1019
1020 assert(size);
1021 assert((size & ((1<<21)-1)) == size);
1022
1023 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1024
1025 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1026 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
1027 radeon_emit(cs, sync_flag | dst_sel | S_411_SRC_SEL(V_411_DATA)); /* CP_SYNC [31] | SRC_SEL[30:29] */
1028 radeon_emit(cs, clear_value); /* DATA [31:0] */
1029 radeon_emit(cs, 0);
1030 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1031 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [15:0] */
1032 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
1033 } else {
1034 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
1035 radeon_emit(cs, clear_value); /* DATA [31:0] */
1036 radeon_emit(cs, sync_flag | S_411_SRC_SEL(V_411_DATA)); /* CP_SYNC [31] | SRC_SEL[30:29] */
1037 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1038 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1039 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
1040 }
1041
1042 /* See "copy_buffer" for explanation. */
1043 if (sync_flag && cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1044 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1045 radeon_emit(cs, 0);
1046 }
1047 radv_cmd_buffer_trace_emit(cmd_buffer);
1048 }
1049
1050 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1051 uint64_t remaining_size, unsigned *flags)
1052 {
1053
1054 /* Flush the caches for the first copy only.
1055 * Also wait for the previous CP DMA operations.
1056 */
1057 if (cmd_buffer->state.flush_bits) {
1058 si_emit_cache_flush(cmd_buffer);
1059 *flags |= SI_CP_DMA_RAW_WAIT;
1060 }
1061
1062 /* Do the synchronization after the last dma, so that all data
1063 * is written to memory.
1064 */
1065 if (byte_count == remaining_size)
1066 *flags |= R600_CP_DMA_SYNC;
1067 }
1068
1069 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1070 {
1071 uint64_t va;
1072 uint32_t offset;
1073 unsigned dma_flags = 0;
1074 unsigned buf_size = CP_DMA_ALIGNMENT * 2;
1075 void *ptr;
1076
1077 assert(size < CP_DMA_ALIGNMENT);
1078
1079 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, CP_DMA_ALIGNMENT, &offset, &ptr);
1080
1081 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1082 va += offset;
1083
1084 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1085
1086 si_emit_cp_dma_copy_buffer(cmd_buffer, va, va + CP_DMA_ALIGNMENT, size,
1087 dma_flags);
1088 }
1089
1090 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1091 uint64_t src_va, uint64_t dest_va,
1092 uint64_t size)
1093 {
1094 uint64_t main_src_va, main_dest_va;
1095 uint64_t skipped_size = 0, realign_size = 0;
1096
1097
1098 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1099 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1100 /* If the size is not aligned, we must add a dummy copy at the end
1101 * just to align the internal counter. Otherwise, the DMA engine
1102 * would slow down by an order of magnitude for following copies.
1103 */
1104 if (size % CP_DMA_ALIGNMENT)
1105 realign_size = CP_DMA_ALIGNMENT - (size % CP_DMA_ALIGNMENT);
1106
1107 /* If the copy begins unaligned, we must start copying from the next
1108 * aligned block and the skipped part should be copied after everything
1109 * else has been copied. Only the src alignment matters, not dst.
1110 */
1111 if (src_va % CP_DMA_ALIGNMENT) {
1112 skipped_size = CP_DMA_ALIGNMENT - (src_va % CP_DMA_ALIGNMENT);
1113 /* The main part will be skipped if the size is too small. */
1114 skipped_size = MIN2(skipped_size, size);
1115 size -= skipped_size;
1116 }
1117 }
1118 main_src_va = src_va + skipped_size;
1119 main_dest_va = dest_va + skipped_size;
1120
1121 while (size) {
1122 unsigned dma_flags = 0;
1123 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
1124
1125 si_cp_dma_prepare(cmd_buffer, byte_count,
1126 size + skipped_size + realign_size,
1127 &dma_flags);
1128
1129 si_emit_cp_dma_copy_buffer(cmd_buffer, main_dest_va, main_src_va,
1130 byte_count, dma_flags);
1131
1132 size -= byte_count;
1133 main_src_va += byte_count;
1134 main_dest_va += byte_count;
1135 }
1136
1137 if (skipped_size) {
1138 unsigned dma_flags = 0;
1139
1140 si_cp_dma_prepare(cmd_buffer, skipped_size,
1141 size + skipped_size + realign_size,
1142 &dma_flags);
1143
1144 si_emit_cp_dma_copy_buffer(cmd_buffer, dest_va, src_va,
1145 skipped_size, dma_flags);
1146 }
1147 if (realign_size)
1148 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1149 }
1150
1151 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1152 uint64_t size, unsigned value)
1153 {
1154
1155 if (!size)
1156 return;
1157
1158 assert(va % 4 == 0 && size % 4 == 0);
1159
1160 while (size) {
1161 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
1162 unsigned dma_flags = 0;
1163
1164 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1165
1166 /* Emit the clear packet. */
1167 si_emit_cp_dma_clear_buffer(cmd_buffer, va, byte_count, value,
1168 dma_flags);
1169
1170 size -= byte_count;
1171 va += byte_count;
1172 }
1173 }
1174
1175 /* For MSAA sample positions. */
1176 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1177 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
1178 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1179 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1180 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1181
1182
1183 /* 2xMSAA
1184 * There are two locations (4, 4), (-4, -4). */
1185 const uint32_t eg_sample_locs_2x[4] = {
1186 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1187 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1188 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1189 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1190 };
1191 const unsigned eg_max_dist_2x = 4;
1192 /* 4xMSAA
1193 * There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
1194 const uint32_t eg_sample_locs_4x[4] = {
1195 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1196 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1197 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1198 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1199 };
1200 const unsigned eg_max_dist_4x = 6;
1201
1202 /* Cayman 8xMSAA */
1203 static const uint32_t cm_sample_locs_8x[] = {
1204 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1205 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1206 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1207 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1208 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1209 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1210 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1211 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1212 };
1213 static const unsigned cm_max_dist_8x = 8;
1214 /* Cayman 16xMSAA */
1215 static const uint32_t cm_sample_locs_16x[] = {
1216 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1217 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1218 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1219 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1220 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1221 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1222 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1223 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1224 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1225 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1226 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1227 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1228 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1229 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1230 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1231 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1232 };
1233 static const unsigned cm_max_dist_16x = 8;
1234
1235 unsigned radv_cayman_get_maxdist(int log_samples)
1236 {
1237 unsigned max_dist[] = {
1238 0,
1239 eg_max_dist_2x,
1240 eg_max_dist_4x,
1241 cm_max_dist_8x,
1242 cm_max_dist_16x
1243 };
1244 return max_dist[log_samples];
1245 }
1246
1247 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples)
1248 {
1249 switch (nr_samples) {
1250 default:
1251 case 1:
1252 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
1253 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
1254 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
1255 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
1256 break;
1257 case 2:
1258 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
1259 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
1260 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
1261 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
1262 break;
1263 case 4:
1264 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
1265 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
1266 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
1267 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
1268 break;
1269 case 8:
1270 radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1271 radeon_emit(cs, cm_sample_locs_8x[0]);
1272 radeon_emit(cs, cm_sample_locs_8x[4]);
1273 radeon_emit(cs, 0);
1274 radeon_emit(cs, 0);
1275 radeon_emit(cs, cm_sample_locs_8x[1]);
1276 radeon_emit(cs, cm_sample_locs_8x[5]);
1277 radeon_emit(cs, 0);
1278 radeon_emit(cs, 0);
1279 radeon_emit(cs, cm_sample_locs_8x[2]);
1280 radeon_emit(cs, cm_sample_locs_8x[6]);
1281 radeon_emit(cs, 0);
1282 radeon_emit(cs, 0);
1283 radeon_emit(cs, cm_sample_locs_8x[3]);
1284 radeon_emit(cs, cm_sample_locs_8x[7]);
1285 break;
1286 case 16:
1287 radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
1288 radeon_emit(cs, cm_sample_locs_16x[0]);
1289 radeon_emit(cs, cm_sample_locs_16x[4]);
1290 radeon_emit(cs, cm_sample_locs_16x[8]);
1291 radeon_emit(cs, cm_sample_locs_16x[12]);
1292 radeon_emit(cs, cm_sample_locs_16x[1]);
1293 radeon_emit(cs, cm_sample_locs_16x[5]);
1294 radeon_emit(cs, cm_sample_locs_16x[9]);
1295 radeon_emit(cs, cm_sample_locs_16x[13]);
1296 radeon_emit(cs, cm_sample_locs_16x[2]);
1297 radeon_emit(cs, cm_sample_locs_16x[6]);
1298 radeon_emit(cs, cm_sample_locs_16x[10]);
1299 radeon_emit(cs, cm_sample_locs_16x[14]);
1300 radeon_emit(cs, cm_sample_locs_16x[3]);
1301 radeon_emit(cs, cm_sample_locs_16x[7]);
1302 radeon_emit(cs, cm_sample_locs_16x[11]);
1303 radeon_emit(cs, cm_sample_locs_16x[15]);
1304 break;
1305 }
1306 }
1307
1308 static void radv_cayman_get_sample_position(struct radv_device *device,
1309 unsigned sample_count,
1310 unsigned sample_index, float *out_value)
1311 {
1312 int offset, index;
1313 struct {
1314 int idx:4;
1315 } val;
1316 switch (sample_count) {
1317 case 1:
1318 default:
1319 out_value[0] = out_value[1] = 0.5;
1320 break;
1321 case 2:
1322 offset = 4 * (sample_index * 2);
1323 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1324 out_value[0] = (float)(val.idx + 8) / 16.0f;
1325 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1326 out_value[1] = (float)(val.idx + 8) / 16.0f;
1327 break;
1328 case 4:
1329 offset = 4 * (sample_index * 2);
1330 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1331 out_value[0] = (float)(val.idx + 8) / 16.0f;
1332 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1333 out_value[1] = (float)(val.idx + 8) / 16.0f;
1334 break;
1335 case 8:
1336 offset = 4 * (sample_index % 4 * 2);
1337 index = (sample_index / 4) * 4;
1338 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1339 out_value[0] = (float)(val.idx + 8) / 16.0f;
1340 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1341 out_value[1] = (float)(val.idx + 8) / 16.0f;
1342 break;
1343 case 16:
1344 offset = 4 * (sample_index % 4 * 2);
1345 index = (sample_index / 4) * 4;
1346 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1347 out_value[0] = (float)(val.idx + 8) / 16.0f;
1348 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1349 out_value[1] = (float)(val.idx + 8) / 16.0f;
1350 break;
1351 }
1352 }
1353
1354 void radv_device_init_msaa(struct radv_device *device)
1355 {
1356 int i;
1357 radv_cayman_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1358
1359 for (i = 0; i < 2; i++)
1360 radv_cayman_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1361 for (i = 0; i < 4; i++)
1362 radv_cayman_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1363 for (i = 0; i < 8; i++)
1364 radv_cayman_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1365 for (i = 0; i < 16; i++)
1366 radv_cayman_get_sample_position(device, 16, i, device->sample_locations_16x[i]);
1367 }