2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
6 * Copyright © 2015 Advanced Micro Devices, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 /* command buffer handling for SI */
30 #include "radv_private.h"
34 #include "radv_util.h"
35 #include "main/macros.h"
37 #define SI_GS_PER_ES 128
40 si_write_harvested_raster_configs(struct radv_physical_device
*physical_device
,
41 struct radeon_winsys_cs
*cs
,
42 unsigned raster_config
,
43 unsigned raster_config_1
)
45 unsigned sh_per_se
= MAX2(physical_device
->rad_info
.max_sh_per_se
, 1);
46 unsigned num_se
= MAX2(physical_device
->rad_info
.max_se
, 1);
47 unsigned rb_mask
= physical_device
->rad_info
.enabled_rb_mask
;
48 unsigned num_rb
= MIN2(physical_device
->rad_info
.num_render_backends
, 16);
49 unsigned rb_per_pkr
= MIN2(num_rb
/ num_se
/ sh_per_se
, 2);
50 unsigned rb_per_se
= num_rb
/ num_se
;
54 se_mask
[0] = ((1 << rb_per_se
) - 1) & rb_mask
;
55 se_mask
[1] = (se_mask
[0] << rb_per_se
) & rb_mask
;
56 se_mask
[2] = (se_mask
[1] << rb_per_se
) & rb_mask
;
57 se_mask
[3] = (se_mask
[2] << rb_per_se
) & rb_mask
;
59 assert(num_se
== 1 || num_se
== 2 || num_se
== 4);
60 assert(sh_per_se
== 1 || sh_per_se
== 2);
61 assert(rb_per_pkr
== 1 || rb_per_pkr
== 2);
63 /* XXX: I can't figure out what the *_XSEL and *_YSEL
64 * fields are for, so I'm leaving them as their default
67 if ((num_se
> 2) && ((!se_mask
[0] && !se_mask
[1]) ||
68 (!se_mask
[2] && !se_mask
[3]))) {
69 raster_config_1
&= C_028354_SE_PAIR_MAP
;
71 if (!se_mask
[0] && !se_mask
[1]) {
73 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3
);
76 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0
);
80 for (se
= 0; se
< num_se
; se
++) {
81 unsigned raster_config_se
= raster_config
;
82 unsigned pkr0_mask
= ((1 << rb_per_pkr
) - 1) << (se
* rb_per_se
);
83 unsigned pkr1_mask
= pkr0_mask
<< rb_per_pkr
;
84 int idx
= (se
/ 2) * 2;
86 if ((num_se
> 1) && (!se_mask
[idx
] || !se_mask
[idx
+ 1])) {
87 raster_config_se
&= C_028350_SE_MAP
;
91 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3
);
94 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0
);
100 if (rb_per_se
> 2 && (!pkr0_mask
|| !pkr1_mask
)) {
101 raster_config_se
&= C_028350_PKR_MAP
;
105 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3
);
108 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0
);
112 if (rb_per_se
>= 2) {
113 unsigned rb0_mask
= 1 << (se
* rb_per_se
);
114 unsigned rb1_mask
= rb0_mask
<< 1;
118 if (!rb0_mask
|| !rb1_mask
) {
119 raster_config_se
&= C_028350_RB_MAP_PKR0
;
123 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3
);
126 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0
);
131 rb0_mask
= 1 << (se
* rb_per_se
+ rb_per_pkr
);
132 rb1_mask
= rb0_mask
<< 1;
135 if (!rb0_mask
|| !rb1_mask
) {
136 raster_config_se
&= C_028350_RB_MAP_PKR1
;
140 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3
);
143 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0
);
149 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
150 if (physical_device
->rad_info
.chip_class
< CIK
)
151 radeon_set_config_reg(cs
, GRBM_GFX_INDEX
,
152 SE_INDEX(se
) | SH_BROADCAST_WRITES
|
153 INSTANCE_BROADCAST_WRITES
);
155 radeon_set_uconfig_reg(cs
, R_030800_GRBM_GFX_INDEX
,
156 S_030800_SE_INDEX(se
) | S_030800_SH_BROADCAST_WRITES(1) |
157 S_030800_INSTANCE_BROADCAST_WRITES(1));
158 radeon_set_context_reg(cs
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
);
159 if (physical_device
->rad_info
.chip_class
>= CIK
)
160 radeon_set_context_reg(cs
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
163 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
164 if (physical_device
->rad_info
.chip_class
< CIK
)
165 radeon_set_config_reg(cs
, GRBM_GFX_INDEX
,
166 SE_BROADCAST_WRITES
| SH_BROADCAST_WRITES
|
167 INSTANCE_BROADCAST_WRITES
);
169 radeon_set_uconfig_reg(cs
, R_030800_GRBM_GFX_INDEX
,
170 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
171 S_030800_INSTANCE_BROADCAST_WRITES(1));
175 si_emit_compute(struct radv_physical_device
*physical_device
,
176 struct radeon_winsys_cs
*cs
)
178 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
183 radeon_set_sh_reg_seq(cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
, 3);
185 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
186 radeon_emit(cs
, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
187 radeon_emit(cs
, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
189 if (physical_device
->rad_info
.chip_class
>= CIK
) {
190 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
191 radeon_set_sh_reg_seq(cs
,
192 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2
, 2);
193 radeon_emit(cs
, S_00B864_SH0_CU_EN(0xffff) |
194 S_00B864_SH1_CU_EN(0xffff));
195 radeon_emit(cs
, S_00B868_SH0_CU_EN(0xffff) |
196 S_00B868_SH1_CU_EN(0xffff));
199 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
200 * and is now per pipe, so it should be handled in the
201 * kernel if we want to use something other than the default value,
202 * which is now 0x22f.
204 if (physical_device
->rad_info
.chip_class
<= SI
) {
205 /* XXX: This should be:
206 * (number of compute units) * 4 * (waves per simd) - 1 */
208 radeon_set_sh_reg(cs
, R_00B82C_COMPUTE_MAX_WAVE_ID
,
209 0x190 /* Default value */);
214 si_init_compute(struct radv_cmd_buffer
*cmd_buffer
)
216 struct radv_physical_device
*physical_device
= cmd_buffer
->device
->physical_device
;
217 si_emit_compute(physical_device
, cmd_buffer
->cs
);
221 si_emit_config(struct radv_physical_device
*physical_device
,
222 struct radeon_winsys_cs
*cs
)
224 unsigned num_rb
= MIN2(physical_device
->rad_info
.num_render_backends
, 16);
225 unsigned rb_mask
= physical_device
->rad_info
.enabled_rb_mask
;
226 unsigned raster_config
, raster_config_1
;
229 radeon_emit(cs
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
230 radeon_emit(cs
, CONTEXT_CONTROL_LOAD_ENABLE(1));
231 radeon_emit(cs
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
233 radeon_set_context_reg(cs
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
234 radeon_set_context_reg(cs
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
236 /* FIXME calculate these values somehow ??? */
237 radeon_set_context_reg(cs
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
238 radeon_set_context_reg(cs
, R_028A58_VGT_ES_PER_GS
, 0x40);
239 radeon_set_context_reg(cs
, R_028A5C_VGT_GS_PER_VS
, 0x2);
241 radeon_set_context_reg(cs
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
242 radeon_set_context_reg(cs
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
244 radeon_set_context_reg(cs
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
245 radeon_set_context_reg(cs
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
246 if (physical_device
->rad_info
.chip_class
>= GFX9
)
247 radeon_set_context_reg(cs
, R_028AB4_VGT_REUSE_OFF
, 0);
248 radeon_set_context_reg(cs
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
249 if (physical_device
->rad_info
.chip_class
< CIK
)
250 radeon_set_config_reg(cs
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
251 S_008A14_CLIP_VTX_REORDER_ENA(1));
253 radeon_set_context_reg(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 0x76543210);
254 radeon_set_context_reg(cs
, R_028BD8_PA_SC_CENTROID_PRIORITY_1
, 0xfedcba98);
256 radeon_set_context_reg(cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, 0);
258 for (i
= 0; i
< 16; i
++) {
259 radeon_set_context_reg(cs
, R_0282D0_PA_SC_VPORT_ZMIN_0
+ i
*8, 0);
260 radeon_set_context_reg(cs
, R_0282D4_PA_SC_VPORT_ZMAX_0
+ i
*8, fui(1.0));
263 switch (physical_device
->rad_info
.family
) {
266 raster_config
= 0x2a00126a;
267 raster_config_1
= 0x00000000;
270 raster_config
= 0x0000124a;
271 raster_config_1
= 0x00000000;
274 raster_config
= 0x00000082;
275 raster_config_1
= 0x00000000;
278 raster_config
= 0x00000000;
279 raster_config_1
= 0x00000000;
282 raster_config
= 0x16000012;
283 raster_config_1
= 0x00000000;
286 raster_config
= 0x3a00161a;
287 raster_config_1
= 0x0000002e;
290 if (physical_device
->rad_info
.cik_macrotile_mode_array
[0] == 0x000000e8) {
291 /* old kernels with old tiling config */
292 raster_config
= 0x16000012;
293 raster_config_1
= 0x0000002a;
295 raster_config
= 0x3a00161a;
296 raster_config_1
= 0x0000002e;
300 raster_config
= 0x16000012;
301 raster_config_1
= 0x0000002a;
305 raster_config
= 0x16000012;
306 raster_config_1
= 0x00000000;
309 raster_config
= 0x16000012;
310 raster_config_1
= 0x0000002a;
314 raster_config
= 0x00000000;
316 raster_config
= 0x00000002;
317 raster_config_1
= 0x00000000;
320 raster_config
= 0x00000002;
321 raster_config_1
= 0x00000000;
324 /* KV should be 0x00000002, but that causes problems with radeon */
325 raster_config
= 0x00000000; /* 0x00000002 */
326 raster_config_1
= 0x00000000;
331 raster_config
= 0x00000000;
332 raster_config_1
= 0x00000000;
335 if (physical_device
->rad_info
.chip_class
<= VI
) {
337 "radeonsi: Unknown GPU, using 0 for raster_config\n");
338 raster_config
= 0x00000000;
339 raster_config_1
= 0x00000000;
344 /* Always use the default config when all backends are enabled
345 * (or when we failed to determine the enabled backends).
347 if (physical_device
->rad_info
.chip_class
<= VI
) {
348 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
349 radeon_set_context_reg(cs
, R_028350_PA_SC_RASTER_CONFIG
,
351 if (physical_device
->rad_info
.chip_class
>= CIK
)
352 radeon_set_context_reg(cs
, R_028354_PA_SC_RASTER_CONFIG_1
,
355 si_write_harvested_raster_configs(physical_device
, cs
, raster_config
, raster_config_1
);
359 radeon_set_context_reg(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
360 radeon_set_context_reg(cs
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
361 radeon_set_context_reg(cs
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
362 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
363 radeon_set_context_reg(cs
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
364 radeon_set_context_reg(cs
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
365 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
367 radeon_set_context_reg(cs
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
368 radeon_set_context_reg(cs
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
369 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
370 radeon_set_context_reg(cs
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
371 radeon_set_context_reg(cs
, R_028820_PA_CL_NANINF_CNTL
, 0);
373 radeon_set_context_reg(cs
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
374 radeon_set_context_reg(cs
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
375 radeon_set_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
376 radeon_set_context_reg(cs
, R_02800C_DB_RENDER_OVERRIDE
,
377 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
378 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
));
380 if (physical_device
->rad_info
.chip_class
>= GFX9
) {
381 radeon_set_uconfig_reg(cs
, R_030920_VGT_MAX_VTX_INDX
, ~0);
382 radeon_set_uconfig_reg(cs
, R_030924_VGT_MIN_VTX_INDX
, 0);
383 radeon_set_uconfig_reg(cs
, R_030928_VGT_INDX_OFFSET
, 0);
385 radeon_set_context_reg(cs
, R_028400_VGT_MAX_VTX_INDX
, ~0);
386 radeon_set_context_reg(cs
, R_028404_VGT_MIN_VTX_INDX
, 0);
387 radeon_set_context_reg(cs
, R_028408_VGT_INDX_OFFSET
, 0);
390 if (physical_device
->rad_info
.chip_class
>= CIK
) {
391 if (physical_device
->rad_info
.chip_class
>= GFX9
) {
392 radeon_set_sh_reg(cs
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
, S_00B41C_CU_EN(0xffff));
394 radeon_set_sh_reg(cs
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
, S_00B51C_CU_EN(0xffff));
395 radeon_set_sh_reg(cs
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
, 0);
396 radeon_set_sh_reg(cs
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
, S_00B31C_CU_EN(0xffff));
397 /* If this is 0, Bonaire can hang even if GS isn't being used.
398 * Other chips are unaffected. These are suboptimal values,
399 * but we don't use on-chip GS.
401 radeon_set_context_reg(cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
402 S_028A44_ES_VERTS_PER_SUBGRP(64) |
403 S_028A44_GS_PRIMS_PER_SUBGRP(4));
405 radeon_set_sh_reg(cs
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
, S_00B21C_CU_EN(0xffff));
407 if (physical_device
->rad_info
.num_good_compute_units
/
408 (physical_device
->rad_info
.max_se
* physical_device
->rad_info
.max_sh_per_se
) <= 4) {
409 /* Too few available compute units per SH. Disallowing
410 * VS to run on CU0 could hurt us more than late VS
411 * allocation would help.
413 * LATE_ALLOC_VS = 2 is the highest safe number.
415 radeon_set_sh_reg(cs
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
, S_00B118_CU_EN(0xffff));
416 radeon_set_sh_reg(cs
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(2));
418 /* Set LATE_ALLOC_VS == 31. It should be less than
419 * the number of scratch waves. Limitations:
420 * - VS can't execute on CU0.
421 * - If HS writes outputs to LDS, LS can't execute on CU0.
423 radeon_set_sh_reg(cs
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
, S_00B118_CU_EN(0xfffe));
424 radeon_set_sh_reg(cs
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(31));
427 radeon_set_sh_reg(cs
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
, S_00B01C_CU_EN(0xffff));
430 if (physical_device
->rad_info
.chip_class
>= VI
) {
431 uint32_t vgt_tess_distribution
;
432 radeon_set_context_reg(cs
, R_028424_CB_DCC_CONTROL
,
433 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
434 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
435 if (physical_device
->rad_info
.family
< CHIP_POLARIS10
)
436 radeon_set_context_reg(cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 30);
437 radeon_set_context_reg(cs
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 32);
439 vgt_tess_distribution
= S_028B50_ACCUM_ISOLINE(32) |
440 S_028B50_ACCUM_TRI(11) |
441 S_028B50_ACCUM_QUAD(11) |
442 S_028B50_DONUT_SPLIT(16);
444 if (physical_device
->rad_info
.family
== CHIP_FIJI
||
445 physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
446 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
448 radeon_set_context_reg(cs
, R_028B50_VGT_TESS_DISTRIBUTION
,
449 vgt_tess_distribution
);
451 radeon_set_context_reg(cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
452 radeon_set_context_reg(cs
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
455 if (physical_device
->has_rbplus
)
456 radeon_set_context_reg(cs
, R_028C40_PA_SC_SHADER_CONTROL
, 0);
458 if (physical_device
->rad_info
.chip_class
>= GFX9
) {
459 unsigned num_se
= physical_device
->rad_info
.max_se
;
460 unsigned pc_lines
= 0;
462 switch (physical_device
->rad_info
.family
) {
473 radeon_set_context_reg(cs
, R_028060_DB_DFSM_CONTROL
,
474 S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
));
475 radeon_set_context_reg(cs
, R_028064_DB_RENDER_FILTER
, 0);
476 /* TODO: We can use this to disable RBs for rendering to GART: */
477 radeon_set_context_reg(cs
, R_02835C_PA_SC_TILE_STEERING_OVERRIDE
, 0);
478 radeon_set_context_reg(cs
, R_02883C_PA_SU_OVER_RASTERIZATION_CNTL
, 0);
479 /* TODO: Enable the binner: */
480 radeon_set_context_reg(cs
, R_028C44_PA_SC_BINNER_CNTL_0
,
481 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
482 S_028C44_DISABLE_START_OF_PRIM(1));
483 radeon_set_context_reg(cs
, R_028C48_PA_SC_BINNER_CNTL_1
,
484 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines
/ (4 * num_se
))) |
485 S_028C48_MAX_PRIM_PER_BATCH(1023));
486 radeon_set_context_reg(cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
487 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
488 radeon_set_uconfig_reg(cs
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
490 si_emit_compute(physical_device
, cs
);
493 void si_init_config(struct radv_cmd_buffer
*cmd_buffer
)
495 struct radv_physical_device
*physical_device
= cmd_buffer
->device
->physical_device
;
497 si_emit_config(physical_device
, cmd_buffer
->cs
);
501 cik_create_gfx_config(struct radv_device
*device
)
503 struct radeon_winsys_cs
*cs
= device
->ws
->cs_create(device
->ws
, RING_GFX
);
507 si_emit_config(device
->physical_device
, cs
);
509 while (cs
->cdw
& 7) {
510 if (device
->physical_device
->rad_info
.gfx_ib_pad_with_type2
)
511 radeon_emit(cs
, 0x80000000);
513 radeon_emit(cs
, 0xffff1000);
516 device
->gfx_init
= device
->ws
->buffer_create(device
->ws
,
519 RADEON_FLAG_CPU_ACCESS
);
520 if (!device
->gfx_init
)
523 void *map
= device
->ws
->buffer_map(device
->gfx_init
);
525 device
->ws
->buffer_destroy(device
->gfx_init
);
526 device
->gfx_init
= NULL
;
529 memcpy(map
, cs
->buf
, cs
->cdw
* 4);
531 device
->ws
->buffer_unmap(device
->gfx_init
);
532 device
->gfx_init_size_dw
= cs
->cdw
;
534 device
->ws
->cs_destroy(cs
);
538 get_viewport_xform(const VkViewport
*viewport
,
539 float scale
[3], float translate
[3])
541 float x
= viewport
->x
;
542 float y
= viewport
->y
;
543 float half_width
= 0.5f
* viewport
->width
;
544 float half_height
= 0.5f
* viewport
->height
;
545 double n
= viewport
->minDepth
;
546 double f
= viewport
->maxDepth
;
548 scale
[0] = half_width
;
549 translate
[0] = half_width
+ x
;
550 scale
[1] = half_height
;
551 translate
[1] = half_height
+ y
;
558 si_write_viewport(struct radeon_winsys_cs
*cs
, int first_vp
,
559 int count
, const VkViewport
*viewports
)
564 radeon_set_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE
+
565 first_vp
* 4 * 6, count
* 6);
567 for (i
= 0; i
< count
; i
++) {
568 float scale
[3], translate
[3];
571 get_viewport_xform(&viewports
[i
], scale
, translate
);
572 radeon_emit(cs
, fui(scale
[0]));
573 radeon_emit(cs
, fui(translate
[0]));
574 radeon_emit(cs
, fui(scale
[1]));
575 radeon_emit(cs
, fui(translate
[1]));
576 radeon_emit(cs
, fui(scale
[2]));
577 radeon_emit(cs
, fui(translate
[2]));
580 radeon_set_context_reg_seq(cs
, R_0282D0_PA_SC_VPORT_ZMIN_0
+
581 first_vp
* 4 * 2, count
* 2);
582 for (i
= 0; i
< count
; i
++) {
583 float zmin
= MIN2(viewports
[i
].minDepth
, viewports
[i
].maxDepth
);
584 float zmax
= MAX2(viewports
[i
].minDepth
, viewports
[i
].maxDepth
);
585 radeon_emit(cs
, fui(zmin
));
586 radeon_emit(cs
, fui(zmax
));
590 static VkRect2D
si_scissor_from_viewport(const VkViewport
*viewport
)
592 float scale
[3], translate
[3];
595 get_viewport_xform(viewport
, scale
, translate
);
597 rect
.offset
.x
= translate
[0] - abs(scale
[0]);
598 rect
.offset
.y
= translate
[1] - abs(scale
[1]);
599 rect
.extent
.width
= ceilf(translate
[0] + abs(scale
[0])) - rect
.offset
.x
;
600 rect
.extent
.height
= ceilf(translate
[1] + abs(scale
[1])) - rect
.offset
.y
;
605 static VkRect2D
si_intersect_scissor(const VkRect2D
*a
, const VkRect2D
*b
) {
607 ret
.offset
.x
= MAX2(a
->offset
.x
, b
->offset
.x
);
608 ret
.offset
.y
= MAX2(a
->offset
.y
, b
->offset
.y
);
609 ret
.extent
.width
= MIN2(a
->offset
.x
+ a
->extent
.width
,
610 b
->offset
.x
+ b
->extent
.width
) - ret
.offset
.x
;
611 ret
.extent
.height
= MIN2(a
->offset
.y
+ a
->extent
.height
,
612 b
->offset
.y
+ b
->extent
.height
) - ret
.offset
.y
;
617 si_write_scissors(struct radeon_winsys_cs
*cs
, int first
,
618 int count
, const VkRect2D
*scissors
,
619 const VkViewport
*viewports
, bool can_use_guardband
)
622 float scale
[3], translate
[3], guardband_x
= INFINITY
, guardband_y
= INFINITY
;
623 const float max_range
= 32767.0f
;
626 radeon_set_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
+ first
* 4 * 2, count
* 2);
627 for (i
= 0; i
< count
; i
++) {
628 VkRect2D viewport_scissor
= si_scissor_from_viewport(viewports
+ i
);
629 VkRect2D scissor
= si_intersect_scissor(&scissors
[i
], &viewport_scissor
);
631 get_viewport_xform(viewports
+ i
, scale
, translate
);
632 scale
[0] = abs(scale
[0]);
633 scale
[1] = abs(scale
[1]);
640 guardband_x
= MIN2(guardband_x
, (max_range
- abs(translate
[0])) / scale
[0]);
641 guardband_y
= MIN2(guardband_y
, (max_range
- abs(translate
[1])) / scale
[1]);
643 radeon_emit(cs
, S_028250_TL_X(scissor
.offset
.x
) |
644 S_028250_TL_Y(scissor
.offset
.y
) |
645 S_028250_WINDOW_OFFSET_DISABLE(1));
646 radeon_emit(cs
, S_028254_BR_X(scissor
.offset
.x
+ scissor
.extent
.width
) |
647 S_028254_BR_Y(scissor
.offset
.y
+ scissor
.extent
.height
));
649 if (!can_use_guardband
) {
654 radeon_set_context_reg_seq(cs
, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 4);
655 radeon_emit(cs
, fui(guardband_y
));
656 radeon_emit(cs
, fui(1.0));
657 radeon_emit(cs
, fui(guardband_x
));
658 radeon_emit(cs
, fui(1.0));
661 static inline unsigned
662 radv_prims_for_vertices(struct radv_prim_vertex_count
*info
, unsigned num
)
673 return 1 + ((num
- info
->min
) / info
->incr
);
677 si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
678 bool instanced_draw
, bool indirect_draw
,
679 uint32_t draw_vertex_count
)
681 enum chip_class chip_class
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
;
682 enum radeon_family family
= cmd_buffer
->device
->physical_device
->rad_info
.family
;
683 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
684 unsigned prim
= cmd_buffer
->state
.pipeline
->graphics
.prim
;
685 unsigned primgroup_size
= 128; /* recommended without a GS */
686 unsigned max_primgroup_in_wave
= 2;
687 /* SWITCH_ON_EOP(0) is always preferable. */
688 bool wd_switch_on_eop
= false;
689 bool ia_switch_on_eop
= false;
690 bool ia_switch_on_eoi
= false;
691 bool partial_vs_wave
= false;
692 bool partial_es_wave
= false;
693 uint32_t num_prims
= radv_prims_for_vertices(&cmd_buffer
->state
.pipeline
->graphics
.prim_vertex_count
, draw_vertex_count
);
694 bool multi_instances_smaller_than_primgroup
;
696 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
697 primgroup_size
= cmd_buffer
->state
.pipeline
->graphics
.tess
.num_patches
;
698 else if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
699 primgroup_size
= 64; /* recommended with a GS */
701 multi_instances_smaller_than_primgroup
= indirect_draw
|| (instanced_draw
&&
702 num_prims
< primgroup_size
);
703 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.fs
.prim_id_input
)
704 ia_switch_on_eoi
= true;
706 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
)) {
707 /* SWITCH_ON_EOI must be set if PrimID is used. */
708 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.uses_prim_id
||
709 cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.uses_prim_id
)
710 ia_switch_on_eoi
= true;
712 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
713 if ((family
== CHIP_TAHITI
||
714 family
== CHIP_PITCAIRN
||
715 family
== CHIP_BONAIRE
) &&
716 radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
717 partial_vs_wave
= true;
719 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
720 if (cmd_buffer
->device
->has_distributed_tess
) {
721 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
)) {
722 if (chip_class
<= VI
)
723 partial_es_wave
= true;
725 if (family
== CHIP_TONGA
||
726 family
== CHIP_FIJI
||
727 family
== CHIP_POLARIS10
||
728 family
== CHIP_POLARIS11
||
729 family
== CHIP_POLARIS12
)
730 partial_vs_wave
= true;
732 partial_vs_wave
= true;
736 /* TODO linestipple */
738 if (chip_class
>= CIK
) {
739 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
740 * 4 shader engines. Set 1 to pass the assertion below.
741 * The other cases are hardware requirements. */
742 if (info
->max_se
< 4 ||
743 prim
== V_008958_DI_PT_POLYGON
||
744 prim
== V_008958_DI_PT_LINELOOP
||
745 prim
== V_008958_DI_PT_TRIFAN
||
746 prim
== V_008958_DI_PT_TRISTRIP_ADJ
||
747 (cmd_buffer
->state
.pipeline
->graphics
.prim_restart_enable
&&
748 (family
< CHIP_POLARIS10
||
749 (prim
!= V_008958_DI_PT_POINTLIST
&&
750 prim
!= V_008958_DI_PT_LINESTRIP
&&
751 prim
!= V_008958_DI_PT_TRISTRIP
))))
752 wd_switch_on_eop
= true;
754 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
755 * We don't know that for indirect drawing, so treat it as
756 * always problematic. */
757 if (family
== CHIP_HAWAII
&&
758 (instanced_draw
|| indirect_draw
))
759 wd_switch_on_eop
= true;
761 /* Performance recommendation for 4 SE Gfx7-8 parts if
762 * instances are smaller than a primgroup.
763 * Assume indirect draws always use small instances.
764 * This is needed for good VS wave utilization.
766 if (chip_class
<= VI
&&
768 multi_instances_smaller_than_primgroup
)
769 wd_switch_on_eop
= true;
771 /* Required on CIK and later. */
772 if (info
->max_se
> 2 && !wd_switch_on_eop
)
773 ia_switch_on_eoi
= true;
775 /* Required by Hawaii and, for some special cases, by VI. */
776 if (ia_switch_on_eoi
&&
777 (family
== CHIP_HAWAII
||
779 (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
) || max_primgroup_in_wave
!= 2))))
780 partial_vs_wave
= true;
782 /* Instancing bug on Bonaire. */
783 if (family
== CHIP_BONAIRE
&& ia_switch_on_eoi
&&
784 (instanced_draw
|| indirect_draw
))
785 partial_vs_wave
= true;
787 /* If the WD switch is false, the IA switch must be false too. */
788 assert(wd_switch_on_eop
|| !ia_switch_on_eop
);
790 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
791 if (chip_class
<= VI
&& ia_switch_on_eoi
)
792 partial_es_wave
= true;
794 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
)) {
796 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
) &&
797 cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.uses_prim_id
)
798 ia_switch_on_eoi
= true;
800 /* GS requirement. */
801 if (SI_GS_PER_ES
/ primgroup_size
>= cmd_buffer
->device
->gs_table_depth
- 3)
802 partial_es_wave
= true;
804 /* Hw bug with single-primitive instances and SWITCH_ON_EOI
805 * on multi-SE chips. */
806 if (info
->max_se
>= 2 && ia_switch_on_eoi
&&
807 ((instanced_draw
|| indirect_draw
) &&
809 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_FLUSH
;
812 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
813 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi
) |
814 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
815 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave
) |
816 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1) |
817 S_028AA8_WD_SWITCH_ON_EOP(chip_class
>= CIK
? wd_switch_on_eop
: 0) |
818 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
819 S_028AA8_MAX_PRIMGRP_IN_WAVE(chip_class
== VI
?
820 max_primgroup_in_wave
: 0) |
821 S_030960_EN_INST_OPT_BASIC(chip_class
>= GFX9
) |
822 S_030960_EN_INST_OPT_ADV(chip_class
>= GFX9
);
826 void si_cs_emit_write_event_eop(struct radeon_winsys_cs
*cs
,
828 enum chip_class chip_class
,
830 unsigned event
, unsigned event_flags
,
836 unsigned op
= EVENT_TYPE(event
) |
839 unsigned is_gfx8_mec
= is_mec
&& chip_class
< GFX9
;
841 if (chip_class
>= GFX9
|| is_gfx8_mec
) {
842 radeon_emit(cs
, PKT3(PKT3_RELEASE_MEM
, is_gfx8_mec
? 5 : 6, predicated
));
844 radeon_emit(cs
, EOP_DATA_SEL(data_sel
));
845 radeon_emit(cs
, va
); /* address lo */
846 radeon_emit(cs
, va
>> 32); /* address hi */
847 radeon_emit(cs
, new_fence
); /* immediate data lo */
848 radeon_emit(cs
, 0); /* immediate data hi */
850 radeon_emit(cs
, 0); /* unused */
852 if (chip_class
== CIK
||
854 /* Two EOP events are required to make all engines go idle
855 * (and optional cache flushes executed) before the timestamp
858 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, predicated
));
861 radeon_emit(cs
, ((va
>> 32) & 0xffff) | EOP_DATA_SEL(data_sel
));
862 radeon_emit(cs
, old_fence
); /* immediate data */
863 radeon_emit(cs
, 0); /* unused */
866 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, predicated
));
869 radeon_emit(cs
, ((va
>> 32) & 0xffff) | EOP_DATA_SEL(data_sel
));
870 radeon_emit(cs
, new_fence
); /* immediate data */
871 radeon_emit(cs
, 0); /* unused */
876 si_emit_wait_fence(struct radeon_winsys_cs
*cs
,
878 uint64_t va
, uint32_t ref
,
881 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, predicated
));
882 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
| WAIT_REG_MEM_MEM_SPACE(1));
884 radeon_emit(cs
, va
>> 32);
885 radeon_emit(cs
, ref
); /* reference value */
886 radeon_emit(cs
, mask
); /* mask */
887 radeon_emit(cs
, 4); /* poll interval */
891 si_emit_acquire_mem(struct radeon_winsys_cs
*cs
,
895 unsigned cp_coher_cntl
)
897 if (is_mec
|| is_gfx9
) {
898 uint32_t hi_val
= is_gfx9
? 0xffffff : 0xff;
899 radeon_emit(cs
, PKT3(PKT3_ACQUIRE_MEM
, 5, predicated
) |
900 PKT3_SHADER_TYPE_S(is_mec
));
901 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
902 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
903 radeon_emit(cs
, hi_val
); /* CP_COHER_SIZE_HI */
904 radeon_emit(cs
, 0); /* CP_COHER_BASE */
905 radeon_emit(cs
, 0); /* CP_COHER_BASE_HI */
906 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
908 /* ACQUIRE_MEM is only required on a compute ring. */
909 radeon_emit(cs
, PKT3(PKT3_SURFACE_SYNC
, 3, predicated
));
910 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
911 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
912 radeon_emit(cs
, 0); /* CP_COHER_BASE */
913 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
918 si_cs_emit_cache_flush(struct radeon_winsys_cs
*cs
,
920 enum chip_class chip_class
,
924 enum radv_cmd_flush_bits flush_bits
)
926 unsigned cp_coher_cntl
= 0;
927 uint32_t flush_cb_db
= flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
928 RADV_CMD_FLAG_FLUSH_AND_INV_DB
);
930 if (flush_bits
& RADV_CMD_FLAG_INV_ICACHE
)
931 cp_coher_cntl
|= S_0085F0_SH_ICACHE_ACTION_ENA(1);
932 if (flush_bits
& RADV_CMD_FLAG_INV_SMEM_L1
)
933 cp_coher_cntl
|= S_0085F0_SH_KCACHE_ACTION_ENA(1);
935 if (chip_class
<= VI
) {
936 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_CB
) {
937 cp_coher_cntl
|= S_0085F0_CB_ACTION_ENA(1) |
938 S_0085F0_CB0_DEST_BASE_ENA(1) |
939 S_0085F0_CB1_DEST_BASE_ENA(1) |
940 S_0085F0_CB2_DEST_BASE_ENA(1) |
941 S_0085F0_CB3_DEST_BASE_ENA(1) |
942 S_0085F0_CB4_DEST_BASE_ENA(1) |
943 S_0085F0_CB5_DEST_BASE_ENA(1) |
944 S_0085F0_CB6_DEST_BASE_ENA(1) |
945 S_0085F0_CB7_DEST_BASE_ENA(1);
947 /* Necessary for DCC */
948 if (chip_class
>= VI
) {
949 si_cs_emit_write_event_eop(cs
,
953 V_028A90_FLUSH_AND_INV_CB_DATA_TS
,
957 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_DB
) {
958 cp_coher_cntl
|= S_0085F0_DB_ACTION_ENA(1) |
959 S_0085F0_DB_DEST_BASE_ENA(1);
963 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
) {
964 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, predicated
));
965 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META
) | EVENT_INDEX(0));
968 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
) {
969 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, predicated
));
970 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META
) | EVENT_INDEX(0));
974 if (flush_bits
& RADV_CMD_FLAG_PS_PARTIAL_FLUSH
) {
975 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, predicated
));
976 radeon_emit(cs
, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
977 } else if (flush_bits
& RADV_CMD_FLAG_VS_PARTIAL_FLUSH
) {
978 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, predicated
));
979 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
983 if (flush_bits
& RADV_CMD_FLAG_CS_PARTIAL_FLUSH
) {
984 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, predicated
));
985 radeon_emit(cs
, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
988 if (chip_class
>= GFX9
&& flush_cb_db
) {
989 unsigned cb_db_event
, tc_flags
;
991 /* Set the CB/DB flush event. */
992 switch (flush_cb_db
) {
993 case RADV_CMD_FLAG_FLUSH_AND_INV_CB
:
994 cb_db_event
= V_028A90_FLUSH_AND_INV_CB_DATA_TS
;
996 case RADV_CMD_FLAG_FLUSH_AND_INV_DB
:
997 cb_db_event
= V_028A90_FLUSH_AND_INV_DB_DATA_TS
;
1001 cb_db_event
= V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT
;
1004 /* TC | TC_WB = invalidate L2 data
1005 * TC_MD | TC_WB = invalidate L2 metadata
1006 * TC | TC_WB | TC_MD = invalidate L2 data & metadata
1008 * The metadata cache must always be invalidated for coherency
1009 * between CB/DB and shaders. (metadata = HTILE, CMASK, DCC)
1011 * TC must be invalidated on GFX9 only if the CB/DB surface is
1012 * not pipe-aligned. If the surface is RB-aligned, it might not
1013 * strictly be pipe-aligned since RB alignment takes precendence.
1015 tc_flags
= EVENT_TC_WB_ACTION_ENA
|
1016 EVENT_TC_MD_ACTION_ENA
;
1018 /* Ideally flush TC together with CB/DB. */
1019 if (flush_bits
& RADV_CMD_FLAG_INV_GLOBAL_L2
) {
1020 tc_flags
|= EVENT_TC_ACTION_ENA
|
1021 EVENT_TCL1_ACTION_ENA
;
1023 /* Clear the flags. */
1024 flush_bits
&= ~(RADV_CMD_FLAG_INV_GLOBAL_L2
|
1025 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
|
1026 RADV_CMD_FLAG_INV_VMEM_L1
);
1029 uint32_t old_fence
= (*flush_cnt
)++;
1031 si_cs_emit_write_event_eop(cs
, predicated
, chip_class
, false, cb_db_event
, tc_flags
, 1,
1032 flush_va
, old_fence
, *flush_cnt
);
1033 si_emit_wait_fence(cs
, predicated
, flush_va
, *flush_cnt
, 0xffffffff);
1036 /* VGT state sync */
1037 if (flush_bits
& RADV_CMD_FLAG_VGT_FLUSH
) {
1038 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, predicated
));
1039 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
1042 /* Make sure ME is idle (it executes most packets) before continuing.
1043 * This prevents read-after-write hazards between PFP and ME.
1045 if ((cp_coher_cntl
||
1046 (flush_bits
& (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
1047 RADV_CMD_FLAG_INV_VMEM_L1
|
1048 RADV_CMD_FLAG_INV_GLOBAL_L2
|
1049 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
))) &&
1051 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, predicated
));
1055 if ((flush_bits
& RADV_CMD_FLAG_INV_GLOBAL_L2
) ||
1056 (chip_class
<= CIK
&& (flush_bits
& RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
))) {
1057 si_emit_acquire_mem(cs
, is_mec
, predicated
, chip_class
>= GFX9
,
1059 S_0085F0_TC_ACTION_ENA(1) |
1060 S_0085F0_TCL1_ACTION_ENA(1) |
1061 S_0301F0_TC_WB_ACTION_ENA(chip_class
>= VI
));
1064 if(flush_bits
& RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
) {
1066 * NC = apply to non-coherent MTYPEs
1067 * (i.e. MTYPE <= 1, which is what we use everywhere)
1069 * WB doesn't work without NC.
1071 si_emit_acquire_mem(cs
, is_mec
, predicated
,
1074 S_0301F0_TC_WB_ACTION_ENA(1) |
1075 S_0301F0_TC_NC_ACTION_ENA(1));
1078 if (flush_bits
& RADV_CMD_FLAG_INV_VMEM_L1
) {
1079 si_emit_acquire_mem(cs
, is_mec
,
1080 predicated
, chip_class
>= GFX9
,
1082 S_0085F0_TCL1_ACTION_ENA(1));
1087 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1088 * Therefore, it should be last. Done in PFP.
1091 si_emit_acquire_mem(cs
, is_mec
, predicated
, chip_class
>= GFX9
, cp_coher_cntl
);
1095 si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
)
1097 bool is_compute
= cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
;
1100 cmd_buffer
->state
.flush_bits
&= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1101 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
1102 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1103 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
|
1104 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
1105 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
|
1106 RADV_CMD_FLAG_VGT_FLUSH
);
1108 if (!cmd_buffer
->state
.flush_bits
)
1111 enum chip_class chip_class
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
;
1112 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 128);
1114 uint32_t *ptr
= NULL
;
1116 if (chip_class
== GFX9
) {
1117 va
= cmd_buffer
->device
->ws
->buffer_get_va(cmd_buffer
->gfx9_fence_bo
) + cmd_buffer
->gfx9_fence_offset
;
1118 ptr
= &cmd_buffer
->gfx9_fence_idx
;
1120 si_cs_emit_cache_flush(cmd_buffer
->cs
,
1121 cmd_buffer
->state
.predicating
,
1122 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
1124 radv_cmd_buffer_uses_mec(cmd_buffer
),
1125 cmd_buffer
->state
.flush_bits
);
1128 radv_cmd_buffer_trace_emit(cmd_buffer
);
1129 cmd_buffer
->state
.flush_bits
= 0;
1132 /* sets the CP predication state using a boolean stored at va */
1134 si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
)
1136 uint32_t op
= PRED_OP(PREDICATION_OP_BOOL64
) | PREDICATION_DRAW_VISIBLE
;
1138 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1139 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_SET_PREDICATION
, 2, 0));
1140 radeon_emit(cmd_buffer
->cs
, op
);
1141 radeon_emit(cmd_buffer
->cs
, va
);
1142 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1144 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_SET_PREDICATION
, 1, 0));
1145 radeon_emit(cmd_buffer
->cs
, va
);
1146 radeon_emit(cmd_buffer
->cs
, op
| ((va
>> 32) & 0xFF));
1150 /* Set this if you want the 3D engine to wait until CP DMA is done.
1151 * It should be set on the last CP DMA packet. */
1152 #define CP_DMA_SYNC (1 << 0)
1154 /* Set this if the source data was used as a destination in a previous CP DMA
1155 * packet. It's for preventing a read-after-write (RAW) hazard between two
1156 * CP DMA packets. */
1157 #define CP_DMA_RAW_WAIT (1 << 1)
1158 #define CP_DMA_USE_L2 (1 << 2)
1159 #define CP_DMA_CLEAR (1 << 3)
1161 /* Alignment for optimal performance. */
1162 #define SI_CPDMA_ALIGNMENT 32
1164 /* The max number of bytes that can be copied per packet. */
1165 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer
*cmd_buffer
)
1167 unsigned max
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
?
1168 S_414_BYTE_COUNT_GFX9(~0u) :
1169 S_414_BYTE_COUNT_GFX6(~0u);
1171 /* make it aligned for optimal performance */
1172 return max
& ~(SI_CPDMA_ALIGNMENT
- 1);
1175 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1176 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1179 static void si_emit_cp_dma(struct radv_cmd_buffer
*cmd_buffer
,
1180 uint64_t dst_va
, uint64_t src_va
,
1181 unsigned size
, unsigned flags
)
1183 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
1184 uint32_t header
= 0, command
= 0;
1187 assert(size
<= cp_dma_max_byte_count(cmd_buffer
));
1189 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 9);
1190 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1191 command
|= S_414_BYTE_COUNT_GFX9(size
);
1193 command
|= S_414_BYTE_COUNT_GFX6(size
);
1196 if (flags
& CP_DMA_SYNC
)
1197 header
|= S_411_CP_SYNC(1);
1199 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1200 command
|= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1202 command
|= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1205 if (flags
& CP_DMA_RAW_WAIT
)
1206 command
|= S_414_RAW_WAIT(1);
1208 /* Src and dst flags. */
1209 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1210 !(flags
& CP_DMA_CLEAR
) &&
1212 header
|= S_411_DSL_SEL(V_411_NOWHERE
); /* prefetch only */
1213 else if (flags
& CP_DMA_USE_L2
)
1214 header
|= S_411_DSL_SEL(V_411_DST_ADDR_TC_L2
);
1216 if (flags
& CP_DMA_CLEAR
)
1217 header
|= S_411_SRC_SEL(V_411_DATA
);
1218 else if (flags
& CP_DMA_USE_L2
)
1219 header
|= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2
);
1221 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1222 radeon_emit(cs
, PKT3(PKT3_DMA_DATA
, 5, cmd_buffer
->state
.predicating
));
1223 radeon_emit(cs
, header
);
1224 radeon_emit(cs
, src_va
); /* SRC_ADDR_LO [31:0] */
1225 radeon_emit(cs
, src_va
>> 32); /* SRC_ADDR_HI [31:0] */
1226 radeon_emit(cs
, dst_va
); /* DST_ADDR_LO [31:0] */
1227 radeon_emit(cs
, dst_va
>> 32); /* DST_ADDR_HI [31:0] */
1228 radeon_emit(cs
, command
);
1230 assert(!(flags
& CP_DMA_USE_L2
));
1231 header
|= S_411_SRC_ADDR_HI(src_va
>> 32);
1232 radeon_emit(cs
, PKT3(PKT3_CP_DMA
, 4, cmd_buffer
->state
.predicating
));
1233 radeon_emit(cs
, src_va
); /* SRC_ADDR_LO [31:0] */
1234 radeon_emit(cs
, header
); /* SRC_ADDR_HI [15:0] + flags. */
1235 radeon_emit(cs
, dst_va
); /* DST_ADDR_LO [31:0] */
1236 radeon_emit(cs
, (dst_va
>> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1237 radeon_emit(cs
, command
);
1240 /* CP DMA is executed in ME, but index buffers are read by PFP.
1241 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1242 * indices. If we wanted to execute CP DMA in PFP, this packet
1243 * should precede it.
1245 if ((flags
& CP_DMA_SYNC
) && cmd_buffer
->queue_family_index
== RADV_QUEUE_GENERAL
) {
1246 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1250 radv_cmd_buffer_trace_emit(cmd_buffer
);
1253 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1256 uint64_t aligned_va
= va
& ~(SI_CPDMA_ALIGNMENT
- 1);
1257 uint64_t aligned_size
= ((va
+ size
+ SI_CPDMA_ALIGNMENT
-1) & ~(SI_CPDMA_ALIGNMENT
- 1)) - aligned_va
;
1259 si_emit_cp_dma(cmd_buffer
, aligned_va
, aligned_va
,
1260 aligned_size
, CP_DMA_USE_L2
);
1263 static void si_cp_dma_prepare(struct radv_cmd_buffer
*cmd_buffer
, uint64_t byte_count
,
1264 uint64_t remaining_size
, unsigned *flags
)
1267 /* Flush the caches for the first copy only.
1268 * Also wait for the previous CP DMA operations.
1270 if (cmd_buffer
->state
.flush_bits
) {
1271 si_emit_cache_flush(cmd_buffer
);
1272 *flags
|= CP_DMA_RAW_WAIT
;
1275 /* Do the synchronization after the last dma, so that all data
1276 * is written to memory.
1278 if (byte_count
== remaining_size
)
1279 *flags
|= CP_DMA_SYNC
;
1282 static void si_cp_dma_realign_engine(struct radv_cmd_buffer
*cmd_buffer
, unsigned size
)
1286 unsigned dma_flags
= 0;
1287 unsigned buf_size
= SI_CPDMA_ALIGNMENT
* 2;
1290 assert(size
< SI_CPDMA_ALIGNMENT
);
1292 radv_cmd_buffer_upload_alloc(cmd_buffer
, buf_size
, SI_CPDMA_ALIGNMENT
, &offset
, &ptr
);
1294 va
= cmd_buffer
->device
->ws
->buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1297 si_cp_dma_prepare(cmd_buffer
, size
, size
, &dma_flags
);
1299 si_emit_cp_dma(cmd_buffer
, va
, va
+ SI_CPDMA_ALIGNMENT
, size
,
1303 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1304 uint64_t src_va
, uint64_t dest_va
,
1307 uint64_t main_src_va
, main_dest_va
;
1308 uint64_t skipped_size
= 0, realign_size
= 0;
1311 if (cmd_buffer
->device
->physical_device
->rad_info
.family
<= CHIP_CARRIZO
||
1312 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_STONEY
) {
1313 /* If the size is not aligned, we must add a dummy copy at the end
1314 * just to align the internal counter. Otherwise, the DMA engine
1315 * would slow down by an order of magnitude for following copies.
1317 if (size
% SI_CPDMA_ALIGNMENT
)
1318 realign_size
= SI_CPDMA_ALIGNMENT
- (size
% SI_CPDMA_ALIGNMENT
);
1320 /* If the copy begins unaligned, we must start copying from the next
1321 * aligned block and the skipped part should be copied after everything
1322 * else has been copied. Only the src alignment matters, not dst.
1324 if (src_va
% SI_CPDMA_ALIGNMENT
) {
1325 skipped_size
= SI_CPDMA_ALIGNMENT
- (src_va
% SI_CPDMA_ALIGNMENT
);
1326 /* The main part will be skipped if the size is too small. */
1327 skipped_size
= MIN2(skipped_size
, size
);
1328 size
-= skipped_size
;
1331 main_src_va
= src_va
+ skipped_size
;
1332 main_dest_va
= dest_va
+ skipped_size
;
1335 unsigned dma_flags
= 0;
1336 unsigned byte_count
= MIN2(size
, cp_dma_max_byte_count(cmd_buffer
));
1338 si_cp_dma_prepare(cmd_buffer
, byte_count
,
1339 size
+ skipped_size
+ realign_size
,
1342 si_emit_cp_dma(cmd_buffer
, main_dest_va
, main_src_va
,
1343 byte_count
, dma_flags
);
1346 main_src_va
+= byte_count
;
1347 main_dest_va
+= byte_count
;
1351 unsigned dma_flags
= 0;
1353 si_cp_dma_prepare(cmd_buffer
, skipped_size
,
1354 size
+ skipped_size
+ realign_size
,
1357 si_emit_cp_dma(cmd_buffer
, dest_va
, src_va
,
1358 skipped_size
, dma_flags
);
1361 si_cp_dma_realign_engine(cmd_buffer
, realign_size
);
1364 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1365 uint64_t size
, unsigned value
)
1371 assert(va
% 4 == 0 && size
% 4 == 0);
1374 unsigned byte_count
= MIN2(size
, cp_dma_max_byte_count(cmd_buffer
));
1375 unsigned dma_flags
= CP_DMA_CLEAR
;
1377 si_cp_dma_prepare(cmd_buffer
, byte_count
, size
, &dma_flags
);
1379 /* Emit the clear packet. */
1380 si_emit_cp_dma(cmd_buffer
, va
, value
, byte_count
,
1388 /* For MSAA sample positions. */
1389 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1390 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
1391 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1392 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1393 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1397 * There are two locations (4, 4), (-4, -4). */
1398 const uint32_t eg_sample_locs_2x
[4] = {
1399 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1400 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1401 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1402 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1404 const unsigned eg_max_dist_2x
= 4;
1406 * There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
1407 const uint32_t eg_sample_locs_4x
[4] = {
1408 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1409 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1410 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1411 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1413 const unsigned eg_max_dist_4x
= 6;
1416 static const uint32_t cm_sample_locs_8x
[] = {
1417 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1418 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1419 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1420 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1421 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1422 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1423 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1424 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1426 static const unsigned cm_max_dist_8x
= 8;
1427 /* Cayman 16xMSAA */
1428 static const uint32_t cm_sample_locs_16x
[] = {
1429 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1430 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1431 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1432 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1433 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1434 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1435 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1436 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1437 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1438 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1439 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1440 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1441 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1442 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1443 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1444 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1446 static const unsigned cm_max_dist_16x
= 8;
1448 unsigned radv_cayman_get_maxdist(int log_samples
)
1450 unsigned max_dist
[] = {
1457 return max_dist
[log_samples
];
1460 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
)
1462 switch (nr_samples
) {
1465 radeon_set_context_reg(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 0);
1466 radeon_set_context_reg(cs
, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, 0);
1467 radeon_set_context_reg(cs
, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, 0);
1468 radeon_set_context_reg(cs
, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, 0);
1471 radeon_set_context_reg(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, eg_sample_locs_2x
[0]);
1472 radeon_set_context_reg(cs
, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, eg_sample_locs_2x
[1]);
1473 radeon_set_context_reg(cs
, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, eg_sample_locs_2x
[2]);
1474 radeon_set_context_reg(cs
, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, eg_sample_locs_2x
[3]);
1477 radeon_set_context_reg(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, eg_sample_locs_4x
[0]);
1478 radeon_set_context_reg(cs
, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, eg_sample_locs_4x
[1]);
1479 radeon_set_context_reg(cs
, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, eg_sample_locs_4x
[2]);
1480 radeon_set_context_reg(cs
, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, eg_sample_locs_4x
[3]);
1483 radeon_set_context_reg_seq(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 14);
1484 radeon_emit(cs
, cm_sample_locs_8x
[0]);
1485 radeon_emit(cs
, cm_sample_locs_8x
[4]);
1488 radeon_emit(cs
, cm_sample_locs_8x
[1]);
1489 radeon_emit(cs
, cm_sample_locs_8x
[5]);
1492 radeon_emit(cs
, cm_sample_locs_8x
[2]);
1493 radeon_emit(cs
, cm_sample_locs_8x
[6]);
1496 radeon_emit(cs
, cm_sample_locs_8x
[3]);
1497 radeon_emit(cs
, cm_sample_locs_8x
[7]);
1500 radeon_set_context_reg_seq(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 16);
1501 radeon_emit(cs
, cm_sample_locs_16x
[0]);
1502 radeon_emit(cs
, cm_sample_locs_16x
[4]);
1503 radeon_emit(cs
, cm_sample_locs_16x
[8]);
1504 radeon_emit(cs
, cm_sample_locs_16x
[12]);
1505 radeon_emit(cs
, cm_sample_locs_16x
[1]);
1506 radeon_emit(cs
, cm_sample_locs_16x
[5]);
1507 radeon_emit(cs
, cm_sample_locs_16x
[9]);
1508 radeon_emit(cs
, cm_sample_locs_16x
[13]);
1509 radeon_emit(cs
, cm_sample_locs_16x
[2]);
1510 radeon_emit(cs
, cm_sample_locs_16x
[6]);
1511 radeon_emit(cs
, cm_sample_locs_16x
[10]);
1512 radeon_emit(cs
, cm_sample_locs_16x
[14]);
1513 radeon_emit(cs
, cm_sample_locs_16x
[3]);
1514 radeon_emit(cs
, cm_sample_locs_16x
[7]);
1515 radeon_emit(cs
, cm_sample_locs_16x
[11]);
1516 radeon_emit(cs
, cm_sample_locs_16x
[15]);
1521 static void radv_cayman_get_sample_position(struct radv_device
*device
,
1522 unsigned sample_count
,
1523 unsigned sample_index
, float *out_value
)
1529 switch (sample_count
) {
1532 out_value
[0] = out_value
[1] = 0.5;
1535 offset
= 4 * (sample_index
* 2);
1536 val
.idx
= (eg_sample_locs_2x
[0] >> offset
) & 0xf;
1537 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1538 val
.idx
= (eg_sample_locs_2x
[0] >> (offset
+ 4)) & 0xf;
1539 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1542 offset
= 4 * (sample_index
* 2);
1543 val
.idx
= (eg_sample_locs_4x
[0] >> offset
) & 0xf;
1544 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1545 val
.idx
= (eg_sample_locs_4x
[0] >> (offset
+ 4)) & 0xf;
1546 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1549 offset
= 4 * (sample_index
% 4 * 2);
1550 index
= (sample_index
/ 4) * 4;
1551 val
.idx
= (cm_sample_locs_8x
[index
] >> offset
) & 0xf;
1552 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1553 val
.idx
= (cm_sample_locs_8x
[index
] >> (offset
+ 4)) & 0xf;
1554 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1557 offset
= 4 * (sample_index
% 4 * 2);
1558 index
= (sample_index
/ 4) * 4;
1559 val
.idx
= (cm_sample_locs_16x
[index
] >> offset
) & 0xf;
1560 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1561 val
.idx
= (cm_sample_locs_16x
[index
] >> (offset
+ 4)) & 0xf;
1562 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1567 void radv_device_init_msaa(struct radv_device
*device
)
1570 radv_cayman_get_sample_position(device
, 1, 0, device
->sample_locations_1x
[0]);
1572 for (i
= 0; i
< 2; i
++)
1573 radv_cayman_get_sample_position(device
, 2, i
, device
->sample_locations_2x
[i
]);
1574 for (i
= 0; i
< 4; i
++)
1575 radv_cayman_get_sample_position(device
, 4, i
, device
->sample_locations_4x
[i
]);
1576 for (i
= 0; i
< 8; i
++)
1577 radv_cayman_get_sample_position(device
, 8, i
, device
->sample_locations_8x
[i
]);
1578 for (i
= 0; i
< 16; i
++)
1579 radv_cayman_get_sample_position(device
, 16, i
, device
->sample_locations_16x
[i
]);