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radv: add rb+ support for GFX9
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for SI */
29
30 #include "radv_private.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "radv_util.h"
35 #include "main/macros.h"
36
37 #define SI_GS_PER_ES 128
38
39 static void
40 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
41 struct radeon_winsys_cs *cs,
42 unsigned raster_config,
43 unsigned raster_config_1)
44 {
45 unsigned sh_per_se = MAX2(physical_device->rad_info.max_sh_per_se, 1);
46 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
47 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
48 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
49 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
50 unsigned rb_per_se = num_rb / num_se;
51 unsigned se_mask[4];
52 unsigned se;
53
54 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
55 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
56 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
57 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
58
59 assert(num_se == 1 || num_se == 2 || num_se == 4);
60 assert(sh_per_se == 1 || sh_per_se == 2);
61 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
62
63 /* XXX: I can't figure out what the *_XSEL and *_YSEL
64 * fields are for, so I'm leaving them as their default
65 * values. */
66
67 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
68 (!se_mask[2] && !se_mask[3]))) {
69 raster_config_1 &= C_028354_SE_PAIR_MAP;
70
71 if (!se_mask[0] && !se_mask[1]) {
72 raster_config_1 |=
73 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
74 } else {
75 raster_config_1 |=
76 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
77 }
78 }
79
80 for (se = 0; se < num_se; se++) {
81 unsigned raster_config_se = raster_config;
82 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
83 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
84 int idx = (se / 2) * 2;
85
86 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
87 raster_config_se &= C_028350_SE_MAP;
88
89 if (!se_mask[idx]) {
90 raster_config_se |=
91 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
92 } else {
93 raster_config_se |=
94 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
95 }
96 }
97
98 pkr0_mask &= rb_mask;
99 pkr1_mask &= rb_mask;
100 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
101 raster_config_se &= C_028350_PKR_MAP;
102
103 if (!pkr0_mask) {
104 raster_config_se |=
105 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
106 } else {
107 raster_config_se |=
108 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
109 }
110 }
111
112 if (rb_per_se >= 2) {
113 unsigned rb0_mask = 1 << (se * rb_per_se);
114 unsigned rb1_mask = rb0_mask << 1;
115
116 rb0_mask &= rb_mask;
117 rb1_mask &= rb_mask;
118 if (!rb0_mask || !rb1_mask) {
119 raster_config_se &= C_028350_RB_MAP_PKR0;
120
121 if (!rb0_mask) {
122 raster_config_se |=
123 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
124 } else {
125 raster_config_se |=
126 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
127 }
128 }
129
130 if (rb_per_se > 2) {
131 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
132 rb1_mask = rb0_mask << 1;
133 rb0_mask &= rb_mask;
134 rb1_mask &= rb_mask;
135 if (!rb0_mask || !rb1_mask) {
136 raster_config_se &= C_028350_RB_MAP_PKR1;
137
138 if (!rb0_mask) {
139 raster_config_se |=
140 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
141 } else {
142 raster_config_se |=
143 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
144 }
145 }
146 }
147 }
148
149 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
150 if (physical_device->rad_info.chip_class < CIK)
151 radeon_set_config_reg(cs, GRBM_GFX_INDEX,
152 SE_INDEX(se) | SH_BROADCAST_WRITES |
153 INSTANCE_BROADCAST_WRITES);
154 else
155 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
156 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
157 S_030800_INSTANCE_BROADCAST_WRITES(1));
158 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
159 if (physical_device->rad_info.chip_class >= CIK)
160 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
161 }
162
163 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
164 if (physical_device->rad_info.chip_class < CIK)
165 radeon_set_config_reg(cs, GRBM_GFX_INDEX,
166 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
167 INSTANCE_BROADCAST_WRITES);
168 else
169 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
170 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
171 S_030800_INSTANCE_BROADCAST_WRITES(1));
172 }
173
174 static void
175 si_emit_compute(struct radv_physical_device *physical_device,
176 struct radeon_winsys_cs *cs)
177 {
178 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
179 radeon_emit(cs, 0);
180 radeon_emit(cs, 0);
181 radeon_emit(cs, 0);
182
183 radeon_set_sh_reg_seq(cs, R_00B854_COMPUTE_RESOURCE_LIMITS, 3);
184 radeon_emit(cs, 0);
185 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
186 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
187 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
188
189 if (physical_device->rad_info.chip_class >= CIK) {
190 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
191 radeon_set_sh_reg_seq(cs,
192 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
193 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
194 S_00B864_SH1_CU_EN(0xffff));
195 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
196 S_00B868_SH1_CU_EN(0xffff));
197 }
198
199 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
200 * and is now per pipe, so it should be handled in the
201 * kernel if we want to use something other than the default value,
202 * which is now 0x22f.
203 */
204 if (physical_device->rad_info.chip_class <= SI) {
205 /* XXX: This should be:
206 * (number of compute units) * 4 * (waves per simd) - 1 */
207
208 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
209 0x190 /* Default value */);
210 }
211 }
212
213 void
214 si_init_compute(struct radv_cmd_buffer *cmd_buffer)
215 {
216 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
217 si_emit_compute(physical_device, cmd_buffer->cs);
218 }
219
220 static void
221 si_emit_config(struct radv_physical_device *physical_device,
222 struct radeon_winsys_cs *cs)
223 {
224 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
225 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
226 unsigned raster_config, raster_config_1;
227 int i;
228
229 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
230 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
231 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
232
233 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
234 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
235
236 /* FIXME calculate these values somehow ??? */
237 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
238 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
239 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
240
241 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
242 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
243
244 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
245 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
246 if (physical_device->rad_info.chip_class >= GFX9)
247 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF, 0);
248 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
249 if (physical_device->rad_info.chip_class < CIK)
250 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
251 S_008A14_CLIP_VTX_REORDER_ENA(1));
252
253 radeon_set_context_reg(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
254 radeon_set_context_reg(cs, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
255
256 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
257
258 for (i = 0; i < 16; i++) {
259 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
260 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
261 }
262
263 switch (physical_device->rad_info.family) {
264 case CHIP_TAHITI:
265 case CHIP_PITCAIRN:
266 raster_config = 0x2a00126a;
267 raster_config_1 = 0x00000000;
268 break;
269 case CHIP_VERDE:
270 raster_config = 0x0000124a;
271 raster_config_1 = 0x00000000;
272 break;
273 case CHIP_OLAND:
274 raster_config = 0x00000082;
275 raster_config_1 = 0x00000000;
276 break;
277 case CHIP_HAINAN:
278 raster_config = 0x00000000;
279 raster_config_1 = 0x00000000;
280 break;
281 case CHIP_BONAIRE:
282 raster_config = 0x16000012;
283 raster_config_1 = 0x00000000;
284 break;
285 case CHIP_HAWAII:
286 raster_config = 0x3a00161a;
287 raster_config_1 = 0x0000002e;
288 break;
289 case CHIP_FIJI:
290 if (physical_device->rad_info.cik_macrotile_mode_array[0] == 0x000000e8) {
291 /* old kernels with old tiling config */
292 raster_config = 0x16000012;
293 raster_config_1 = 0x0000002a;
294 } else {
295 raster_config = 0x3a00161a;
296 raster_config_1 = 0x0000002e;
297 }
298 break;
299 case CHIP_POLARIS10:
300 raster_config = 0x16000012;
301 raster_config_1 = 0x0000002a;
302 break;
303 case CHIP_POLARIS11:
304 case CHIP_POLARIS12:
305 raster_config = 0x16000012;
306 raster_config_1 = 0x00000000;
307 break;
308 case CHIP_TONGA:
309 raster_config = 0x16000012;
310 raster_config_1 = 0x0000002a;
311 break;
312 case CHIP_ICELAND:
313 if (num_rb == 1)
314 raster_config = 0x00000000;
315 else
316 raster_config = 0x00000002;
317 raster_config_1 = 0x00000000;
318 break;
319 case CHIP_CARRIZO:
320 raster_config = 0x00000002;
321 raster_config_1 = 0x00000000;
322 break;
323 case CHIP_KAVERI:
324 /* KV should be 0x00000002, but that causes problems with radeon */
325 raster_config = 0x00000000; /* 0x00000002 */
326 raster_config_1 = 0x00000000;
327 break;
328 case CHIP_KABINI:
329 case CHIP_MULLINS:
330 case CHIP_STONEY:
331 raster_config = 0x00000000;
332 raster_config_1 = 0x00000000;
333 break;
334 default:
335 if (physical_device->rad_info.chip_class <= VI) {
336 fprintf(stderr,
337 "radeonsi: Unknown GPU, using 0 for raster_config\n");
338 raster_config = 0x00000000;
339 raster_config_1 = 0x00000000;
340 }
341 break;
342 }
343
344 /* Always use the default config when all backends are enabled
345 * (or when we failed to determine the enabled backends).
346 */
347 if (physical_device->rad_info.chip_class <= VI) {
348 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
349 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
350 raster_config);
351 if (physical_device->rad_info.chip_class >= CIK)
352 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
353 raster_config_1);
354 } else {
355 si_write_harvested_raster_configs(physical_device, cs, raster_config, raster_config_1);
356 }
357 }
358
359 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
360 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
361 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
362 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
363 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
364 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
365 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
366
367 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
368 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
369 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
370 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
371 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
372
373 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
374 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
375 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
376 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
377 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
378 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
379
380 if (physical_device->rad_info.chip_class >= GFX9) {
381 radeon_set_context_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
382 radeon_set_context_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
383 radeon_set_context_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
384 } else {
385 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
386 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
387 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
388 }
389
390 if (physical_device->rad_info.chip_class >= CIK) {
391 if (physical_device->rad_info.chip_class >= GFX9) {
392 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_CU_EN(0xffff));
393 } else {
394 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
395 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
396 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
397 /* If this is 0, Bonaire can hang even if GS isn't being used.
398 * Other chips are unaffected. These are suboptimal values,
399 * but we don't use on-chip GS.
400 */
401 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
402 S_028A44_ES_VERTS_PER_SUBGRP(64) |
403 S_028A44_GS_PRIMS_PER_SUBGRP(4));
404 }
405 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
406
407 if (physical_device->rad_info.num_good_compute_units /
408 (physical_device->rad_info.max_se * physical_device->rad_info.max_sh_per_se) <= 4) {
409 /* Too few available compute units per SH. Disallowing
410 * VS to run on CU0 could hurt us more than late VS
411 * allocation would help.
412 *
413 * LATE_ALLOC_VS = 2 is the highest safe number.
414 */
415 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
416 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
417 } else {
418 /* Set LATE_ALLOC_VS == 31. It should be less than
419 * the number of scratch waves. Limitations:
420 * - VS can't execute on CU0.
421 * - If HS writes outputs to LDS, LS can't execute on CU0.
422 */
423 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
424 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
425 }
426
427 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
428 }
429
430 if (physical_device->rad_info.chip_class >= VI) {
431 uint32_t vgt_tess_distribution;
432 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
433 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
434 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
435 if (physical_device->rad_info.family < CHIP_POLARIS10)
436 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
437 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
438
439 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
440 S_028B50_ACCUM_TRI(11) |
441 S_028B50_ACCUM_QUAD(11) |
442 S_028B50_DONUT_SPLIT(16);
443
444 if (physical_device->rad_info.family == CHIP_FIJI ||
445 physical_device->rad_info.family >= CHIP_POLARIS10)
446 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
447
448 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
449 vgt_tess_distribution);
450 } else {
451 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
452 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
453 }
454
455 if (physical_device->has_rbplus)
456 radeon_set_context_reg(cs, R_028C40_PA_SC_SHADER_CONTROL, 0);
457
458 if (physical_device->rad_info.chip_class >= GFX9) {
459 unsigned num_se = physical_device->rad_info.max_se;
460 unsigned pc_lines = 0;
461
462 switch (physical_device->rad_info.family) {
463 case CHIP_VEGA10:
464 pc_lines = 4096;
465 break;
466 case CHIP_RAVEN:
467 pc_lines = 1024;
468 break;
469 default:
470 assert(0);
471 }
472
473 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
474 S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF));
475 radeon_set_context_reg(cs, R_028064_DB_RENDER_FILTER, 0);
476 /* TODO: We can use this to disable RBs for rendering to GART: */
477 radeon_set_context_reg(cs, R_02835C_PA_SC_TILE_STEERING_OVERRIDE, 0);
478 radeon_set_context_reg(cs, R_02883C_PA_SU_OVER_RASTERIZATION_CNTL, 0);
479 /* TODO: Enable the binner: */
480 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
481 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
482 S_028C44_DISABLE_START_OF_PRIM(1));
483 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
484 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
485 S_028C48_MAX_PRIM_PER_BATCH(1023));
486 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
487 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
488 radeon_set_context_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
489 }
490 si_emit_compute(physical_device, cs);
491 }
492
493 void si_init_config(struct radv_cmd_buffer *cmd_buffer)
494 {
495 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
496
497 si_emit_config(physical_device, cmd_buffer->cs);
498 }
499
500 void
501 cik_create_gfx_config(struct radv_device *device)
502 {
503 struct radeon_winsys_cs *cs = device->ws->cs_create(device->ws, RING_GFX);
504 if (!cs)
505 return;
506
507 si_emit_config(device->physical_device, cs);
508
509 while (cs->cdw & 7) {
510 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
511 radeon_emit(cs, 0x80000000);
512 else
513 radeon_emit(cs, 0xffff1000);
514 }
515
516 device->gfx_init = device->ws->buffer_create(device->ws,
517 cs->cdw * 4, 4096,
518 RADEON_DOMAIN_GTT,
519 RADEON_FLAG_CPU_ACCESS);
520 if (!device->gfx_init)
521 goto fail;
522
523 void *map = device->ws->buffer_map(device->gfx_init);
524 if (!map) {
525 device->ws->buffer_destroy(device->gfx_init);
526 device->gfx_init = NULL;
527 goto fail;
528 }
529 memcpy(map, cs->buf, cs->cdw * 4);
530
531 device->ws->buffer_unmap(device->gfx_init);
532 device->gfx_init_size_dw = cs->cdw;
533 fail:
534 device->ws->cs_destroy(cs);
535 }
536
537 static void
538 get_viewport_xform(const VkViewport *viewport,
539 float scale[3], float translate[3])
540 {
541 float x = viewport->x;
542 float y = viewport->y;
543 float half_width = 0.5f * viewport->width;
544 float half_height = 0.5f * viewport->height;
545 double n = viewport->minDepth;
546 double f = viewport->maxDepth;
547
548 scale[0] = half_width;
549 translate[0] = half_width + x;
550 scale[1] = half_height;
551 translate[1] = half_height + y;
552
553 scale[2] = (f - n);
554 translate[2] = n;
555 }
556
557 void
558 si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
559 int count, const VkViewport *viewports)
560 {
561 int i;
562
563 assert(count);
564 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
565 first_vp * 4 * 6, count * 6);
566
567 for (i = 0; i < count; i++) {
568 float scale[3], translate[3];
569
570
571 get_viewport_xform(&viewports[i], scale, translate);
572 radeon_emit(cs, fui(scale[0]));
573 radeon_emit(cs, fui(translate[0]));
574 radeon_emit(cs, fui(scale[1]));
575 radeon_emit(cs, fui(translate[1]));
576 radeon_emit(cs, fui(scale[2]));
577 radeon_emit(cs, fui(translate[2]));
578 }
579
580 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
581 first_vp * 4 * 2, count * 2);
582 for (i = 0; i < count; i++) {
583 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
584 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
585 radeon_emit(cs, fui(zmin));
586 radeon_emit(cs, fui(zmax));
587 }
588 }
589
590 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
591 {
592 float scale[3], translate[3];
593 VkRect2D rect;
594
595 get_viewport_xform(viewport, scale, translate);
596
597 rect.offset.x = translate[0] - abs(scale[0]);
598 rect.offset.y = translate[1] - abs(scale[1]);
599 rect.extent.width = ceilf(translate[0] + abs(scale[0])) - rect.offset.x;
600 rect.extent.height = ceilf(translate[1] + abs(scale[1])) - rect.offset.y;
601
602 return rect;
603 }
604
605 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
606 VkRect2D ret;
607 ret.offset.x = MAX2(a->offset.x, b->offset.x);
608 ret.offset.y = MAX2(a->offset.y, b->offset.y);
609 ret.extent.width = MIN2(a->offset.x + a->extent.width,
610 b->offset.x + b->extent.width) - ret.offset.x;
611 ret.extent.height = MIN2(a->offset.y + a->extent.height,
612 b->offset.y + b->extent.height) - ret.offset.y;
613 return ret;
614 }
615
616 void
617 si_write_scissors(struct radeon_winsys_cs *cs, int first,
618 int count, const VkRect2D *scissors,
619 const VkViewport *viewports, bool can_use_guardband)
620 {
621 int i;
622 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
623 const float max_range = 32767.0f;
624 assert(count);
625
626 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
627 for (i = 0; i < count; i++) {
628 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
629 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
630
631 get_viewport_xform(viewports + i, scale, translate);
632 scale[0] = abs(scale[0]);
633 scale[1] = abs(scale[1]);
634
635 if (scale[0] < 0.5)
636 scale[0] = 0.5;
637 if (scale[1] < 0.5)
638 scale[1] = 0.5;
639
640 guardband_x = MIN2(guardband_x, (max_range - abs(translate[0])) / scale[0]);
641 guardband_y = MIN2(guardband_y, (max_range - abs(translate[1])) / scale[1]);
642
643 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
644 S_028250_TL_Y(scissor.offset.y) |
645 S_028250_WINDOW_OFFSET_DISABLE(1));
646 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
647 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
648 }
649 if (!can_use_guardband) {
650 guardband_x = 1.0;
651 guardband_y = 1.0;
652 }
653
654 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
655 radeon_emit(cs, fui(guardband_y));
656 radeon_emit(cs, fui(1.0));
657 radeon_emit(cs, fui(guardband_x));
658 radeon_emit(cs, fui(1.0));
659 }
660
661 static inline unsigned
662 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
663 {
664 if (num == 0)
665 return 0;
666
667 if (info->incr == 0)
668 return 0;
669
670 if (num < info->min)
671 return 0;
672
673 return 1 + ((num - info->min) / info->incr);
674 }
675
676 uint32_t
677 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
678 bool instanced_draw, bool indirect_draw,
679 uint32_t draw_vertex_count)
680 {
681 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
682 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
683 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
684 unsigned prim = cmd_buffer->state.pipeline->graphics.prim;
685 unsigned primgroup_size = 128; /* recommended without a GS */
686 unsigned max_primgroup_in_wave = 2;
687 /* SWITCH_ON_EOP(0) is always preferable. */
688 bool wd_switch_on_eop = false;
689 bool ia_switch_on_eop = false;
690 bool ia_switch_on_eoi = false;
691 bool partial_vs_wave = false;
692 bool partial_es_wave = false;
693 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
694 bool multi_instances_smaller_than_primgroup;
695
696 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
697 primgroup_size = cmd_buffer->state.pipeline->graphics.tess.num_patches;
698 else if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
699 primgroup_size = 64; /* recommended with a GS */
700
701 multi_instances_smaller_than_primgroup = indirect_draw || (instanced_draw &&
702 num_prims < primgroup_size);
703 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline)) {
704 /* SWITCH_ON_EOI must be set if PrimID is used. */
705 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.uses_prim_id ||
706 cmd_buffer->state.pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.uses_prim_id)
707 ia_switch_on_eoi = true;
708
709 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
710 if ((family == CHIP_TAHITI ||
711 family == CHIP_PITCAIRN ||
712 family == CHIP_BONAIRE) &&
713 radv_pipeline_has_gs(cmd_buffer->state.pipeline))
714 partial_vs_wave = true;
715
716 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
717 if (cmd_buffer->device->has_distributed_tess) {
718 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
719 partial_es_wave = true;
720
721 if (family == CHIP_TONGA ||
722 family == CHIP_FIJI ||
723 family == CHIP_POLARIS10 ||
724 family == CHIP_POLARIS11 ||
725 family == CHIP_POLARIS12)
726 partial_vs_wave = true;
727 } else {
728 partial_vs_wave = true;
729 }
730 }
731 }
732 /* TODO linestipple */
733
734 if (chip_class >= CIK) {
735 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
736 * 4 shader engines. Set 1 to pass the assertion below.
737 * The other cases are hardware requirements. */
738 if (info->max_se < 4 ||
739 prim == V_008958_DI_PT_POLYGON ||
740 prim == V_008958_DI_PT_LINELOOP ||
741 prim == V_008958_DI_PT_TRIFAN ||
742 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
743 (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
744 (family < CHIP_POLARIS10 ||
745 (prim != V_008958_DI_PT_POINTLIST &&
746 prim != V_008958_DI_PT_LINESTRIP &&
747 prim != V_008958_DI_PT_TRISTRIP))))
748 wd_switch_on_eop = true;
749
750 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
751 * We don't know that for indirect drawing, so treat it as
752 * always problematic. */
753 if (family == CHIP_HAWAII &&
754 (instanced_draw || indirect_draw))
755 wd_switch_on_eop = true;
756
757 /* Performance recommendation for 4 SE Gfx7-8 parts if
758 * instances are smaller than a primgroup.
759 * Assume indirect draws always use small instances.
760 * This is needed for good VS wave utilization.
761 */
762 if (chip_class <= VI &&
763 info->max_se == 4 &&
764 multi_instances_smaller_than_primgroup)
765 wd_switch_on_eop = true;
766
767 /* Required on CIK and later. */
768 if (info->max_se > 2 && !wd_switch_on_eop)
769 ia_switch_on_eoi = true;
770
771 /* Required by Hawaii and, for some special cases, by VI. */
772 if (ia_switch_on_eoi &&
773 (family == CHIP_HAWAII ||
774 (chip_class == VI &&
775 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
776 partial_vs_wave = true;
777
778 /* Instancing bug on Bonaire. */
779 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
780 (instanced_draw || indirect_draw))
781 partial_vs_wave = true;
782
783 /* If the WD switch is false, the IA switch must be false too. */
784 assert(wd_switch_on_eop || !ia_switch_on_eop);
785 }
786 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
787 if (ia_switch_on_eoi)
788 partial_es_wave = true;
789
790 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
791 /* GS requirement. */
792 if (SI_GS_PER_ES / primgroup_size >= cmd_buffer->device->gs_table_depth - 3)
793 partial_es_wave = true;
794
795 /* Hw bug with single-primitive instances and SWITCH_ON_EOI
796 * on multi-SE chips. */
797 if (info->max_se >= 2 && ia_switch_on_eoi &&
798 ((instanced_draw || indirect_draw) &&
799 num_prims <= 1))
800 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
801 }
802
803 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
804 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
805 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
806 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
807 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
808 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop : 0) |
809 S_028AA8_MAX_PRIMGRP_IN_WAVE(chip_class >= VI ?
810 max_primgroup_in_wave : 0);
811
812 }
813
814 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
815 enum chip_class chip_class,
816 bool is_mec,
817 unsigned event, unsigned event_flags,
818 unsigned data_sel,
819 uint64_t va,
820 uint32_t old_fence,
821 uint32_t new_fence)
822 {
823 unsigned op = EVENT_TYPE(event) |
824 EVENT_INDEX(5) |
825 event_flags;
826 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
827
828 if (chip_class >= GFX9 || is_gfx8_mec) {
829 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, 0));
830 radeon_emit(cs, op);
831 radeon_emit(cs, EOP_DATA_SEL(data_sel));
832 radeon_emit(cs, va); /* address lo */
833 radeon_emit(cs, va >> 32); /* address hi */
834 radeon_emit(cs, new_fence); /* immediate data lo */
835 radeon_emit(cs, 0); /* immediate data hi */
836 if (!is_gfx8_mec)
837 radeon_emit(cs, 0); /* unused */
838 } else {
839 if (chip_class == CIK ||
840 chip_class == VI) {
841 /* Two EOP events are required to make all engines go idle
842 * (and optional cache flushes executed) before the timestamp
843 * is written.
844 */
845 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
846 radeon_emit(cs, op);
847 radeon_emit(cs, va);
848 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
849 radeon_emit(cs, old_fence); /* immediate data */
850 radeon_emit(cs, 0); /* unused */
851 }
852
853 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
854 radeon_emit(cs, op);
855 radeon_emit(cs, va);
856 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
857 radeon_emit(cs, new_fence); /* immediate data */
858 radeon_emit(cs, 0); /* unused */
859 }
860 }
861
862 void
863 si_emit_wait_fence(struct radeon_winsys_cs *cs,
864 uint64_t va, uint32_t ref,
865 uint32_t mask)
866 {
867 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
868 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
869 radeon_emit(cs, va);
870 radeon_emit(cs, va >> 32);
871 radeon_emit(cs, ref); /* reference value */
872 radeon_emit(cs, mask); /* mask */
873 radeon_emit(cs, 4); /* poll interval */
874 }
875
876 static void
877 si_emit_acquire_mem(struct radeon_winsys_cs *cs,
878 bool is_mec, bool is_gfx9,
879 unsigned cp_coher_cntl)
880 {
881 if (is_mec || is_gfx9) {
882 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
883 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0) |
884 PKT3_SHADER_TYPE_S(is_mec));
885 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
886 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
887 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
888 radeon_emit(cs, 0); /* CP_COHER_BASE */
889 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
890 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
891 } else {
892 /* ACQUIRE_MEM is only required on a compute ring. */
893 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
894 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
895 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
896 radeon_emit(cs, 0); /* CP_COHER_BASE */
897 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
898 }
899 }
900
901 void
902 si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
903 enum chip_class chip_class,
904 uint32_t *flush_cnt,
905 uint64_t flush_va,
906 bool is_mec,
907 enum radv_cmd_flush_bits flush_bits)
908 {
909 unsigned cp_coher_cntl = 0;
910 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
911 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
912
913 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
914 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
915 if (flush_bits & RADV_CMD_FLAG_INV_SMEM_L1)
916 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
917
918 if (chip_class <= VI) {
919 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
920 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
921 S_0085F0_CB0_DEST_BASE_ENA(1) |
922 S_0085F0_CB1_DEST_BASE_ENA(1) |
923 S_0085F0_CB2_DEST_BASE_ENA(1) |
924 S_0085F0_CB3_DEST_BASE_ENA(1) |
925 S_0085F0_CB4_DEST_BASE_ENA(1) |
926 S_0085F0_CB5_DEST_BASE_ENA(1) |
927 S_0085F0_CB6_DEST_BASE_ENA(1) |
928 S_0085F0_CB7_DEST_BASE_ENA(1);
929
930 /* Necessary for DCC */
931 if (chip_class >= VI) {
932 si_cs_emit_write_event_eop(cs,
933 chip_class,
934 is_mec,
935 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
936 0, 0, 0, 0, 0);
937 }
938 }
939 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
940 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
941 S_0085F0_DB_DEST_BASE_ENA(1);
942 }
943 }
944
945 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
946 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
947 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
948 }
949
950 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
951 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
952 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
953 }
954
955 if (!flush_cb_db) {
956 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
957 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
958 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
959 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
960 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
961 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
962 }
963 }
964
965 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
966 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
967 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
968 }
969
970 if (chip_class >= GFX9 && flush_cb_db) {
971 unsigned cb_db_event, tc_flags;
972
973 /* Set the CB/DB flush event. */
974 switch (flush_cb_db) {
975 case RADV_CMD_FLAG_FLUSH_AND_INV_CB:
976 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
977 break;
978 case RADV_CMD_FLAG_FLUSH_AND_INV_DB:
979 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
980 break;
981 default:
982 /* both CB & DB */
983 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
984 }
985
986 /* TC | TC_WB = invalidate L2 data
987 * TC_MD | TC_WB = invalidate L2 metadata
988 * TC | TC_WB | TC_MD = invalidate L2 data & metadata
989 *
990 * The metadata cache must always be invalidated for coherency
991 * between CB/DB and shaders. (metadata = HTILE, CMASK, DCC)
992 *
993 * TC must be invalidated on GFX9 only if the CB/DB surface is
994 * not pipe-aligned. If the surface is RB-aligned, it might not
995 * strictly be pipe-aligned since RB alignment takes precendence.
996 */
997 tc_flags = EVENT_TC_WB_ACTION_ENA |
998 EVENT_TC_MD_ACTION_ENA;
999
1000 /* Ideally flush TC together with CB/DB. */
1001 if (flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) {
1002 tc_flags |= EVENT_TC_ACTION_ENA |
1003 EVENT_TCL1_ACTION_ENA;
1004
1005 /* Clear the flags. */
1006 flush_bits &= ~(RADV_CMD_FLAG_INV_GLOBAL_L2 |
1007 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 |
1008 RADV_CMD_FLAG_INV_VMEM_L1);
1009 }
1010 assert(flush_cnt);
1011 uint32_t old_fence = (*flush_cnt)++;
1012
1013 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags, 1,
1014 flush_va, old_fence, *flush_cnt);
1015 si_emit_wait_fence(cs, flush_va, *flush_cnt, 0xffffffff);
1016 }
1017
1018 /* VGT state sync */
1019 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1020 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1021 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1022 }
1023
1024 /* Make sure ME is idle (it executes most packets) before continuing.
1025 * This prevents read-after-write hazards between PFP and ME.
1026 */
1027 if ((cp_coher_cntl ||
1028 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1029 RADV_CMD_FLAG_INV_VMEM_L1 |
1030 RADV_CMD_FLAG_INV_GLOBAL_L2 |
1031 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) &&
1032 !is_mec) {
1033 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1034 radeon_emit(cs, 0);
1035 }
1036
1037 if ((flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) ||
1038 (chip_class <= CIK && (flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) {
1039 si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9,
1040 cp_coher_cntl |
1041 S_0085F0_TC_ACTION_ENA(1) |
1042 S_0085F0_TCL1_ACTION_ENA(1) |
1043 S_0301F0_TC_WB_ACTION_ENA(chip_class >= VI));
1044 cp_coher_cntl = 0;
1045 } else {
1046 if(flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2) {
1047 /* WB = write-back
1048 * NC = apply to non-coherent MTYPEs
1049 * (i.e. MTYPE <= 1, which is what we use everywhere)
1050 *
1051 * WB doesn't work without NC.
1052 */
1053 si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9,
1054 cp_coher_cntl |
1055 S_0301F0_TC_WB_ACTION_ENA(1) |
1056 S_0301F0_TC_NC_ACTION_ENA(1));
1057 cp_coher_cntl = 0;
1058 }
1059 if (flush_bits & RADV_CMD_FLAG_INV_VMEM_L1) {
1060 si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9,
1061 cp_coher_cntl |
1062 S_0085F0_TCL1_ACTION_ENA(1));
1063 cp_coher_cntl = 0;
1064 }
1065 }
1066
1067 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1068 * Therefore, it should be last. Done in PFP.
1069 */
1070 if (cp_coher_cntl)
1071 si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9, cp_coher_cntl);
1072 }
1073
1074 void
1075 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
1076 {
1077 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1078 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
1079 if (is_compute)
1080 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1081 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1082 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1083 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1084 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1085 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1086 RADV_CMD_FLAG_VGT_FLUSH);
1087
1088 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1089
1090 uint32_t *ptr = NULL;
1091 uint64_t va = 0;
1092 if (chip_class == GFX9) {
1093 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->gfx9_fence_bo) + cmd_buffer->gfx9_fence_offset;
1094 ptr = &cmd_buffer->gfx9_fence_idx;
1095 }
1096 si_cs_emit_cache_flush(cmd_buffer->cs,
1097 cmd_buffer->device->physical_device->rad_info.chip_class,
1098 ptr, va,
1099 radv_cmd_buffer_uses_mec(cmd_buffer),
1100 cmd_buffer->state.flush_bits);
1101
1102
1103 if (cmd_buffer->state.flush_bits)
1104 radv_cmd_buffer_trace_emit(cmd_buffer);
1105 cmd_buffer->state.flush_bits = 0;
1106 }
1107
1108
1109 /* Set this if you want the 3D engine to wait until CP DMA is done.
1110 * It should be set on the last CP DMA packet. */
1111 #define CP_DMA_SYNC (1 << 0)
1112
1113 /* Set this if the source data was used as a destination in a previous CP DMA
1114 * packet. It's for preventing a read-after-write (RAW) hazard between two
1115 * CP DMA packets. */
1116 #define CP_DMA_RAW_WAIT (1 << 1)
1117 #define CP_DMA_USE_L2 (1 << 2)
1118 #define CP_DMA_CLEAR (1 << 3)
1119
1120 /* Alignment for optimal performance. */
1121 #define SI_CPDMA_ALIGNMENT 32
1122
1123 /* The max number of bytes that can be copied per packet. */
1124 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1125 {
1126 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1127 S_414_BYTE_COUNT_GFX9(~0u) :
1128 S_414_BYTE_COUNT_GFX6(~0u);
1129
1130 /* make it aligned for optimal performance */
1131 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1132 }
1133
1134 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1135 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1136 * clear value.
1137 */
1138 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1139 uint64_t dst_va, uint64_t src_va,
1140 unsigned size, unsigned flags)
1141 {
1142 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1143 uint32_t header = 0, command = 0;
1144
1145 assert(size);
1146 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1147
1148 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1149 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1150 command |= S_414_BYTE_COUNT_GFX9(size);
1151 else
1152 command |= S_414_BYTE_COUNT_GFX6(size);
1153
1154 /* Sync flags. */
1155 if (flags & CP_DMA_SYNC)
1156 header |= S_411_CP_SYNC(1);
1157 else {
1158 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1159 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1160 else
1161 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1162 }
1163
1164 if (flags & CP_DMA_RAW_WAIT)
1165 command |= S_414_RAW_WAIT(1);
1166
1167 /* Src and dst flags. */
1168 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1169 !(flags & CP_DMA_CLEAR) &&
1170 src_va == dst_va)
1171 header |= S_411_DSL_SEL(V_411_NOWHERE); /* prefetch only */
1172 else if (flags & CP_DMA_USE_L2)
1173 header |= S_411_DSL_SEL(V_411_DST_ADDR_TC_L2);
1174
1175 if (flags & CP_DMA_CLEAR)
1176 header |= S_411_SRC_SEL(V_411_DATA);
1177 else if (flags & CP_DMA_USE_L2)
1178 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1179
1180 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1181 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
1182 radeon_emit(cs, header);
1183 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1184 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1185 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1186 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1187 radeon_emit(cs, command);
1188 } else {
1189 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1190 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
1191 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1192 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1193 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1194 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1195 radeon_emit(cs, command);
1196 }
1197
1198 /* CP DMA is executed in ME, but index buffers are read by PFP.
1199 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1200 * indices. If we wanted to execute CP DMA in PFP, this packet
1201 * should precede it.
1202 */
1203 if ((flags & CP_DMA_SYNC) && cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1204 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1205 radeon_emit(cs, 0);
1206 }
1207
1208 radv_cmd_buffer_trace_emit(cmd_buffer);
1209 }
1210
1211 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1212 unsigned size)
1213 {
1214 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1215 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1216
1217 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1218 aligned_size, CP_DMA_USE_L2);
1219 }
1220
1221 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1222 uint64_t remaining_size, unsigned *flags)
1223 {
1224
1225 /* Flush the caches for the first copy only.
1226 * Also wait for the previous CP DMA operations.
1227 */
1228 if (cmd_buffer->state.flush_bits) {
1229 si_emit_cache_flush(cmd_buffer);
1230 *flags |= CP_DMA_RAW_WAIT;
1231 }
1232
1233 /* Do the synchronization after the last dma, so that all data
1234 * is written to memory.
1235 */
1236 if (byte_count == remaining_size)
1237 *flags |= CP_DMA_SYNC;
1238 }
1239
1240 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1241 {
1242 uint64_t va;
1243 uint32_t offset;
1244 unsigned dma_flags = 0;
1245 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1246 void *ptr;
1247
1248 assert(size < SI_CPDMA_ALIGNMENT);
1249
1250 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1251
1252 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1253 va += offset;
1254
1255 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1256
1257 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1258 dma_flags);
1259 }
1260
1261 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1262 uint64_t src_va, uint64_t dest_va,
1263 uint64_t size)
1264 {
1265 uint64_t main_src_va, main_dest_va;
1266 uint64_t skipped_size = 0, realign_size = 0;
1267
1268
1269 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1270 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1271 /* If the size is not aligned, we must add a dummy copy at the end
1272 * just to align the internal counter. Otherwise, the DMA engine
1273 * would slow down by an order of magnitude for following copies.
1274 */
1275 if (size % SI_CPDMA_ALIGNMENT)
1276 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1277
1278 /* If the copy begins unaligned, we must start copying from the next
1279 * aligned block and the skipped part should be copied after everything
1280 * else has been copied. Only the src alignment matters, not dst.
1281 */
1282 if (src_va % SI_CPDMA_ALIGNMENT) {
1283 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1284 /* The main part will be skipped if the size is too small. */
1285 skipped_size = MIN2(skipped_size, size);
1286 size -= skipped_size;
1287 }
1288 }
1289 main_src_va = src_va + skipped_size;
1290 main_dest_va = dest_va + skipped_size;
1291
1292 while (size) {
1293 unsigned dma_flags = 0;
1294 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1295
1296 si_cp_dma_prepare(cmd_buffer, byte_count,
1297 size + skipped_size + realign_size,
1298 &dma_flags);
1299
1300 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1301 byte_count, dma_flags);
1302
1303 size -= byte_count;
1304 main_src_va += byte_count;
1305 main_dest_va += byte_count;
1306 }
1307
1308 if (skipped_size) {
1309 unsigned dma_flags = 0;
1310
1311 si_cp_dma_prepare(cmd_buffer, skipped_size,
1312 size + skipped_size + realign_size,
1313 &dma_flags);
1314
1315 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1316 skipped_size, dma_flags);
1317 }
1318 if (realign_size)
1319 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1320 }
1321
1322 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1323 uint64_t size, unsigned value)
1324 {
1325
1326 if (!size)
1327 return;
1328
1329 assert(va % 4 == 0 && size % 4 == 0);
1330
1331 while (size) {
1332 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1333 unsigned dma_flags = CP_DMA_CLEAR;
1334
1335 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1336
1337 /* Emit the clear packet. */
1338 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1339 dma_flags);
1340
1341 size -= byte_count;
1342 va += byte_count;
1343 }
1344 }
1345
1346 /* For MSAA sample positions. */
1347 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1348 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
1349 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1350 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1351 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1352
1353
1354 /* 2xMSAA
1355 * There are two locations (4, 4), (-4, -4). */
1356 const uint32_t eg_sample_locs_2x[4] = {
1357 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1358 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1359 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1360 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1361 };
1362 const unsigned eg_max_dist_2x = 4;
1363 /* 4xMSAA
1364 * There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
1365 const uint32_t eg_sample_locs_4x[4] = {
1366 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1367 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1368 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1369 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1370 };
1371 const unsigned eg_max_dist_4x = 6;
1372
1373 /* Cayman 8xMSAA */
1374 static const uint32_t cm_sample_locs_8x[] = {
1375 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1376 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1377 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1378 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1379 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1380 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1381 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1382 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1383 };
1384 static const unsigned cm_max_dist_8x = 8;
1385 /* Cayman 16xMSAA */
1386 static const uint32_t cm_sample_locs_16x[] = {
1387 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1388 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1389 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1390 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1391 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1392 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1393 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1394 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1395 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1396 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1397 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1398 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1399 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1400 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1401 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1402 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1403 };
1404 static const unsigned cm_max_dist_16x = 8;
1405
1406 unsigned radv_cayman_get_maxdist(int log_samples)
1407 {
1408 unsigned max_dist[] = {
1409 0,
1410 eg_max_dist_2x,
1411 eg_max_dist_4x,
1412 cm_max_dist_8x,
1413 cm_max_dist_16x
1414 };
1415 return max_dist[log_samples];
1416 }
1417
1418 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples)
1419 {
1420 switch (nr_samples) {
1421 default:
1422 case 1:
1423 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
1424 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
1425 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
1426 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
1427 break;
1428 case 2:
1429 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
1430 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
1431 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
1432 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
1433 break;
1434 case 4:
1435 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
1436 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
1437 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
1438 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
1439 break;
1440 case 8:
1441 radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1442 radeon_emit(cs, cm_sample_locs_8x[0]);
1443 radeon_emit(cs, cm_sample_locs_8x[4]);
1444 radeon_emit(cs, 0);
1445 radeon_emit(cs, 0);
1446 radeon_emit(cs, cm_sample_locs_8x[1]);
1447 radeon_emit(cs, cm_sample_locs_8x[5]);
1448 radeon_emit(cs, 0);
1449 radeon_emit(cs, 0);
1450 radeon_emit(cs, cm_sample_locs_8x[2]);
1451 radeon_emit(cs, cm_sample_locs_8x[6]);
1452 radeon_emit(cs, 0);
1453 radeon_emit(cs, 0);
1454 radeon_emit(cs, cm_sample_locs_8x[3]);
1455 radeon_emit(cs, cm_sample_locs_8x[7]);
1456 break;
1457 case 16:
1458 radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
1459 radeon_emit(cs, cm_sample_locs_16x[0]);
1460 radeon_emit(cs, cm_sample_locs_16x[4]);
1461 radeon_emit(cs, cm_sample_locs_16x[8]);
1462 radeon_emit(cs, cm_sample_locs_16x[12]);
1463 radeon_emit(cs, cm_sample_locs_16x[1]);
1464 radeon_emit(cs, cm_sample_locs_16x[5]);
1465 radeon_emit(cs, cm_sample_locs_16x[9]);
1466 radeon_emit(cs, cm_sample_locs_16x[13]);
1467 radeon_emit(cs, cm_sample_locs_16x[2]);
1468 radeon_emit(cs, cm_sample_locs_16x[6]);
1469 radeon_emit(cs, cm_sample_locs_16x[10]);
1470 radeon_emit(cs, cm_sample_locs_16x[14]);
1471 radeon_emit(cs, cm_sample_locs_16x[3]);
1472 radeon_emit(cs, cm_sample_locs_16x[7]);
1473 radeon_emit(cs, cm_sample_locs_16x[11]);
1474 radeon_emit(cs, cm_sample_locs_16x[15]);
1475 break;
1476 }
1477 }
1478
1479 static void radv_cayman_get_sample_position(struct radv_device *device,
1480 unsigned sample_count,
1481 unsigned sample_index, float *out_value)
1482 {
1483 int offset, index;
1484 struct {
1485 int idx:4;
1486 } val;
1487 switch (sample_count) {
1488 case 1:
1489 default:
1490 out_value[0] = out_value[1] = 0.5;
1491 break;
1492 case 2:
1493 offset = 4 * (sample_index * 2);
1494 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1495 out_value[0] = (float)(val.idx + 8) / 16.0f;
1496 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1497 out_value[1] = (float)(val.idx + 8) / 16.0f;
1498 break;
1499 case 4:
1500 offset = 4 * (sample_index * 2);
1501 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1502 out_value[0] = (float)(val.idx + 8) / 16.0f;
1503 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1504 out_value[1] = (float)(val.idx + 8) / 16.0f;
1505 break;
1506 case 8:
1507 offset = 4 * (sample_index % 4 * 2);
1508 index = (sample_index / 4) * 4;
1509 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1510 out_value[0] = (float)(val.idx + 8) / 16.0f;
1511 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1512 out_value[1] = (float)(val.idx + 8) / 16.0f;
1513 break;
1514 case 16:
1515 offset = 4 * (sample_index % 4 * 2);
1516 index = (sample_index / 4) * 4;
1517 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1518 out_value[0] = (float)(val.idx + 8) / 16.0f;
1519 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1520 out_value[1] = (float)(val.idx + 8) / 16.0f;
1521 break;
1522 }
1523 }
1524
1525 void radv_device_init_msaa(struct radv_device *device)
1526 {
1527 int i;
1528 radv_cayman_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1529
1530 for (i = 0; i < 2; i++)
1531 radv_cayman_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1532 for (i = 0; i < 4; i++)
1533 radv_cayman_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1534 for (i = 0; i < 8; i++)
1535 radv_cayman_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1536 for (i = 0; i < 16; i++)
1537 radv_cayman_get_sample_position(device, 16, i, device->sample_locations_16x[i]);
1538 }