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radv: Split out the ia_multi_vgt_param precomputation.
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for SI */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "gfx9d.h"
35 #include "radv_util.h"
36 #include "main/macros.h"
37
38 static void
39 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
40 struct radeon_winsys_cs *cs,
41 unsigned raster_config,
42 unsigned raster_config_1)
43 {
44 unsigned sh_per_se = MAX2(physical_device->rad_info.max_sh_per_se, 1);
45 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
46 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
47 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
48 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
49 unsigned rb_per_se = num_rb / num_se;
50 unsigned se_mask[4];
51 unsigned se;
52
53 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
54 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
55 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
56 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
57
58 assert(num_se == 1 || num_se == 2 || num_se == 4);
59 assert(sh_per_se == 1 || sh_per_se == 2);
60 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
61
62 /* XXX: I can't figure out what the *_XSEL and *_YSEL
63 * fields are for, so I'm leaving them as their default
64 * values. */
65
66 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
67 (!se_mask[2] && !se_mask[3]))) {
68 raster_config_1 &= C_028354_SE_PAIR_MAP;
69
70 if (!se_mask[0] && !se_mask[1]) {
71 raster_config_1 |=
72 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
73 } else {
74 raster_config_1 |=
75 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
76 }
77 }
78
79 for (se = 0; se < num_se; se++) {
80 unsigned raster_config_se = raster_config;
81 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
82 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
83 int idx = (se / 2) * 2;
84
85 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
86 raster_config_se &= C_028350_SE_MAP;
87
88 if (!se_mask[idx]) {
89 raster_config_se |=
90 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
91 } else {
92 raster_config_se |=
93 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
94 }
95 }
96
97 pkr0_mask &= rb_mask;
98 pkr1_mask &= rb_mask;
99 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
100 raster_config_se &= C_028350_PKR_MAP;
101
102 if (!pkr0_mask) {
103 raster_config_se |=
104 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
105 } else {
106 raster_config_se |=
107 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
108 }
109 }
110
111 if (rb_per_se >= 2) {
112 unsigned rb0_mask = 1 << (se * rb_per_se);
113 unsigned rb1_mask = rb0_mask << 1;
114
115 rb0_mask &= rb_mask;
116 rb1_mask &= rb_mask;
117 if (!rb0_mask || !rb1_mask) {
118 raster_config_se &= C_028350_RB_MAP_PKR0;
119
120 if (!rb0_mask) {
121 raster_config_se |=
122 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
123 } else {
124 raster_config_se |=
125 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
126 }
127 }
128
129 if (rb_per_se > 2) {
130 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
131 rb1_mask = rb0_mask << 1;
132 rb0_mask &= rb_mask;
133 rb1_mask &= rb_mask;
134 if (!rb0_mask || !rb1_mask) {
135 raster_config_se &= C_028350_RB_MAP_PKR1;
136
137 if (!rb0_mask) {
138 raster_config_se |=
139 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
140 } else {
141 raster_config_se |=
142 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
143 }
144 }
145 }
146 }
147
148 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
149 if (physical_device->rad_info.chip_class < CIK)
150 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
151 S_00802C_SE_INDEX(se) |
152 S_00802C_SH_BROADCAST_WRITES(1) |
153 S_00802C_INSTANCE_BROADCAST_WRITES(1));
154 else
155 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
156 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
157 S_030800_INSTANCE_BROADCAST_WRITES(1));
158 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
159 if (physical_device->rad_info.chip_class >= CIK)
160 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
161 }
162
163 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
164 if (physical_device->rad_info.chip_class < CIK)
165 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
166 S_00802C_SE_BROADCAST_WRITES(1) |
167 S_00802C_SH_BROADCAST_WRITES(1) |
168 S_00802C_INSTANCE_BROADCAST_WRITES(1));
169 else
170 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
171 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
172 S_030800_INSTANCE_BROADCAST_WRITES(1));
173 }
174
175 static void
176 si_emit_compute(struct radv_physical_device *physical_device,
177 struct radeon_winsys_cs *cs)
178 {
179 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
180 radeon_emit(cs, 0);
181 radeon_emit(cs, 0);
182 radeon_emit(cs, 0);
183
184 radeon_set_sh_reg_seq(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
185 S_00B854_WAVES_PER_SH(0x3));
186 radeon_emit(cs, 0);
187 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
188 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
189 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
190
191 if (physical_device->rad_info.chip_class >= CIK) {
192 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
193 radeon_set_sh_reg_seq(cs,
194 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
195 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
196 S_00B864_SH1_CU_EN(0xffff));
197 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
198 S_00B868_SH1_CU_EN(0xffff));
199 }
200
201 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
202 * and is now per pipe, so it should be handled in the
203 * kernel if we want to use something other than the default value,
204 * which is now 0x22f.
205 */
206 if (physical_device->rad_info.chip_class <= SI) {
207 /* XXX: This should be:
208 * (number of compute units) * 4 * (waves per simd) - 1 */
209
210 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
211 0x190 /* Default value */);
212 }
213 }
214
215 void
216 si_init_compute(struct radv_cmd_buffer *cmd_buffer)
217 {
218 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
219 si_emit_compute(physical_device, cmd_buffer->cs);
220 }
221
222 /* 12.4 fixed-point */
223 static unsigned radv_pack_float_12p4(float x)
224 {
225 return x <= 0 ? 0 :
226 x >= 4096 ? 0xffff : x * 16;
227 }
228
229 static void
230 si_set_raster_config(struct radv_physical_device *physical_device,
231 struct radeon_winsys_cs *cs)
232 {
233 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
234 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
235 unsigned raster_config, raster_config_1;
236
237 switch (physical_device->rad_info.family) {
238 case CHIP_TAHITI:
239 case CHIP_PITCAIRN:
240 raster_config = 0x2a00126a;
241 raster_config_1 = 0x00000000;
242 break;
243 case CHIP_VERDE:
244 raster_config = 0x0000124a;
245 raster_config_1 = 0x00000000;
246 break;
247 case CHIP_OLAND:
248 raster_config = 0x00000082;
249 raster_config_1 = 0x00000000;
250 break;
251 case CHIP_HAINAN:
252 raster_config = 0x00000000;
253 raster_config_1 = 0x00000000;
254 break;
255 case CHIP_BONAIRE:
256 raster_config = 0x16000012;
257 raster_config_1 = 0x00000000;
258 break;
259 case CHIP_HAWAII:
260 raster_config = 0x3a00161a;
261 raster_config_1 = 0x0000002e;
262 break;
263 case CHIP_FIJI:
264 if (physical_device->rad_info.cik_macrotile_mode_array[0] == 0x000000e8) {
265 /* old kernels with old tiling config */
266 raster_config = 0x16000012;
267 raster_config_1 = 0x0000002a;
268 } else {
269 raster_config = 0x3a00161a;
270 raster_config_1 = 0x0000002e;
271 }
272 break;
273 case CHIP_POLARIS10:
274 raster_config = 0x16000012;
275 raster_config_1 = 0x0000002a;
276 break;
277 case CHIP_POLARIS11:
278 case CHIP_POLARIS12:
279 raster_config = 0x16000012;
280 raster_config_1 = 0x00000000;
281 break;
282 case CHIP_TONGA:
283 raster_config = 0x16000012;
284 raster_config_1 = 0x0000002a;
285 break;
286 case CHIP_ICELAND:
287 if (num_rb == 1)
288 raster_config = 0x00000000;
289 else
290 raster_config = 0x00000002;
291 raster_config_1 = 0x00000000;
292 break;
293 case CHIP_CARRIZO:
294 raster_config = 0x00000002;
295 raster_config_1 = 0x00000000;
296 break;
297 case CHIP_KAVERI:
298 /* KV should be 0x00000002, but that causes problems with radeon */
299 raster_config = 0x00000000; /* 0x00000002 */
300 raster_config_1 = 0x00000000;
301 break;
302 case CHIP_KABINI:
303 case CHIP_MULLINS:
304 case CHIP_STONEY:
305 raster_config = 0x00000000;
306 raster_config_1 = 0x00000000;
307 break;
308 default:
309 fprintf(stderr,
310 "radv: Unknown GPU, using 0 for raster_config\n");
311 raster_config = 0x00000000;
312 raster_config_1 = 0x00000000;
313 break;
314 }
315
316 /* Always use the default config when all backends are enabled
317 * (or when we failed to determine the enabled backends).
318 */
319 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
320 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
321 raster_config);
322 if (physical_device->rad_info.chip_class >= CIK)
323 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
324 raster_config_1);
325 } else {
326 si_write_harvested_raster_configs(physical_device, cs,
327 raster_config,
328 raster_config_1);
329 }
330 }
331
332 static void
333 si_emit_config(struct radv_physical_device *physical_device,
334 struct radeon_winsys_cs *cs)
335 {
336 int i;
337
338 /* Only SI can disable CLEAR_STATE for now. */
339 assert(physical_device->has_clear_state ||
340 physical_device->rad_info.chip_class == SI);
341
342 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
343 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
344 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
345
346 if (physical_device->has_clear_state) {
347 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
348 radeon_emit(cs, 0);
349 }
350
351 if (physical_device->rad_info.chip_class <= VI)
352 si_set_raster_config(physical_device, cs);
353
354 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
355 if (!physical_device->has_clear_state)
356 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
357
358 /* FIXME calculate these values somehow ??? */
359 if (physical_device->rad_info.chip_class <= VI) {
360 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
361 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
362 }
363
364 if (!physical_device->has_clear_state) {
365 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
366 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
367 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
368 }
369
370 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
371 if (!physical_device->has_clear_state)
372 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
373 if (physical_device->rad_info.chip_class < CIK)
374 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
375 S_008A14_CLIP_VTX_REORDER_ENA(1));
376
377 radeon_set_context_reg(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
378 radeon_set_context_reg(cs, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
379
380 if (!physical_device->has_clear_state)
381 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
382
383 /* CLEAR_STATE doesn't clear these correctly on certain generations.
384 * I don't know why. Deduced by trial and error.
385 */
386 if (physical_device->rad_info.chip_class <= CIK) {
387 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
388 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
389 S_028204_WINDOW_OFFSET_DISABLE(1));
390 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
391 S_028240_WINDOW_OFFSET_DISABLE(1));
392 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
393 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
394 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
395 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
396 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
397 }
398
399 if (!physical_device->has_clear_state) {
400 for (i = 0; i < 16; i++) {
401 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
402 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
403 }
404 }
405
406 if (!physical_device->has_clear_state) {
407 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
408 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
409 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
410 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
411 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
412 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
413 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
414 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
415 }
416
417 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
418 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
419 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
420
421 if (physical_device->rad_info.chip_class >= GFX9) {
422 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
423 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
424 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
425 } else {
426 /* These registers, when written, also overwrite the
427 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
428 * them. It would be an issue if there was another UMD
429 * changing them.
430 */
431 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
432 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
433 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
434 }
435
436 if (physical_device->rad_info.chip_class >= CIK) {
437 if (physical_device->rad_info.chip_class >= GFX9) {
438 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
439 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
440 } else {
441 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
442 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
443 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
444 S_00B41C_WAVE_LIMIT(0x3F));
445 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
446 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
447 /* If this is 0, Bonaire can hang even if GS isn't being used.
448 * Other chips are unaffected. These are suboptimal values,
449 * but we don't use on-chip GS.
450 */
451 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
452 S_028A44_ES_VERTS_PER_SUBGRP(64) |
453 S_028A44_GS_PRIMS_PER_SUBGRP(4));
454 }
455 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
456 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
457
458 if (physical_device->rad_info.num_good_compute_units /
459 (physical_device->rad_info.max_se * physical_device->rad_info.max_sh_per_se) <= 4) {
460 /* Too few available compute units per SH. Disallowing
461 * VS to run on CU0 could hurt us more than late VS
462 * allocation would help.
463 *
464 * LATE_ALLOC_VS = 2 is the highest safe number.
465 */
466 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
467 S_00B118_CU_EN(0xffff) | S_00B118_WAVE_LIMIT(0x3F) );
468 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
469 } else {
470 /* Set LATE_ALLOC_VS == 31. It should be less than
471 * the number of scratch waves. Limitations:
472 * - VS can't execute on CU0.
473 * - If HS writes outputs to LDS, LS can't execute on CU0.
474 */
475 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
476 S_00B118_CU_EN(0xfffe) | S_00B118_WAVE_LIMIT(0x3F));
477 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
478 }
479
480 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
481 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
482 }
483
484 if (physical_device->rad_info.chip_class >= VI) {
485 uint32_t vgt_tess_distribution;
486 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
487 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
488 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
489
490 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
491 S_028B50_ACCUM_TRI(11) |
492 S_028B50_ACCUM_QUAD(11) |
493 S_028B50_DONUT_SPLIT(16);
494
495 if (physical_device->rad_info.family == CHIP_FIJI ||
496 physical_device->rad_info.family >= CHIP_POLARIS10)
497 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
498
499 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
500 vgt_tess_distribution);
501 } else if (!physical_device->has_clear_state) {
502 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
503 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
504 }
505
506 if (physical_device->rad_info.chip_class >= GFX9) {
507 unsigned num_se = physical_device->rad_info.max_se;
508 unsigned pc_lines = 0;
509
510 switch (physical_device->rad_info.family) {
511 case CHIP_VEGA10:
512 pc_lines = 4096;
513 break;
514 case CHIP_RAVEN:
515 pc_lines = 1024;
516 break;
517 default:
518 assert(0);
519 }
520
521 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
522 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
523 S_028C48_MAX_PRIM_PER_BATCH(1023));
524 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
525 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
526 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
527 }
528
529 unsigned tmp = (unsigned)(1.0 * 8.0);
530 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
531 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
532 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
533 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
534 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
535
536 if (!physical_device->has_clear_state) {
537 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
538 S_028004_ZPASS_INCREMENT_DISABLE(1));
539 }
540
541 si_emit_compute(physical_device, cs);
542 }
543
544 void si_init_config(struct radv_cmd_buffer *cmd_buffer)
545 {
546 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
547
548 si_emit_config(physical_device, cmd_buffer->cs);
549 }
550
551 void
552 cik_create_gfx_config(struct radv_device *device)
553 {
554 struct radeon_winsys_cs *cs = device->ws->cs_create(device->ws, RING_GFX);
555 if (!cs)
556 return;
557
558 si_emit_config(device->physical_device, cs);
559
560 while (cs->cdw & 7) {
561 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
562 radeon_emit(cs, 0x80000000);
563 else
564 radeon_emit(cs, 0xffff1000);
565 }
566
567 device->gfx_init = device->ws->buffer_create(device->ws,
568 cs->cdw * 4, 4096,
569 RADEON_DOMAIN_GTT,
570 RADEON_FLAG_CPU_ACCESS|
571 RADEON_FLAG_NO_INTERPROCESS_SHARING |
572 RADEON_FLAG_READ_ONLY);
573 if (!device->gfx_init)
574 goto fail;
575
576 void *map = device->ws->buffer_map(device->gfx_init);
577 if (!map) {
578 device->ws->buffer_destroy(device->gfx_init);
579 device->gfx_init = NULL;
580 goto fail;
581 }
582 memcpy(map, cs->buf, cs->cdw * 4);
583
584 device->ws->buffer_unmap(device->gfx_init);
585 device->gfx_init_size_dw = cs->cdw;
586 fail:
587 device->ws->cs_destroy(cs);
588 }
589
590 static void
591 get_viewport_xform(const VkViewport *viewport,
592 float scale[3], float translate[3])
593 {
594 float x = viewport->x;
595 float y = viewport->y;
596 float half_width = 0.5f * viewport->width;
597 float half_height = 0.5f * viewport->height;
598 double n = viewport->minDepth;
599 double f = viewport->maxDepth;
600
601 scale[0] = half_width;
602 translate[0] = half_width + x;
603 scale[1] = half_height;
604 translate[1] = half_height + y;
605
606 scale[2] = (f - n);
607 translate[2] = n;
608 }
609
610 void
611 si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
612 int count, const VkViewport *viewports)
613 {
614 int i;
615
616 assert(count);
617 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
618 first_vp * 4 * 6, count * 6);
619
620 for (i = 0; i < count; i++) {
621 float scale[3], translate[3];
622
623
624 get_viewport_xform(&viewports[i], scale, translate);
625 radeon_emit(cs, fui(scale[0]));
626 radeon_emit(cs, fui(translate[0]));
627 radeon_emit(cs, fui(scale[1]));
628 radeon_emit(cs, fui(translate[1]));
629 radeon_emit(cs, fui(scale[2]));
630 radeon_emit(cs, fui(translate[2]));
631 }
632
633 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
634 first_vp * 4 * 2, count * 2);
635 for (i = 0; i < count; i++) {
636 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
637 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
638 radeon_emit(cs, fui(zmin));
639 radeon_emit(cs, fui(zmax));
640 }
641 }
642
643 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
644 {
645 float scale[3], translate[3];
646 VkRect2D rect;
647
648 get_viewport_xform(viewport, scale, translate);
649
650 rect.offset.x = translate[0] - abs(scale[0]);
651 rect.offset.y = translate[1] - abs(scale[1]);
652 rect.extent.width = ceilf(translate[0] + abs(scale[0])) - rect.offset.x;
653 rect.extent.height = ceilf(translate[1] + abs(scale[1])) - rect.offset.y;
654
655 return rect;
656 }
657
658 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
659 VkRect2D ret;
660 ret.offset.x = MAX2(a->offset.x, b->offset.x);
661 ret.offset.y = MAX2(a->offset.y, b->offset.y);
662 ret.extent.width = MIN2(a->offset.x + a->extent.width,
663 b->offset.x + b->extent.width) - ret.offset.x;
664 ret.extent.height = MIN2(a->offset.y + a->extent.height,
665 b->offset.y + b->extent.height) - ret.offset.y;
666 return ret;
667 }
668
669 void
670 si_write_scissors(struct radeon_winsys_cs *cs, int first,
671 int count, const VkRect2D *scissors,
672 const VkViewport *viewports, bool can_use_guardband)
673 {
674 int i;
675 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
676 const float max_range = 32767.0f;
677 if (!count)
678 return;
679
680 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
681 for (i = 0; i < count; i++) {
682 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
683 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
684
685 get_viewport_xform(viewports + i, scale, translate);
686 scale[0] = abs(scale[0]);
687 scale[1] = abs(scale[1]);
688
689 if (scale[0] < 0.5)
690 scale[0] = 0.5;
691 if (scale[1] < 0.5)
692 scale[1] = 0.5;
693
694 guardband_x = MIN2(guardband_x, (max_range - abs(translate[0])) / scale[0]);
695 guardband_y = MIN2(guardband_y, (max_range - abs(translate[1])) / scale[1]);
696
697 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
698 S_028250_TL_Y(scissor.offset.y) |
699 S_028250_WINDOW_OFFSET_DISABLE(1));
700 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
701 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
702 }
703 if (!can_use_guardband) {
704 guardband_x = 1.0;
705 guardband_y = 1.0;
706 }
707
708 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
709 radeon_emit(cs, fui(guardband_y));
710 radeon_emit(cs, fui(1.0));
711 radeon_emit(cs, fui(guardband_x));
712 radeon_emit(cs, fui(1.0));
713 }
714
715 static inline unsigned
716 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
717 {
718 if (num == 0)
719 return 0;
720
721 if (info->incr == 0)
722 return 0;
723
724 if (num < info->min)
725 return 0;
726
727 return 1 + ((num - info->min) / info->incr);
728 }
729
730 uint32_t
731 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
732 bool instanced_draw, bool indirect_draw,
733 uint32_t draw_vertex_count)
734 {
735 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
736 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
737 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
738 const unsigned max_primgroup_in_wave = 2;
739 /* SWITCH_ON_EOP(0) is always preferable. */
740 bool wd_switch_on_eop = false;
741 bool ia_switch_on_eop = false;
742 bool ia_switch_on_eoi = false;
743 bool partial_vs_wave = false;
744 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave;
745 bool multi_instances_smaller_than_primgroup;
746
747 multi_instances_smaller_than_primgroup = indirect_draw;
748 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
749 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
750 if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size)
751 multi_instances_smaller_than_primgroup = true;
752 }
753
754 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
755 partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
756
757 if (chip_class >= CIK) {
758 wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.wd_switch_on_eop;
759
760 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
761 * We don't know that for indirect drawing, so treat it as
762 * always problematic. */
763 if (family == CHIP_HAWAII &&
764 (instanced_draw || indirect_draw))
765 wd_switch_on_eop = true;
766
767 /* Performance recommendation for 4 SE Gfx7-8 parts if
768 * instances are smaller than a primgroup.
769 * Assume indirect draws always use small instances.
770 * This is needed for good VS wave utilization.
771 */
772 if (chip_class <= VI &&
773 info->max_se == 4 &&
774 multi_instances_smaller_than_primgroup)
775 wd_switch_on_eop = true;
776
777 /* Required on CIK and later. */
778 if (info->max_se > 2 && !wd_switch_on_eop)
779 ia_switch_on_eoi = true;
780
781 /* Required by Hawaii and, for some special cases, by VI. */
782 if (ia_switch_on_eoi &&
783 (family == CHIP_HAWAII ||
784 (chip_class == VI &&
785 /* max primgroup in wave is always 2 - leave this for documentation */
786 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
787 partial_vs_wave = true;
788
789 /* Instancing bug on Bonaire. */
790 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
791 (instanced_draw || indirect_draw))
792 partial_vs_wave = true;
793
794 /* If the WD switch is false, the IA switch must be false too. */
795 assert(wd_switch_on_eop || !ia_switch_on_eop);
796 }
797 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
798 if (chip_class <= VI && ia_switch_on_eoi)
799 partial_es_wave = true;
800
801 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
802 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
803 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
804 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
805 */
806 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
807 bool set_vgt_flush = indirect_draw;
808 if (!set_vgt_flush && instanced_draw) {
809 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
810 if (num_prims <= 1)
811 set_vgt_flush = true;
812 }
813 if (set_vgt_flush)
814 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
815 }
816 }
817
818 return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base |
819 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
820 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
821 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
822 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
823 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop : 0);
824
825 }
826
827 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
828 bool predicated,
829 enum chip_class chip_class,
830 bool is_mec,
831 unsigned event, unsigned event_flags,
832 unsigned data_sel,
833 uint64_t va,
834 uint32_t old_fence,
835 uint32_t new_fence)
836 {
837 unsigned op = EVENT_TYPE(event) |
838 EVENT_INDEX(5) |
839 event_flags;
840 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
841
842 if (chip_class >= GFX9 || is_gfx8_mec) {
843 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, predicated));
844 radeon_emit(cs, op);
845 radeon_emit(cs, EOP_DATA_SEL(data_sel));
846 radeon_emit(cs, va); /* address lo */
847 radeon_emit(cs, va >> 32); /* address hi */
848 radeon_emit(cs, new_fence); /* immediate data lo */
849 radeon_emit(cs, 0); /* immediate data hi */
850 if (!is_gfx8_mec)
851 radeon_emit(cs, 0); /* unused */
852 } else {
853 if (chip_class == CIK ||
854 chip_class == VI) {
855 /* Two EOP events are required to make all engines go idle
856 * (and optional cache flushes executed) before the timestamp
857 * is written.
858 */
859 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated));
860 radeon_emit(cs, op);
861 radeon_emit(cs, va);
862 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
863 radeon_emit(cs, old_fence); /* immediate data */
864 radeon_emit(cs, 0); /* unused */
865 }
866
867 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated));
868 radeon_emit(cs, op);
869 radeon_emit(cs, va);
870 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
871 radeon_emit(cs, new_fence); /* immediate data */
872 radeon_emit(cs, 0); /* unused */
873 }
874 }
875
876 void
877 si_emit_wait_fence(struct radeon_winsys_cs *cs,
878 bool predicated,
879 uint64_t va, uint32_t ref,
880 uint32_t mask)
881 {
882 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, predicated));
883 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
884 radeon_emit(cs, va);
885 radeon_emit(cs, va >> 32);
886 radeon_emit(cs, ref); /* reference value */
887 radeon_emit(cs, mask); /* mask */
888 radeon_emit(cs, 4); /* poll interval */
889 }
890
891 static void
892 si_emit_acquire_mem(struct radeon_winsys_cs *cs,
893 bool is_mec,
894 bool predicated,
895 bool is_gfx9,
896 unsigned cp_coher_cntl)
897 {
898 if (is_mec || is_gfx9) {
899 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
900 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, predicated) |
901 PKT3_SHADER_TYPE_S(is_mec));
902 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
903 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
904 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
905 radeon_emit(cs, 0); /* CP_COHER_BASE */
906 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
907 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
908 } else {
909 /* ACQUIRE_MEM is only required on a compute ring. */
910 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, predicated));
911 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
912 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
913 radeon_emit(cs, 0); /* CP_COHER_BASE */
914 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
915 }
916 }
917
918 void
919 si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
920 bool predicated,
921 enum chip_class chip_class,
922 uint32_t *flush_cnt,
923 uint64_t flush_va,
924 bool is_mec,
925 enum radv_cmd_flush_bits flush_bits)
926 {
927 unsigned cp_coher_cntl = 0;
928 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
929 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
930
931 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
932 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
933 if (flush_bits & RADV_CMD_FLAG_INV_SMEM_L1)
934 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
935
936 if (chip_class <= VI) {
937 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
938 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
939 S_0085F0_CB0_DEST_BASE_ENA(1) |
940 S_0085F0_CB1_DEST_BASE_ENA(1) |
941 S_0085F0_CB2_DEST_BASE_ENA(1) |
942 S_0085F0_CB3_DEST_BASE_ENA(1) |
943 S_0085F0_CB4_DEST_BASE_ENA(1) |
944 S_0085F0_CB5_DEST_BASE_ENA(1) |
945 S_0085F0_CB6_DEST_BASE_ENA(1) |
946 S_0085F0_CB7_DEST_BASE_ENA(1);
947
948 /* Necessary for DCC */
949 if (chip_class >= VI) {
950 si_cs_emit_write_event_eop(cs,
951 predicated,
952 chip_class,
953 is_mec,
954 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
955 0, 0, 0, 0, 0);
956 }
957 }
958 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
959 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
960 S_0085F0_DB_DEST_BASE_ENA(1);
961 }
962 }
963
964 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
965 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
966 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
967 }
968
969 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
970 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
971 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
972 }
973
974 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
975 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
976 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
977 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
978 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
979 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
980 }
981
982 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
983 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
984 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
985 }
986
987 if (chip_class >= GFX9 && flush_cb_db) {
988 unsigned cb_db_event, tc_flags;
989
990 #if 0
991 /* This breaks a bunch of:
992 dEQP-VK.renderpass.dedicated_allocation.formats.d32_sfloat_s8_uint.input*.
993 use the big hammer always.
994 */
995 /* Set the CB/DB flush event. */
996 switch (flush_cb_db) {
997 case RADV_CMD_FLAG_FLUSH_AND_INV_CB:
998 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
999 break;
1000 case RADV_CMD_FLAG_FLUSH_AND_INV_DB:
1001 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1002 break;
1003 default:
1004 /* both CB & DB */
1005 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1006 }
1007 #else
1008 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1009 #endif
1010 /* These are the only allowed combinations. If you need to
1011 * do multiple operations at once, do them separately.
1012 * All operations that invalidate L2 also seem to invalidate
1013 * metadata. Volatile (VOL) and WC flushes are not listed here.
1014 *
1015 * TC | TC_WB = writeback & invalidate L2 & L1
1016 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1017 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1018 * TC | TC_NC = invalidate L2 for MTYPE == NC
1019 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1020 * TCL1 = invalidate L1
1021 */
1022 tc_flags = EVENT_TC_ACTION_ENA |
1023 EVENT_TC_MD_ACTION_ENA;
1024
1025 /* Ideally flush TC together with CB/DB. */
1026 if (flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) {
1027 /* Writeback and invalidate everything in L2 & L1. */
1028 tc_flags = EVENT_TC_ACTION_ENA |
1029 EVENT_TC_WB_ACTION_ENA;
1030
1031
1032 /* Clear the flags. */
1033 flush_bits &= ~(RADV_CMD_FLAG_INV_GLOBAL_L2 |
1034 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 |
1035 RADV_CMD_FLAG_INV_VMEM_L1);
1036 }
1037 assert(flush_cnt);
1038 uint32_t old_fence = (*flush_cnt)++;
1039
1040 si_cs_emit_write_event_eop(cs, predicated, chip_class, false, cb_db_event, tc_flags, 1,
1041 flush_va, old_fence, *flush_cnt);
1042 si_emit_wait_fence(cs, predicated, flush_va, *flush_cnt, 0xffffffff);
1043 }
1044
1045 /* VGT state sync */
1046 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1047 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
1048 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1049 }
1050
1051 /* Make sure ME is idle (it executes most packets) before continuing.
1052 * This prevents read-after-write hazards between PFP and ME.
1053 */
1054 if ((cp_coher_cntl ||
1055 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1056 RADV_CMD_FLAG_INV_VMEM_L1 |
1057 RADV_CMD_FLAG_INV_GLOBAL_L2 |
1058 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) &&
1059 !is_mec) {
1060 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, predicated));
1061 radeon_emit(cs, 0);
1062 }
1063
1064 if ((flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) ||
1065 (chip_class <= CIK && (flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) {
1066 si_emit_acquire_mem(cs, is_mec, predicated, chip_class >= GFX9,
1067 cp_coher_cntl |
1068 S_0085F0_TC_ACTION_ENA(1) |
1069 S_0085F0_TCL1_ACTION_ENA(1) |
1070 S_0301F0_TC_WB_ACTION_ENA(chip_class >= VI));
1071 cp_coher_cntl = 0;
1072 } else {
1073 if(flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2) {
1074 /* WB = write-back
1075 * NC = apply to non-coherent MTYPEs
1076 * (i.e. MTYPE <= 1, which is what we use everywhere)
1077 *
1078 * WB doesn't work without NC.
1079 */
1080 si_emit_acquire_mem(cs, is_mec, predicated,
1081 chip_class >= GFX9,
1082 cp_coher_cntl |
1083 S_0301F0_TC_WB_ACTION_ENA(1) |
1084 S_0301F0_TC_NC_ACTION_ENA(1));
1085 cp_coher_cntl = 0;
1086 }
1087 if (flush_bits & RADV_CMD_FLAG_INV_VMEM_L1) {
1088 si_emit_acquire_mem(cs, is_mec,
1089 predicated, chip_class >= GFX9,
1090 cp_coher_cntl |
1091 S_0085F0_TCL1_ACTION_ENA(1));
1092 cp_coher_cntl = 0;
1093 }
1094 }
1095
1096 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1097 * Therefore, it should be last. Done in PFP.
1098 */
1099 if (cp_coher_cntl)
1100 si_emit_acquire_mem(cs, is_mec, predicated, chip_class >= GFX9, cp_coher_cntl);
1101 }
1102
1103 void
1104 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
1105 {
1106 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1107
1108 if (is_compute)
1109 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1110 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1111 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1112 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1113 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1114 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1115 RADV_CMD_FLAG_VGT_FLUSH);
1116
1117 if (!cmd_buffer->state.flush_bits)
1118 return;
1119
1120 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
1121 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1122
1123 uint32_t *ptr = NULL;
1124 uint64_t va = 0;
1125 if (chip_class == GFX9) {
1126 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) + cmd_buffer->gfx9_fence_offset;
1127 ptr = &cmd_buffer->gfx9_fence_idx;
1128 }
1129 si_cs_emit_cache_flush(cmd_buffer->cs,
1130 cmd_buffer->state.predicating,
1131 cmd_buffer->device->physical_device->rad_info.chip_class,
1132 ptr, va,
1133 radv_cmd_buffer_uses_mec(cmd_buffer),
1134 cmd_buffer->state.flush_bits);
1135
1136
1137 if (unlikely(cmd_buffer->device->trace_bo))
1138 radv_cmd_buffer_trace_emit(cmd_buffer);
1139
1140 cmd_buffer->state.flush_bits = 0;
1141 }
1142
1143 /* sets the CP predication state using a boolean stored at va */
1144 void
1145 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
1146 {
1147 uint32_t op = 0;
1148
1149 if (va)
1150 op = PRED_OP(PREDICATION_OP_BOOL64) | PREDICATION_DRAW_VISIBLE;
1151 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1152 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1153 radeon_emit(cmd_buffer->cs, op);
1154 radeon_emit(cmd_buffer->cs, va);
1155 radeon_emit(cmd_buffer->cs, va >> 32);
1156 } else {
1157 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1158 radeon_emit(cmd_buffer->cs, va);
1159 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1160 }
1161 }
1162
1163 /* Set this if you want the 3D engine to wait until CP DMA is done.
1164 * It should be set on the last CP DMA packet. */
1165 #define CP_DMA_SYNC (1 << 0)
1166
1167 /* Set this if the source data was used as a destination in a previous CP DMA
1168 * packet. It's for preventing a read-after-write (RAW) hazard between two
1169 * CP DMA packets. */
1170 #define CP_DMA_RAW_WAIT (1 << 1)
1171 #define CP_DMA_USE_L2 (1 << 2)
1172 #define CP_DMA_CLEAR (1 << 3)
1173
1174 /* Alignment for optimal performance. */
1175 #define SI_CPDMA_ALIGNMENT 32
1176
1177 /* The max number of bytes that can be copied per packet. */
1178 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1179 {
1180 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1181 S_414_BYTE_COUNT_GFX9(~0u) :
1182 S_414_BYTE_COUNT_GFX6(~0u);
1183
1184 /* make it aligned for optimal performance */
1185 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1186 }
1187
1188 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1189 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1190 * clear value.
1191 */
1192 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1193 uint64_t dst_va, uint64_t src_va,
1194 unsigned size, unsigned flags)
1195 {
1196 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1197 uint32_t header = 0, command = 0;
1198
1199 assert(size);
1200 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1201
1202 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1203 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1204 command |= S_414_BYTE_COUNT_GFX9(size);
1205 else
1206 command |= S_414_BYTE_COUNT_GFX6(size);
1207
1208 /* Sync flags. */
1209 if (flags & CP_DMA_SYNC)
1210 header |= S_411_CP_SYNC(1);
1211 else {
1212 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1213 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1214 else
1215 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1216 }
1217
1218 if (flags & CP_DMA_RAW_WAIT)
1219 command |= S_414_RAW_WAIT(1);
1220
1221 /* Src and dst flags. */
1222 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1223 !(flags & CP_DMA_CLEAR) &&
1224 src_va == dst_va)
1225 header |= S_411_DSL_SEL(V_411_NOWHERE); /* prefetch only */
1226 else if (flags & CP_DMA_USE_L2)
1227 header |= S_411_DSL_SEL(V_411_DST_ADDR_TC_L2);
1228
1229 if (flags & CP_DMA_CLEAR)
1230 header |= S_411_SRC_SEL(V_411_DATA);
1231 else if (flags & CP_DMA_USE_L2)
1232 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1233
1234 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1235 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1236 radeon_emit(cs, header);
1237 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1238 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1239 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1240 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1241 radeon_emit(cs, command);
1242 } else {
1243 assert(!(flags & CP_DMA_USE_L2));
1244 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1245 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1246 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1247 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1248 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1249 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1250 radeon_emit(cs, command);
1251 }
1252
1253 /* CP DMA is executed in ME, but index buffers are read by PFP.
1254 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1255 * indices. If we wanted to execute CP DMA in PFP, this packet
1256 * should precede it.
1257 */
1258 if ((flags & CP_DMA_SYNC) && cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1259 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1260 radeon_emit(cs, 0);
1261 }
1262
1263 if (unlikely(cmd_buffer->device->trace_bo))
1264 radv_cmd_buffer_trace_emit(cmd_buffer);
1265 }
1266
1267 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1268 unsigned size)
1269 {
1270 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1271 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1272
1273 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1274 aligned_size, CP_DMA_USE_L2);
1275 }
1276
1277 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1278 uint64_t remaining_size, unsigned *flags)
1279 {
1280
1281 /* Flush the caches for the first copy only.
1282 * Also wait for the previous CP DMA operations.
1283 */
1284 if (cmd_buffer->state.flush_bits) {
1285 si_emit_cache_flush(cmd_buffer);
1286 *flags |= CP_DMA_RAW_WAIT;
1287 }
1288
1289 /* Do the synchronization after the last dma, so that all data
1290 * is written to memory.
1291 */
1292 if (byte_count == remaining_size)
1293 *flags |= CP_DMA_SYNC;
1294 }
1295
1296 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1297 {
1298 uint64_t va;
1299 uint32_t offset;
1300 unsigned dma_flags = 0;
1301 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1302 void *ptr;
1303
1304 assert(size < SI_CPDMA_ALIGNMENT);
1305
1306 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1307
1308 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1309 va += offset;
1310
1311 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1312
1313 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1314 dma_flags);
1315 }
1316
1317 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1318 uint64_t src_va, uint64_t dest_va,
1319 uint64_t size)
1320 {
1321 uint64_t main_src_va, main_dest_va;
1322 uint64_t skipped_size = 0, realign_size = 0;
1323
1324
1325 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1326 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1327 /* If the size is not aligned, we must add a dummy copy at the end
1328 * just to align the internal counter. Otherwise, the DMA engine
1329 * would slow down by an order of magnitude for following copies.
1330 */
1331 if (size % SI_CPDMA_ALIGNMENT)
1332 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1333
1334 /* If the copy begins unaligned, we must start copying from the next
1335 * aligned block and the skipped part should be copied after everything
1336 * else has been copied. Only the src alignment matters, not dst.
1337 */
1338 if (src_va % SI_CPDMA_ALIGNMENT) {
1339 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1340 /* The main part will be skipped if the size is too small. */
1341 skipped_size = MIN2(skipped_size, size);
1342 size -= skipped_size;
1343 }
1344 }
1345 main_src_va = src_va + skipped_size;
1346 main_dest_va = dest_va + skipped_size;
1347
1348 while (size) {
1349 unsigned dma_flags = 0;
1350 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1351
1352 si_cp_dma_prepare(cmd_buffer, byte_count,
1353 size + skipped_size + realign_size,
1354 &dma_flags);
1355
1356 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1357 byte_count, dma_flags);
1358
1359 size -= byte_count;
1360 main_src_va += byte_count;
1361 main_dest_va += byte_count;
1362 }
1363
1364 if (skipped_size) {
1365 unsigned dma_flags = 0;
1366
1367 si_cp_dma_prepare(cmd_buffer, skipped_size,
1368 size + skipped_size + realign_size,
1369 &dma_flags);
1370
1371 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1372 skipped_size, dma_flags);
1373 }
1374 if (realign_size)
1375 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1376 }
1377
1378 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1379 uint64_t size, unsigned value)
1380 {
1381
1382 if (!size)
1383 return;
1384
1385 assert(va % 4 == 0 && size % 4 == 0);
1386
1387 while (size) {
1388 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1389 unsigned dma_flags = CP_DMA_CLEAR;
1390
1391 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1392
1393 /* Emit the clear packet. */
1394 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1395 dma_flags);
1396
1397 size -= byte_count;
1398 va += byte_count;
1399 }
1400 }
1401
1402 /* For MSAA sample positions. */
1403 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1404 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
1405 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1406 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1407 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1408
1409
1410 /* 2xMSAA
1411 * There are two locations (4, 4), (-4, -4). */
1412 const uint32_t eg_sample_locs_2x[4] = {
1413 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1414 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1415 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1416 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1417 };
1418 const unsigned eg_max_dist_2x = 4;
1419 /* 4xMSAA
1420 * There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
1421 const uint32_t eg_sample_locs_4x[4] = {
1422 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1423 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1424 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1425 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1426 };
1427 const unsigned eg_max_dist_4x = 6;
1428
1429 /* Cayman 8xMSAA */
1430 static const uint32_t cm_sample_locs_8x[] = {
1431 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1432 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1433 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1434 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1435 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1436 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1437 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1438 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1439 };
1440 static const unsigned cm_max_dist_8x = 8;
1441 /* Cayman 16xMSAA */
1442 static const uint32_t cm_sample_locs_16x[] = {
1443 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1444 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1445 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1446 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1447 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1448 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1449 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1450 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1451 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1452 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1453 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1454 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1455 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1456 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1457 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1458 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1459 };
1460 static const unsigned cm_max_dist_16x = 8;
1461
1462 unsigned radv_cayman_get_maxdist(int log_samples)
1463 {
1464 unsigned max_dist[] = {
1465 0,
1466 eg_max_dist_2x,
1467 eg_max_dist_4x,
1468 cm_max_dist_8x,
1469 cm_max_dist_16x
1470 };
1471 return max_dist[log_samples];
1472 }
1473
1474 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples)
1475 {
1476 switch (nr_samples) {
1477 default:
1478 case 1:
1479 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
1480 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
1481 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
1482 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
1483 break;
1484 case 2:
1485 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
1486 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
1487 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
1488 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
1489 break;
1490 case 4:
1491 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
1492 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
1493 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
1494 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
1495 break;
1496 case 8:
1497 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1498 radeon_emit(cs, cm_sample_locs_8x[0]);
1499 radeon_emit(cs, cm_sample_locs_8x[4]);
1500 radeon_emit(cs, 0);
1501 radeon_emit(cs, 0);
1502 radeon_emit(cs, cm_sample_locs_8x[1]);
1503 radeon_emit(cs, cm_sample_locs_8x[5]);
1504 radeon_emit(cs, 0);
1505 radeon_emit(cs, 0);
1506 radeon_emit(cs, cm_sample_locs_8x[2]);
1507 radeon_emit(cs, cm_sample_locs_8x[6]);
1508 radeon_emit(cs, 0);
1509 radeon_emit(cs, 0);
1510 radeon_emit(cs, cm_sample_locs_8x[3]);
1511 radeon_emit(cs, cm_sample_locs_8x[7]);
1512 break;
1513 case 16:
1514 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
1515 radeon_emit(cs, cm_sample_locs_16x[0]);
1516 radeon_emit(cs, cm_sample_locs_16x[4]);
1517 radeon_emit(cs, cm_sample_locs_16x[8]);
1518 radeon_emit(cs, cm_sample_locs_16x[12]);
1519 radeon_emit(cs, cm_sample_locs_16x[1]);
1520 radeon_emit(cs, cm_sample_locs_16x[5]);
1521 radeon_emit(cs, cm_sample_locs_16x[9]);
1522 radeon_emit(cs, cm_sample_locs_16x[13]);
1523 radeon_emit(cs, cm_sample_locs_16x[2]);
1524 radeon_emit(cs, cm_sample_locs_16x[6]);
1525 radeon_emit(cs, cm_sample_locs_16x[10]);
1526 radeon_emit(cs, cm_sample_locs_16x[14]);
1527 radeon_emit(cs, cm_sample_locs_16x[3]);
1528 radeon_emit(cs, cm_sample_locs_16x[7]);
1529 radeon_emit(cs, cm_sample_locs_16x[11]);
1530 radeon_emit(cs, cm_sample_locs_16x[15]);
1531 break;
1532 }
1533 }
1534
1535 static void radv_cayman_get_sample_position(struct radv_device *device,
1536 unsigned sample_count,
1537 unsigned sample_index, float *out_value)
1538 {
1539 int offset, index;
1540 struct {
1541 int idx:4;
1542 } val;
1543 switch (sample_count) {
1544 case 1:
1545 default:
1546 out_value[0] = out_value[1] = 0.5;
1547 break;
1548 case 2:
1549 offset = 4 * (sample_index * 2);
1550 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1551 out_value[0] = (float)(val.idx + 8) / 16.0f;
1552 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1553 out_value[1] = (float)(val.idx + 8) / 16.0f;
1554 break;
1555 case 4:
1556 offset = 4 * (sample_index * 2);
1557 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1558 out_value[0] = (float)(val.idx + 8) / 16.0f;
1559 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1560 out_value[1] = (float)(val.idx + 8) / 16.0f;
1561 break;
1562 case 8:
1563 offset = 4 * (sample_index % 4 * 2);
1564 index = (sample_index / 4) * 4;
1565 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1566 out_value[0] = (float)(val.idx + 8) / 16.0f;
1567 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1568 out_value[1] = (float)(val.idx + 8) / 16.0f;
1569 break;
1570 case 16:
1571 offset = 4 * (sample_index % 4 * 2);
1572 index = (sample_index / 4) * 4;
1573 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1574 out_value[0] = (float)(val.idx + 8) / 16.0f;
1575 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1576 out_value[1] = (float)(val.idx + 8) / 16.0f;
1577 break;
1578 }
1579 }
1580
1581 void radv_device_init_msaa(struct radv_device *device)
1582 {
1583 int i;
1584 radv_cayman_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1585
1586 for (i = 0; i < 2; i++)
1587 radv_cayman_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1588 for (i = 0; i < 4; i++)
1589 radv_cayman_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1590 for (i = 0; i < 8; i++)
1591 radv_cayman_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1592 for (i = 0; i < 16; i++)
1593 radv_cayman_get_sample_position(device, 16, i, device->sample_locations_16x[i]);
1594 }