projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: Implement binning on GFX9.
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for SI */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "gfx9d.h"
35 #include "radv_util.h"
36 #include "main/macros.h"
37
38 static void
39 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
40 struct radeon_winsys_cs *cs,
41 unsigned raster_config,
42 unsigned raster_config_1)
43 {
44 unsigned sh_per_se = MAX2(physical_device->rad_info.max_sh_per_se, 1);
45 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
46 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
47 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
48 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
49 unsigned rb_per_se = num_rb / num_se;
50 unsigned se_mask[4];
51 unsigned se;
52
53 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
54 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
55 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
56 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
57
58 assert(num_se == 1 || num_se == 2 || num_se == 4);
59 assert(sh_per_se == 1 || sh_per_se == 2);
60 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
61
62 /* XXX: I can't figure out what the *_XSEL and *_YSEL
63 * fields are for, so I'm leaving them as their default
64 * values. */
65
66 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
67 (!se_mask[2] && !se_mask[3]))) {
68 raster_config_1 &= C_028354_SE_PAIR_MAP;
69
70 if (!se_mask[0] && !se_mask[1]) {
71 raster_config_1 |=
72 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
73 } else {
74 raster_config_1 |=
75 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
76 }
77 }
78
79 for (se = 0; se < num_se; se++) {
80 unsigned raster_config_se = raster_config;
81 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
82 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
83 int idx = (se / 2) * 2;
84
85 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
86 raster_config_se &= C_028350_SE_MAP;
87
88 if (!se_mask[idx]) {
89 raster_config_se |=
90 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
91 } else {
92 raster_config_se |=
93 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
94 }
95 }
96
97 pkr0_mask &= rb_mask;
98 pkr1_mask &= rb_mask;
99 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
100 raster_config_se &= C_028350_PKR_MAP;
101
102 if (!pkr0_mask) {
103 raster_config_se |=
104 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
105 } else {
106 raster_config_se |=
107 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
108 }
109 }
110
111 if (rb_per_se >= 2) {
112 unsigned rb0_mask = 1 << (se * rb_per_se);
113 unsigned rb1_mask = rb0_mask << 1;
114
115 rb0_mask &= rb_mask;
116 rb1_mask &= rb_mask;
117 if (!rb0_mask || !rb1_mask) {
118 raster_config_se &= C_028350_RB_MAP_PKR0;
119
120 if (!rb0_mask) {
121 raster_config_se |=
122 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
123 } else {
124 raster_config_se |=
125 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
126 }
127 }
128
129 if (rb_per_se > 2) {
130 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
131 rb1_mask = rb0_mask << 1;
132 rb0_mask &= rb_mask;
133 rb1_mask &= rb_mask;
134 if (!rb0_mask || !rb1_mask) {
135 raster_config_se &= C_028350_RB_MAP_PKR1;
136
137 if (!rb0_mask) {
138 raster_config_se |=
139 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
140 } else {
141 raster_config_se |=
142 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
143 }
144 }
145 }
146 }
147
148 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
149 if (physical_device->rad_info.chip_class < CIK)
150 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
151 S_00802C_SE_INDEX(se) |
152 S_00802C_SH_BROADCAST_WRITES(1) |
153 S_00802C_INSTANCE_BROADCAST_WRITES(1));
154 else
155 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
156 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
157 S_030800_INSTANCE_BROADCAST_WRITES(1));
158 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
159 if (physical_device->rad_info.chip_class >= CIK)
160 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
161 }
162
163 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
164 if (physical_device->rad_info.chip_class < CIK)
165 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
166 S_00802C_SE_BROADCAST_WRITES(1) |
167 S_00802C_SH_BROADCAST_WRITES(1) |
168 S_00802C_INSTANCE_BROADCAST_WRITES(1));
169 else
170 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
171 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
172 S_030800_INSTANCE_BROADCAST_WRITES(1));
173 }
174
175 static void
176 si_emit_compute(struct radv_physical_device *physical_device,
177 struct radeon_winsys_cs *cs)
178 {
179 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
180 radeon_emit(cs, 0);
181 radeon_emit(cs, 0);
182 radeon_emit(cs, 0);
183
184 radeon_set_sh_reg_seq(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
185 S_00B854_WAVES_PER_SH(0x3));
186 radeon_emit(cs, 0);
187 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
188 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
189 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
190
191 if (physical_device->rad_info.chip_class >= CIK) {
192 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
193 radeon_set_sh_reg_seq(cs,
194 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
195 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
196 S_00B864_SH1_CU_EN(0xffff));
197 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
198 S_00B868_SH1_CU_EN(0xffff));
199 }
200
201 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
202 * and is now per pipe, so it should be handled in the
203 * kernel if we want to use something other than the default value,
204 * which is now 0x22f.
205 */
206 if (physical_device->rad_info.chip_class <= SI) {
207 /* XXX: This should be:
208 * (number of compute units) * 4 * (waves per simd) - 1 */
209
210 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
211 0x190 /* Default value */);
212 }
213 }
214
215 void
216 si_init_compute(struct radv_cmd_buffer *cmd_buffer)
217 {
218 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
219 si_emit_compute(physical_device, cmd_buffer->cs);
220 }
221
222 /* 12.4 fixed-point */
223 static unsigned radv_pack_float_12p4(float x)
224 {
225 return x <= 0 ? 0 :
226 x >= 4096 ? 0xffff : x * 16;
227 }
228
229 static void
230 si_set_raster_config(struct radv_physical_device *physical_device,
231 struct radeon_winsys_cs *cs)
232 {
233 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
234 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
235 unsigned raster_config, raster_config_1;
236
237 switch (physical_device->rad_info.family) {
238 case CHIP_TAHITI:
239 case CHIP_PITCAIRN:
240 raster_config = 0x2a00126a;
241 raster_config_1 = 0x00000000;
242 break;
243 case CHIP_VERDE:
244 raster_config = 0x0000124a;
245 raster_config_1 = 0x00000000;
246 break;
247 case CHIP_OLAND:
248 raster_config = 0x00000082;
249 raster_config_1 = 0x00000000;
250 break;
251 case CHIP_HAINAN:
252 raster_config = 0x00000000;
253 raster_config_1 = 0x00000000;
254 break;
255 case CHIP_BONAIRE:
256 raster_config = 0x16000012;
257 raster_config_1 = 0x00000000;
258 break;
259 case CHIP_HAWAII:
260 raster_config = 0x3a00161a;
261 raster_config_1 = 0x0000002e;
262 break;
263 case CHIP_FIJI:
264 if (physical_device->rad_info.cik_macrotile_mode_array[0] == 0x000000e8) {
265 /* old kernels with old tiling config */
266 raster_config = 0x16000012;
267 raster_config_1 = 0x0000002a;
268 } else {
269 raster_config = 0x3a00161a;
270 raster_config_1 = 0x0000002e;
271 }
272 break;
273 case CHIP_POLARIS10:
274 raster_config = 0x16000012;
275 raster_config_1 = 0x0000002a;
276 break;
277 case CHIP_POLARIS11:
278 case CHIP_POLARIS12:
279 raster_config = 0x16000012;
280 raster_config_1 = 0x00000000;
281 break;
282 case CHIP_TONGA:
283 raster_config = 0x16000012;
284 raster_config_1 = 0x0000002a;
285 break;
286 case CHIP_ICELAND:
287 if (num_rb == 1)
288 raster_config = 0x00000000;
289 else
290 raster_config = 0x00000002;
291 raster_config_1 = 0x00000000;
292 break;
293 case CHIP_CARRIZO:
294 raster_config = 0x00000002;
295 raster_config_1 = 0x00000000;
296 break;
297 case CHIP_KAVERI:
298 /* KV should be 0x00000002, but that causes problems with radeon */
299 raster_config = 0x00000000; /* 0x00000002 */
300 raster_config_1 = 0x00000000;
301 break;
302 case CHIP_KABINI:
303 case CHIP_MULLINS:
304 case CHIP_STONEY:
305 raster_config = 0x00000000;
306 raster_config_1 = 0x00000000;
307 break;
308 default:
309 fprintf(stderr,
310 "radv: Unknown GPU, using 0 for raster_config\n");
311 raster_config = 0x00000000;
312 raster_config_1 = 0x00000000;
313 break;
314 }
315
316 /* Always use the default config when all backends are enabled
317 * (or when we failed to determine the enabled backends).
318 */
319 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
320 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
321 raster_config);
322 if (physical_device->rad_info.chip_class >= CIK)
323 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
324 raster_config_1);
325 } else {
326 si_write_harvested_raster_configs(physical_device, cs,
327 raster_config,
328 raster_config_1);
329 }
330 }
331
332 static void
333 si_emit_config(struct radv_physical_device *physical_device,
334 struct radeon_winsys_cs *cs)
335 {
336 int i;
337
338 /* Only SI can disable CLEAR_STATE for now. */
339 assert(physical_device->has_clear_state ||
340 physical_device->rad_info.chip_class == SI);
341
342 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
343 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
344 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
345
346 if (physical_device->has_clear_state) {
347 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
348 radeon_emit(cs, 0);
349 }
350
351 if (physical_device->rad_info.chip_class <= VI)
352 si_set_raster_config(physical_device, cs);
353
354 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
355 if (!physical_device->has_clear_state)
356 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
357
358 /* FIXME calculate these values somehow ??? */
359 if (physical_device->rad_info.chip_class <= VI) {
360 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
361 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
362 }
363
364 if (!physical_device->has_clear_state) {
365 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
366 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
367 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
368 }
369
370 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
371 if (!physical_device->has_clear_state)
372 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
373 if (physical_device->rad_info.chip_class < CIK)
374 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
375 S_008A14_CLIP_VTX_REORDER_ENA(1));
376
377 radeon_set_context_reg(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
378 radeon_set_context_reg(cs, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
379
380 if (!physical_device->has_clear_state)
381 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
382
383 /* CLEAR_STATE doesn't clear these correctly on certain generations.
384 * I don't know why. Deduced by trial and error.
385 */
386 if (physical_device->rad_info.chip_class <= CIK) {
387 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
388 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
389 S_028204_WINDOW_OFFSET_DISABLE(1));
390 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
391 S_028240_WINDOW_OFFSET_DISABLE(1));
392 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
393 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
394 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
395 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
396 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
397 }
398
399 if (!physical_device->has_clear_state) {
400 for (i = 0; i < 16; i++) {
401 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
402 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
403 }
404 }
405
406 if (!physical_device->has_clear_state) {
407 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
408 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
409 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
410 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
411 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
412 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
413 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
414 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
415 }
416
417 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
418 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
419 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
420
421 if (physical_device->rad_info.chip_class >= GFX9) {
422 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
423 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
424 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
425 } else {
426 /* These registers, when written, also overwrite the
427 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
428 * them. It would be an issue if there was another UMD
429 * changing them.
430 */
431 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
432 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
433 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
434 }
435
436 if (physical_device->rad_info.chip_class >= CIK) {
437 if (physical_device->rad_info.chip_class >= GFX9) {
438 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
439 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
440 } else {
441 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
442 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
443 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
444 S_00B41C_WAVE_LIMIT(0x3F));
445 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
446 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
447 /* If this is 0, Bonaire can hang even if GS isn't being used.
448 * Other chips are unaffected. These are suboptimal values,
449 * but we don't use on-chip GS.
450 */
451 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
452 S_028A44_ES_VERTS_PER_SUBGRP(64) |
453 S_028A44_GS_PRIMS_PER_SUBGRP(4));
454 }
455 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
456 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
457
458 if (physical_device->rad_info.num_good_compute_units /
459 (physical_device->rad_info.max_se * physical_device->rad_info.max_sh_per_se) <= 4) {
460 /* Too few available compute units per SH. Disallowing
461 * VS to run on CU0 could hurt us more than late VS
462 * allocation would help.
463 *
464 * LATE_ALLOC_VS = 2 is the highest safe number.
465 */
466 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
467 S_00B118_CU_EN(0xffff) | S_00B118_WAVE_LIMIT(0x3F) );
468 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
469 } else {
470 /* Set LATE_ALLOC_VS == 31. It should be less than
471 * the number of scratch waves. Limitations:
472 * - VS can't execute on CU0.
473 * - If HS writes outputs to LDS, LS can't execute on CU0.
474 */
475 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
476 S_00B118_CU_EN(0xfffe) | S_00B118_WAVE_LIMIT(0x3F));
477 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
478 }
479
480 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
481 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
482 }
483
484 if (physical_device->rad_info.chip_class >= VI) {
485 uint32_t vgt_tess_distribution;
486 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
487 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
488 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
489
490 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
491 S_028B50_ACCUM_TRI(11) |
492 S_028B50_ACCUM_QUAD(11) |
493 S_028B50_DONUT_SPLIT(16);
494
495 if (physical_device->rad_info.family == CHIP_FIJI ||
496 physical_device->rad_info.family >= CHIP_POLARIS10)
497 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
498
499 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
500 vgt_tess_distribution);
501 } else if (!physical_device->has_clear_state) {
502 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
503 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
504 }
505
506 if (physical_device->rad_info.chip_class >= GFX9) {
507 unsigned num_se = physical_device->rad_info.max_se;
508 unsigned pc_lines = 0;
509
510 switch (physical_device->rad_info.family) {
511 case CHIP_VEGA10:
512 pc_lines = 4096;
513 break;
514 case CHIP_RAVEN:
515 pc_lines = 1024;
516 break;
517 default:
518 assert(0);
519 }
520
521 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
522 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
523 S_028C48_MAX_PRIM_PER_BATCH(1023));
524 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
525 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
526 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
527 }
528
529 unsigned tmp = (unsigned)(1.0 * 8.0);
530 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
531 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
532 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
533 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
534 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
535
536 if (!physical_device->has_clear_state) {
537 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
538 S_028004_ZPASS_INCREMENT_DISABLE(1));
539 }
540
541 si_emit_compute(physical_device, cs);
542 }
543
544 void si_init_config(struct radv_cmd_buffer *cmd_buffer)
545 {
546 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
547
548 si_emit_config(physical_device, cmd_buffer->cs);
549 }
550
551 void
552 cik_create_gfx_config(struct radv_device *device)
553 {
554 struct radeon_winsys_cs *cs = device->ws->cs_create(device->ws, RING_GFX);
555 if (!cs)
556 return;
557
558 si_emit_config(device->physical_device, cs);
559
560 while (cs->cdw & 7) {
561 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
562 radeon_emit(cs, 0x80000000);
563 else
564 radeon_emit(cs, 0xffff1000);
565 }
566
567 device->gfx_init = device->ws->buffer_create(device->ws,
568 cs->cdw * 4, 4096,
569 RADEON_DOMAIN_GTT,
570 RADEON_FLAG_CPU_ACCESS|
571 RADEON_FLAG_NO_INTERPROCESS_SHARING);
572 if (!device->gfx_init)
573 goto fail;
574
575 void *map = device->ws->buffer_map(device->gfx_init);
576 if (!map) {
577 device->ws->buffer_destroy(device->gfx_init);
578 device->gfx_init = NULL;
579 goto fail;
580 }
581 memcpy(map, cs->buf, cs->cdw * 4);
582
583 device->ws->buffer_unmap(device->gfx_init);
584 device->gfx_init_size_dw = cs->cdw;
585 fail:
586 device->ws->cs_destroy(cs);
587 }
588
589 static void
590 get_viewport_xform(const VkViewport *viewport,
591 float scale[3], float translate[3])
592 {
593 float x = viewport->x;
594 float y = viewport->y;
595 float half_width = 0.5f * viewport->width;
596 float half_height = 0.5f * viewport->height;
597 double n = viewport->minDepth;
598 double f = viewport->maxDepth;
599
600 scale[0] = half_width;
601 translate[0] = half_width + x;
602 scale[1] = half_height;
603 translate[1] = half_height + y;
604
605 scale[2] = (f - n);
606 translate[2] = n;
607 }
608
609 void
610 si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
611 int count, const VkViewport *viewports)
612 {
613 int i;
614
615 assert(count);
616 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
617 first_vp * 4 * 6, count * 6);
618
619 for (i = 0; i < count; i++) {
620 float scale[3], translate[3];
621
622
623 get_viewport_xform(&viewports[i], scale, translate);
624 radeon_emit(cs, fui(scale[0]));
625 radeon_emit(cs, fui(translate[0]));
626 radeon_emit(cs, fui(scale[1]));
627 radeon_emit(cs, fui(translate[1]));
628 radeon_emit(cs, fui(scale[2]));
629 radeon_emit(cs, fui(translate[2]));
630 }
631
632 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
633 first_vp * 4 * 2, count * 2);
634 for (i = 0; i < count; i++) {
635 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
636 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
637 radeon_emit(cs, fui(zmin));
638 radeon_emit(cs, fui(zmax));
639 }
640 }
641
642 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
643 {
644 float scale[3], translate[3];
645 VkRect2D rect;
646
647 get_viewport_xform(viewport, scale, translate);
648
649 rect.offset.x = translate[0] - abs(scale[0]);
650 rect.offset.y = translate[1] - abs(scale[1]);
651 rect.extent.width = ceilf(translate[0] + abs(scale[0])) - rect.offset.x;
652 rect.extent.height = ceilf(translate[1] + abs(scale[1])) - rect.offset.y;
653
654 return rect;
655 }
656
657 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
658 VkRect2D ret;
659 ret.offset.x = MAX2(a->offset.x, b->offset.x);
660 ret.offset.y = MAX2(a->offset.y, b->offset.y);
661 ret.extent.width = MIN2(a->offset.x + a->extent.width,
662 b->offset.x + b->extent.width) - ret.offset.x;
663 ret.extent.height = MIN2(a->offset.y + a->extent.height,
664 b->offset.y + b->extent.height) - ret.offset.y;
665 return ret;
666 }
667
668 void
669 si_write_scissors(struct radeon_winsys_cs *cs, int first,
670 int count, const VkRect2D *scissors,
671 const VkViewport *viewports, bool can_use_guardband)
672 {
673 int i;
674 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
675 const float max_range = 32767.0f;
676 assert(count);
677
678 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
679 for (i = 0; i < count; i++) {
680 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
681 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
682
683 get_viewport_xform(viewports + i, scale, translate);
684 scale[0] = abs(scale[0]);
685 scale[1] = abs(scale[1]);
686
687 if (scale[0] < 0.5)
688 scale[0] = 0.5;
689 if (scale[1] < 0.5)
690 scale[1] = 0.5;
691
692 guardband_x = MIN2(guardband_x, (max_range - abs(translate[0])) / scale[0]);
693 guardband_y = MIN2(guardband_y, (max_range - abs(translate[1])) / scale[1]);
694
695 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
696 S_028250_TL_Y(scissor.offset.y) |
697 S_028250_WINDOW_OFFSET_DISABLE(1));
698 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
699 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
700 }
701 if (!can_use_guardband) {
702 guardband_x = 1.0;
703 guardband_y = 1.0;
704 }
705
706 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
707 radeon_emit(cs, fui(guardband_y));
708 radeon_emit(cs, fui(1.0));
709 radeon_emit(cs, fui(guardband_x));
710 radeon_emit(cs, fui(1.0));
711 }
712
713 static inline unsigned
714 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
715 {
716 if (num == 0)
717 return 0;
718
719 if (info->incr == 0)
720 return 0;
721
722 if (num < info->min)
723 return 0;
724
725 return 1 + ((num - info->min) / info->incr);
726 }
727
728 uint32_t
729 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
730 bool instanced_draw, bool indirect_draw,
731 uint32_t draw_vertex_count)
732 {
733 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
734 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
735 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
736 const unsigned max_primgroup_in_wave = 2;
737 /* SWITCH_ON_EOP(0) is always preferable. */
738 bool wd_switch_on_eop = false;
739 bool ia_switch_on_eop = false;
740 bool ia_switch_on_eoi = false;
741 bool partial_vs_wave = false;
742 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.partial_es_wave;
743 bool multi_instances_smaller_than_primgroup;
744
745 multi_instances_smaller_than_primgroup = indirect_draw;
746 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
747 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
748 if (num_prims < cmd_buffer->state.pipeline->graphics.primgroup_size)
749 multi_instances_smaller_than_primgroup = true;
750 }
751
752 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_switch_on_eoi;
753 partial_vs_wave = cmd_buffer->state.pipeline->graphics.partial_vs_wave;
754
755 if (chip_class >= CIK) {
756 wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.wd_switch_on_eop;
757
758 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
759 * We don't know that for indirect drawing, so treat it as
760 * always problematic. */
761 if (family == CHIP_HAWAII &&
762 (instanced_draw || indirect_draw))
763 wd_switch_on_eop = true;
764
765 /* Performance recommendation for 4 SE Gfx7-8 parts if
766 * instances are smaller than a primgroup.
767 * Assume indirect draws always use small instances.
768 * This is needed for good VS wave utilization.
769 */
770 if (chip_class <= VI &&
771 info->max_se == 4 &&
772 multi_instances_smaller_than_primgroup)
773 wd_switch_on_eop = true;
774
775 /* Required on CIK and later. */
776 if (info->max_se > 2 && !wd_switch_on_eop)
777 ia_switch_on_eoi = true;
778
779 /* Required by Hawaii and, for some special cases, by VI. */
780 if (ia_switch_on_eoi &&
781 (family == CHIP_HAWAII ||
782 (chip_class == VI &&
783 /* max primgroup in wave is always 2 - leave this for documentation */
784 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
785 partial_vs_wave = true;
786
787 /* Instancing bug on Bonaire. */
788 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
789 (instanced_draw || indirect_draw))
790 partial_vs_wave = true;
791
792 /* If the WD switch is false, the IA switch must be false too. */
793 assert(wd_switch_on_eop || !ia_switch_on_eop);
794 }
795 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
796 if (chip_class <= VI && ia_switch_on_eoi)
797 partial_es_wave = true;
798
799 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
800 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
801 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
802 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
803 */
804 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
805 bool set_vgt_flush = indirect_draw;
806 if (!set_vgt_flush && instanced_draw) {
807 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
808 if (num_prims <= 1)
809 set_vgt_flush = true;
810 }
811 if (set_vgt_flush)
812 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
813 }
814 }
815
816 return cmd_buffer->state.pipeline->graphics.base_ia_multi_vgt_param |
817 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
818 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
819 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
820 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
821 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop : 0);
822
823 }
824
825 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
826 bool predicated,
827 enum chip_class chip_class,
828 bool is_mec,
829 unsigned event, unsigned event_flags,
830 unsigned data_sel,
831 uint64_t va,
832 uint32_t old_fence,
833 uint32_t new_fence)
834 {
835 unsigned op = EVENT_TYPE(event) |
836 EVENT_INDEX(5) |
837 event_flags;
838 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
839
840 if (chip_class >= GFX9 || is_gfx8_mec) {
841 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, predicated));
842 radeon_emit(cs, op);
843 radeon_emit(cs, EOP_DATA_SEL(data_sel));
844 radeon_emit(cs, va); /* address lo */
845 radeon_emit(cs, va >> 32); /* address hi */
846 radeon_emit(cs, new_fence); /* immediate data lo */
847 radeon_emit(cs, 0); /* immediate data hi */
848 if (!is_gfx8_mec)
849 radeon_emit(cs, 0); /* unused */
850 } else {
851 if (chip_class == CIK ||
852 chip_class == VI) {
853 /* Two EOP events are required to make all engines go idle
854 * (and optional cache flushes executed) before the timestamp
855 * is written.
856 */
857 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated));
858 radeon_emit(cs, op);
859 radeon_emit(cs, va);
860 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
861 radeon_emit(cs, old_fence); /* immediate data */
862 radeon_emit(cs, 0); /* unused */
863 }
864
865 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated));
866 radeon_emit(cs, op);
867 radeon_emit(cs, va);
868 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
869 radeon_emit(cs, new_fence); /* immediate data */
870 radeon_emit(cs, 0); /* unused */
871 }
872 }
873
874 void
875 si_emit_wait_fence(struct radeon_winsys_cs *cs,
876 bool predicated,
877 uint64_t va, uint32_t ref,
878 uint32_t mask)
879 {
880 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, predicated));
881 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
882 radeon_emit(cs, va);
883 radeon_emit(cs, va >> 32);
884 radeon_emit(cs, ref); /* reference value */
885 radeon_emit(cs, mask); /* mask */
886 radeon_emit(cs, 4); /* poll interval */
887 }
888
889 static void
890 si_emit_acquire_mem(struct radeon_winsys_cs *cs,
891 bool is_mec,
892 bool predicated,
893 bool is_gfx9,
894 unsigned cp_coher_cntl)
895 {
896 if (is_mec || is_gfx9) {
897 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
898 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, predicated) |
899 PKT3_SHADER_TYPE_S(is_mec));
900 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
901 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
902 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
903 radeon_emit(cs, 0); /* CP_COHER_BASE */
904 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
905 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
906 } else {
907 /* ACQUIRE_MEM is only required on a compute ring. */
908 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, predicated));
909 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
910 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
911 radeon_emit(cs, 0); /* CP_COHER_BASE */
912 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
913 }
914 }
915
916 void
917 si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
918 bool predicated,
919 enum chip_class chip_class,
920 uint32_t *flush_cnt,
921 uint64_t flush_va,
922 bool is_mec,
923 enum radv_cmd_flush_bits flush_bits)
924 {
925 unsigned cp_coher_cntl = 0;
926 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
927 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
928
929 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
930 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
931 if (flush_bits & RADV_CMD_FLAG_INV_SMEM_L1)
932 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
933
934 if (chip_class <= VI) {
935 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
936 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
937 S_0085F0_CB0_DEST_BASE_ENA(1) |
938 S_0085F0_CB1_DEST_BASE_ENA(1) |
939 S_0085F0_CB2_DEST_BASE_ENA(1) |
940 S_0085F0_CB3_DEST_BASE_ENA(1) |
941 S_0085F0_CB4_DEST_BASE_ENA(1) |
942 S_0085F0_CB5_DEST_BASE_ENA(1) |
943 S_0085F0_CB6_DEST_BASE_ENA(1) |
944 S_0085F0_CB7_DEST_BASE_ENA(1);
945
946 /* Necessary for DCC */
947 if (chip_class >= VI) {
948 si_cs_emit_write_event_eop(cs,
949 predicated,
950 chip_class,
951 is_mec,
952 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
953 0, 0, 0, 0, 0);
954 }
955 }
956 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
957 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
958 S_0085F0_DB_DEST_BASE_ENA(1);
959 }
960 }
961
962 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
963 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
964 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
965 }
966
967 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
968 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
969 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
970 }
971
972 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
973 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
974 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
975 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
976 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
977 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
978 }
979
980 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
981 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
982 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
983 }
984
985 if (chip_class >= GFX9 && flush_cb_db) {
986 unsigned cb_db_event, tc_flags;
987
988 #if 0
989 /* This breaks a bunch of:
990 dEQP-VK.renderpass.dedicated_allocation.formats.d32_sfloat_s8_uint.input*.
991 use the big hammer always.
992 */
993 /* Set the CB/DB flush event. */
994 switch (flush_cb_db) {
995 case RADV_CMD_FLAG_FLUSH_AND_INV_CB:
996 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
997 break;
998 case RADV_CMD_FLAG_FLUSH_AND_INV_DB:
999 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1000 break;
1001 default:
1002 /* both CB & DB */
1003 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1004 }
1005 #else
1006 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1007 #endif
1008 /* TC | TC_WB = invalidate L2 data
1009 * TC_MD | TC_WB = invalidate L2 metadata
1010 * TC | TC_WB | TC_MD = invalidate L2 data & metadata
1011 *
1012 * The metadata cache must always be invalidated for coherency
1013 * between CB/DB and shaders. (metadata = HTILE, CMASK, DCC)
1014 *
1015 * TC must be invalidated on GFX9 only if the CB/DB surface is
1016 * not pipe-aligned. If the surface is RB-aligned, it might not
1017 * strictly be pipe-aligned since RB alignment takes precendence.
1018 */
1019 tc_flags = EVENT_TC_WB_ACTION_ENA |
1020 EVENT_TC_MD_ACTION_ENA;
1021
1022 /* Ideally flush TC together with CB/DB. */
1023 if (flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) {
1024 tc_flags |= EVENT_TC_ACTION_ENA |
1025 EVENT_TCL1_ACTION_ENA;
1026
1027 /* Clear the flags. */
1028 flush_bits &= ~(RADV_CMD_FLAG_INV_GLOBAL_L2 |
1029 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 |
1030 RADV_CMD_FLAG_INV_VMEM_L1);
1031 }
1032 assert(flush_cnt);
1033 uint32_t old_fence = (*flush_cnt)++;
1034
1035 si_cs_emit_write_event_eop(cs, predicated, chip_class, false, cb_db_event, tc_flags, 1,
1036 flush_va, old_fence, *flush_cnt);
1037 si_emit_wait_fence(cs, predicated, flush_va, *flush_cnt, 0xffffffff);
1038 }
1039
1040 /* VGT state sync */
1041 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1042 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
1043 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1044 }
1045
1046 /* Make sure ME is idle (it executes most packets) before continuing.
1047 * This prevents read-after-write hazards between PFP and ME.
1048 */
1049 if ((cp_coher_cntl ||
1050 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1051 RADV_CMD_FLAG_INV_VMEM_L1 |
1052 RADV_CMD_FLAG_INV_GLOBAL_L2 |
1053 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) &&
1054 !is_mec) {
1055 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, predicated));
1056 radeon_emit(cs, 0);
1057 }
1058
1059 if ((flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) ||
1060 (chip_class <= CIK && (flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) {
1061 si_emit_acquire_mem(cs, is_mec, predicated, chip_class >= GFX9,
1062 cp_coher_cntl |
1063 S_0085F0_TC_ACTION_ENA(1) |
1064 S_0085F0_TCL1_ACTION_ENA(1) |
1065 S_0301F0_TC_WB_ACTION_ENA(chip_class >= VI));
1066 cp_coher_cntl = 0;
1067 } else {
1068 if(flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2) {
1069 /* WB = write-back
1070 * NC = apply to non-coherent MTYPEs
1071 * (i.e. MTYPE <= 1, which is what we use everywhere)
1072 *
1073 * WB doesn't work without NC.
1074 */
1075 si_emit_acquire_mem(cs, is_mec, predicated,
1076 chip_class >= GFX9,
1077 cp_coher_cntl |
1078 S_0301F0_TC_WB_ACTION_ENA(1) |
1079 S_0301F0_TC_NC_ACTION_ENA(1));
1080 cp_coher_cntl = 0;
1081 }
1082 if (flush_bits & RADV_CMD_FLAG_INV_VMEM_L1) {
1083 si_emit_acquire_mem(cs, is_mec,
1084 predicated, chip_class >= GFX9,
1085 cp_coher_cntl |
1086 S_0085F0_TCL1_ACTION_ENA(1));
1087 cp_coher_cntl = 0;
1088 }
1089 }
1090
1091 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1092 * Therefore, it should be last. Done in PFP.
1093 */
1094 if (cp_coher_cntl)
1095 si_emit_acquire_mem(cs, is_mec, predicated, chip_class >= GFX9, cp_coher_cntl);
1096 }
1097
1098 void
1099 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
1100 {
1101 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1102
1103 if (is_compute)
1104 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1105 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1106 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1107 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1108 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1109 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1110 RADV_CMD_FLAG_VGT_FLUSH);
1111
1112 if (!cmd_buffer->state.flush_bits)
1113 return;
1114
1115 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
1116 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1117
1118 uint32_t *ptr = NULL;
1119 uint64_t va = 0;
1120 if (chip_class == GFX9) {
1121 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) + cmd_buffer->gfx9_fence_offset;
1122 ptr = &cmd_buffer->gfx9_fence_idx;
1123 }
1124 si_cs_emit_cache_flush(cmd_buffer->cs,
1125 cmd_buffer->state.predicating,
1126 cmd_buffer->device->physical_device->rad_info.chip_class,
1127 ptr, va,
1128 radv_cmd_buffer_uses_mec(cmd_buffer),
1129 cmd_buffer->state.flush_bits);
1130
1131
1132 if (unlikely(cmd_buffer->device->trace_bo))
1133 radv_cmd_buffer_trace_emit(cmd_buffer);
1134
1135 cmd_buffer->state.flush_bits = 0;
1136 }
1137
1138 /* sets the CP predication state using a boolean stored at va */
1139 void
1140 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
1141 {
1142 uint32_t op = 0;
1143
1144 if (va)
1145 op = PRED_OP(PREDICATION_OP_BOOL64) | PREDICATION_DRAW_VISIBLE;
1146 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1147 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1148 radeon_emit(cmd_buffer->cs, op);
1149 radeon_emit(cmd_buffer->cs, va);
1150 radeon_emit(cmd_buffer->cs, va >> 32);
1151 } else {
1152 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1153 radeon_emit(cmd_buffer->cs, va);
1154 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1155 }
1156 }
1157
1158 /* Set this if you want the 3D engine to wait until CP DMA is done.
1159 * It should be set on the last CP DMA packet. */
1160 #define CP_DMA_SYNC (1 << 0)
1161
1162 /* Set this if the source data was used as a destination in a previous CP DMA
1163 * packet. It's for preventing a read-after-write (RAW) hazard between two
1164 * CP DMA packets. */
1165 #define CP_DMA_RAW_WAIT (1 << 1)
1166 #define CP_DMA_USE_L2 (1 << 2)
1167 #define CP_DMA_CLEAR (1 << 3)
1168
1169 /* Alignment for optimal performance. */
1170 #define SI_CPDMA_ALIGNMENT 32
1171
1172 /* The max number of bytes that can be copied per packet. */
1173 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1174 {
1175 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1176 S_414_BYTE_COUNT_GFX9(~0u) :
1177 S_414_BYTE_COUNT_GFX6(~0u);
1178
1179 /* make it aligned for optimal performance */
1180 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1181 }
1182
1183 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1184 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1185 * clear value.
1186 */
1187 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1188 uint64_t dst_va, uint64_t src_va,
1189 unsigned size, unsigned flags)
1190 {
1191 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1192 uint32_t header = 0, command = 0;
1193
1194 assert(size);
1195 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1196
1197 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1198 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1199 command |= S_414_BYTE_COUNT_GFX9(size);
1200 else
1201 command |= S_414_BYTE_COUNT_GFX6(size);
1202
1203 /* Sync flags. */
1204 if (flags & CP_DMA_SYNC)
1205 header |= S_411_CP_SYNC(1);
1206 else {
1207 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1208 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1209 else
1210 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1211 }
1212
1213 if (flags & CP_DMA_RAW_WAIT)
1214 command |= S_414_RAW_WAIT(1);
1215
1216 /* Src and dst flags. */
1217 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1218 !(flags & CP_DMA_CLEAR) &&
1219 src_va == dst_va)
1220 header |= S_411_DSL_SEL(V_411_NOWHERE); /* prefetch only */
1221 else if (flags & CP_DMA_USE_L2)
1222 header |= S_411_DSL_SEL(V_411_DST_ADDR_TC_L2);
1223
1224 if (flags & CP_DMA_CLEAR)
1225 header |= S_411_SRC_SEL(V_411_DATA);
1226 else if (flags & CP_DMA_USE_L2)
1227 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1228
1229 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1230 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1231 radeon_emit(cs, header);
1232 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1233 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1234 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1235 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1236 radeon_emit(cs, command);
1237 } else {
1238 assert(!(flags & CP_DMA_USE_L2));
1239 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1240 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1241 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1242 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1243 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1244 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1245 radeon_emit(cs, command);
1246 }
1247
1248 /* CP DMA is executed in ME, but index buffers are read by PFP.
1249 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1250 * indices. If we wanted to execute CP DMA in PFP, this packet
1251 * should precede it.
1252 */
1253 if ((flags & CP_DMA_SYNC) && cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1254 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1255 radeon_emit(cs, 0);
1256 }
1257
1258 if (unlikely(cmd_buffer->device->trace_bo))
1259 radv_cmd_buffer_trace_emit(cmd_buffer);
1260 }
1261
1262 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1263 unsigned size)
1264 {
1265 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1266 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1267
1268 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1269 aligned_size, CP_DMA_USE_L2);
1270 }
1271
1272 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1273 uint64_t remaining_size, unsigned *flags)
1274 {
1275
1276 /* Flush the caches for the first copy only.
1277 * Also wait for the previous CP DMA operations.
1278 */
1279 if (cmd_buffer->state.flush_bits) {
1280 si_emit_cache_flush(cmd_buffer);
1281 *flags |= CP_DMA_RAW_WAIT;
1282 }
1283
1284 /* Do the synchronization after the last dma, so that all data
1285 * is written to memory.
1286 */
1287 if (byte_count == remaining_size)
1288 *flags |= CP_DMA_SYNC;
1289 }
1290
1291 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1292 {
1293 uint64_t va;
1294 uint32_t offset;
1295 unsigned dma_flags = 0;
1296 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1297 void *ptr;
1298
1299 assert(size < SI_CPDMA_ALIGNMENT);
1300
1301 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1302
1303 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1304 va += offset;
1305
1306 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1307
1308 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1309 dma_flags);
1310 }
1311
1312 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1313 uint64_t src_va, uint64_t dest_va,
1314 uint64_t size)
1315 {
1316 uint64_t main_src_va, main_dest_va;
1317 uint64_t skipped_size = 0, realign_size = 0;
1318
1319
1320 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1321 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1322 /* If the size is not aligned, we must add a dummy copy at the end
1323 * just to align the internal counter. Otherwise, the DMA engine
1324 * would slow down by an order of magnitude for following copies.
1325 */
1326 if (size % SI_CPDMA_ALIGNMENT)
1327 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1328
1329 /* If the copy begins unaligned, we must start copying from the next
1330 * aligned block and the skipped part should be copied after everything
1331 * else has been copied. Only the src alignment matters, not dst.
1332 */
1333 if (src_va % SI_CPDMA_ALIGNMENT) {
1334 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1335 /* The main part will be skipped if the size is too small. */
1336 skipped_size = MIN2(skipped_size, size);
1337 size -= skipped_size;
1338 }
1339 }
1340 main_src_va = src_va + skipped_size;
1341 main_dest_va = dest_va + skipped_size;
1342
1343 while (size) {
1344 unsigned dma_flags = 0;
1345 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1346
1347 si_cp_dma_prepare(cmd_buffer, byte_count,
1348 size + skipped_size + realign_size,
1349 &dma_flags);
1350
1351 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1352 byte_count, dma_flags);
1353
1354 size -= byte_count;
1355 main_src_va += byte_count;
1356 main_dest_va += byte_count;
1357 }
1358
1359 if (skipped_size) {
1360 unsigned dma_flags = 0;
1361
1362 si_cp_dma_prepare(cmd_buffer, skipped_size,
1363 size + skipped_size + realign_size,
1364 &dma_flags);
1365
1366 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1367 skipped_size, dma_flags);
1368 }
1369 if (realign_size)
1370 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1371 }
1372
1373 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1374 uint64_t size, unsigned value)
1375 {
1376
1377 if (!size)
1378 return;
1379
1380 assert(va % 4 == 0 && size % 4 == 0);
1381
1382 while (size) {
1383 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1384 unsigned dma_flags = CP_DMA_CLEAR;
1385
1386 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1387
1388 /* Emit the clear packet. */
1389 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1390 dma_flags);
1391
1392 size -= byte_count;
1393 va += byte_count;
1394 }
1395 }
1396
1397 /* For MSAA sample positions. */
1398 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1399 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
1400 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1401 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1402 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1403
1404
1405 /* 2xMSAA
1406 * There are two locations (4, 4), (-4, -4). */
1407 const uint32_t eg_sample_locs_2x[4] = {
1408 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1409 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1410 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1411 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1412 };
1413 const unsigned eg_max_dist_2x = 4;
1414 /* 4xMSAA
1415 * There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
1416 const uint32_t eg_sample_locs_4x[4] = {
1417 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1418 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1419 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1420 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1421 };
1422 const unsigned eg_max_dist_4x = 6;
1423
1424 /* Cayman 8xMSAA */
1425 static const uint32_t cm_sample_locs_8x[] = {
1426 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1427 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1428 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1429 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1430 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1431 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1432 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1433 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1434 };
1435 static const unsigned cm_max_dist_8x = 8;
1436 /* Cayman 16xMSAA */
1437 static const uint32_t cm_sample_locs_16x[] = {
1438 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1439 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1440 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1441 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1442 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1443 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1444 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1445 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1446 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1447 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1448 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1449 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1450 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1451 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1452 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1453 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1454 };
1455 static const unsigned cm_max_dist_16x = 8;
1456
1457 unsigned radv_cayman_get_maxdist(int log_samples)
1458 {
1459 unsigned max_dist[] = {
1460 0,
1461 eg_max_dist_2x,
1462 eg_max_dist_4x,
1463 cm_max_dist_8x,
1464 cm_max_dist_16x
1465 };
1466 return max_dist[log_samples];
1467 }
1468
1469 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples)
1470 {
1471 switch (nr_samples) {
1472 default:
1473 case 1:
1474 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
1475 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
1476 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
1477 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
1478 break;
1479 case 2:
1480 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
1481 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
1482 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
1483 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
1484 break;
1485 case 4:
1486 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
1487 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
1488 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
1489 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
1490 break;
1491 case 8:
1492 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1493 radeon_emit(cs, cm_sample_locs_8x[0]);
1494 radeon_emit(cs, cm_sample_locs_8x[4]);
1495 radeon_emit(cs, 0);
1496 radeon_emit(cs, 0);
1497 radeon_emit(cs, cm_sample_locs_8x[1]);
1498 radeon_emit(cs, cm_sample_locs_8x[5]);
1499 radeon_emit(cs, 0);
1500 radeon_emit(cs, 0);
1501 radeon_emit(cs, cm_sample_locs_8x[2]);
1502 radeon_emit(cs, cm_sample_locs_8x[6]);
1503 radeon_emit(cs, 0);
1504 radeon_emit(cs, 0);
1505 radeon_emit(cs, cm_sample_locs_8x[3]);
1506 radeon_emit(cs, cm_sample_locs_8x[7]);
1507 break;
1508 case 16:
1509 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
1510 radeon_emit(cs, cm_sample_locs_16x[0]);
1511 radeon_emit(cs, cm_sample_locs_16x[4]);
1512 radeon_emit(cs, cm_sample_locs_16x[8]);
1513 radeon_emit(cs, cm_sample_locs_16x[12]);
1514 radeon_emit(cs, cm_sample_locs_16x[1]);
1515 radeon_emit(cs, cm_sample_locs_16x[5]);
1516 radeon_emit(cs, cm_sample_locs_16x[9]);
1517 radeon_emit(cs, cm_sample_locs_16x[13]);
1518 radeon_emit(cs, cm_sample_locs_16x[2]);
1519 radeon_emit(cs, cm_sample_locs_16x[6]);
1520 radeon_emit(cs, cm_sample_locs_16x[10]);
1521 radeon_emit(cs, cm_sample_locs_16x[14]);
1522 radeon_emit(cs, cm_sample_locs_16x[3]);
1523 radeon_emit(cs, cm_sample_locs_16x[7]);
1524 radeon_emit(cs, cm_sample_locs_16x[11]);
1525 radeon_emit(cs, cm_sample_locs_16x[15]);
1526 break;
1527 }
1528 }
1529
1530 static void radv_cayman_get_sample_position(struct radv_device *device,
1531 unsigned sample_count,
1532 unsigned sample_index, float *out_value)
1533 {
1534 int offset, index;
1535 struct {
1536 int idx:4;
1537 } val;
1538 switch (sample_count) {
1539 case 1:
1540 default:
1541 out_value[0] = out_value[1] = 0.5;
1542 break;
1543 case 2:
1544 offset = 4 * (sample_index * 2);
1545 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1546 out_value[0] = (float)(val.idx + 8) / 16.0f;
1547 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1548 out_value[1] = (float)(val.idx + 8) / 16.0f;
1549 break;
1550 case 4:
1551 offset = 4 * (sample_index * 2);
1552 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1553 out_value[0] = (float)(val.idx + 8) / 16.0f;
1554 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1555 out_value[1] = (float)(val.idx + 8) / 16.0f;
1556 break;
1557 case 8:
1558 offset = 4 * (sample_index % 4 * 2);
1559 index = (sample_index / 4) * 4;
1560 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1561 out_value[0] = (float)(val.idx + 8) / 16.0f;
1562 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1563 out_value[1] = (float)(val.idx + 8) / 16.0f;
1564 break;
1565 case 16:
1566 offset = 4 * (sample_index % 4 * 2);
1567 index = (sample_index / 4) * 4;
1568 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1569 out_value[0] = (float)(val.idx + 8) / 16.0f;
1570 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1571 out_value[1] = (float)(val.idx + 8) / 16.0f;
1572 break;
1573 }
1574 }
1575
1576 void radv_device_init_msaa(struct radv_device *device)
1577 {
1578 int i;
1579 radv_cayman_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1580
1581 for (i = 0; i < 2; i++)
1582 radv_cayman_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1583 for (i = 0; i < 4; i++)
1584 radv_cayman_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1585 for (i = 0; i < 8; i++)
1586 radv_cayman_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1587 for (i = 0; i < 16; i++)
1588 radv_cayman_get_sample_position(device, 16, i, device->sample_locations_16x[i]);
1589 }