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radv: factor out si_emit_wait_fence code.
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for SI */
29
30 #include "radv_private.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "radv_util.h"
34 #include "main/macros.h"
35
36 #define SI_GS_PER_ES 128
37
38 static void
39 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
40 struct radeon_winsys_cs *cs,
41 unsigned raster_config,
42 unsigned raster_config_1)
43 {
44 unsigned sh_per_se = MAX2(physical_device->rad_info.max_sh_per_se, 1);
45 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
46 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
47 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
48 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
49 unsigned rb_per_se = num_rb / num_se;
50 unsigned se_mask[4];
51 unsigned se;
52
53 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
54 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
55 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
56 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
57
58 assert(num_se == 1 || num_se == 2 || num_se == 4);
59 assert(sh_per_se == 1 || sh_per_se == 2);
60 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
61
62 /* XXX: I can't figure out what the *_XSEL and *_YSEL
63 * fields are for, so I'm leaving them as their default
64 * values. */
65
66 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
67 (!se_mask[2] && !se_mask[3]))) {
68 raster_config_1 &= C_028354_SE_PAIR_MAP;
69
70 if (!se_mask[0] && !se_mask[1]) {
71 raster_config_1 |=
72 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
73 } else {
74 raster_config_1 |=
75 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
76 }
77 }
78
79 for (se = 0; se < num_se; se++) {
80 unsigned raster_config_se = raster_config;
81 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
82 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
83 int idx = (se / 2) * 2;
84
85 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
86 raster_config_se &= C_028350_SE_MAP;
87
88 if (!se_mask[idx]) {
89 raster_config_se |=
90 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
91 } else {
92 raster_config_se |=
93 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
94 }
95 }
96
97 pkr0_mask &= rb_mask;
98 pkr1_mask &= rb_mask;
99 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
100 raster_config_se &= C_028350_PKR_MAP;
101
102 if (!pkr0_mask) {
103 raster_config_se |=
104 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
105 } else {
106 raster_config_se |=
107 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
108 }
109 }
110
111 if (rb_per_se >= 2) {
112 unsigned rb0_mask = 1 << (se * rb_per_se);
113 unsigned rb1_mask = rb0_mask << 1;
114
115 rb0_mask &= rb_mask;
116 rb1_mask &= rb_mask;
117 if (!rb0_mask || !rb1_mask) {
118 raster_config_se &= C_028350_RB_MAP_PKR0;
119
120 if (!rb0_mask) {
121 raster_config_se |=
122 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
123 } else {
124 raster_config_se |=
125 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
126 }
127 }
128
129 if (rb_per_se > 2) {
130 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
131 rb1_mask = rb0_mask << 1;
132 rb0_mask &= rb_mask;
133 rb1_mask &= rb_mask;
134 if (!rb0_mask || !rb1_mask) {
135 raster_config_se &= C_028350_RB_MAP_PKR1;
136
137 if (!rb0_mask) {
138 raster_config_se |=
139 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
140 } else {
141 raster_config_se |=
142 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
143 }
144 }
145 }
146 }
147
148 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
149 if (physical_device->rad_info.chip_class < CIK)
150 radeon_set_config_reg(cs, GRBM_GFX_INDEX,
151 SE_INDEX(se) | SH_BROADCAST_WRITES |
152 INSTANCE_BROADCAST_WRITES);
153 else
154 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
155 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
156 S_030800_INSTANCE_BROADCAST_WRITES(1));
157 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
158 if (physical_device->rad_info.chip_class >= CIK)
159 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
160 }
161
162 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
163 if (physical_device->rad_info.chip_class < CIK)
164 radeon_set_config_reg(cs, GRBM_GFX_INDEX,
165 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
166 INSTANCE_BROADCAST_WRITES);
167 else
168 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
169 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
170 S_030800_INSTANCE_BROADCAST_WRITES(1));
171 }
172
173 static void
174 si_emit_compute(struct radv_physical_device *physical_device,
175 struct radeon_winsys_cs *cs)
176 {
177 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
178 radeon_emit(cs, 0);
179 radeon_emit(cs, 0);
180 radeon_emit(cs, 0);
181
182 radeon_set_sh_reg_seq(cs, R_00B854_COMPUTE_RESOURCE_LIMITS, 3);
183 radeon_emit(cs, 0);
184 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
185 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
186 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
187
188 if (physical_device->rad_info.chip_class >= CIK) {
189 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
190 radeon_set_sh_reg_seq(cs,
191 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
192 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
193 S_00B864_SH1_CU_EN(0xffff));
194 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
195 S_00B868_SH1_CU_EN(0xffff));
196 }
197
198 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
199 * and is now per pipe, so it should be handled in the
200 * kernel if we want to use something other than the default value,
201 * which is now 0x22f.
202 */
203 if (physical_device->rad_info.chip_class <= SI) {
204 /* XXX: This should be:
205 * (number of compute units) * 4 * (waves per simd) - 1 */
206
207 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
208 0x190 /* Default value */);
209 }
210 }
211
212 void
213 si_init_compute(struct radv_cmd_buffer *cmd_buffer)
214 {
215 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
216 si_emit_compute(physical_device, cmd_buffer->cs);
217 }
218
219 static void
220 si_emit_config(struct radv_physical_device *physical_device,
221 struct radeon_winsys_cs *cs)
222 {
223 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
224 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
225 unsigned raster_config, raster_config_1;
226 int i;
227
228 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
229 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
230 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
231
232 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
233 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
234
235 /* FIXME calculate these values somehow ??? */
236 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
237 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
238 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
239
240 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
241 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
242
243 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
244 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
245 if (physical_device->rad_info.chip_class < CIK)
246 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
247 S_008A14_CLIP_VTX_REORDER_ENA(1));
248
249 radeon_set_context_reg(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
250 radeon_set_context_reg(cs, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
251
252 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
253
254 for (i = 0; i < 16; i++) {
255 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
256 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
257 }
258
259 switch (physical_device->rad_info.family) {
260 case CHIP_TAHITI:
261 case CHIP_PITCAIRN:
262 raster_config = 0x2a00126a;
263 raster_config_1 = 0x00000000;
264 break;
265 case CHIP_VERDE:
266 raster_config = 0x0000124a;
267 raster_config_1 = 0x00000000;
268 break;
269 case CHIP_OLAND:
270 raster_config = 0x00000082;
271 raster_config_1 = 0x00000000;
272 break;
273 case CHIP_HAINAN:
274 raster_config = 0x00000000;
275 raster_config_1 = 0x00000000;
276 break;
277 case CHIP_BONAIRE:
278 raster_config = 0x16000012;
279 raster_config_1 = 0x00000000;
280 break;
281 case CHIP_HAWAII:
282 raster_config = 0x3a00161a;
283 raster_config_1 = 0x0000002e;
284 break;
285 case CHIP_FIJI:
286 if (physical_device->rad_info.cik_macrotile_mode_array[0] == 0x000000e8) {
287 /* old kernels with old tiling config */
288 raster_config = 0x16000012;
289 raster_config_1 = 0x0000002a;
290 } else {
291 raster_config = 0x3a00161a;
292 raster_config_1 = 0x0000002e;
293 }
294 break;
295 case CHIP_POLARIS10:
296 raster_config = 0x16000012;
297 raster_config_1 = 0x0000002a;
298 break;
299 case CHIP_POLARIS11:
300 case CHIP_POLARIS12:
301 raster_config = 0x16000012;
302 raster_config_1 = 0x00000000;
303 break;
304 case CHIP_TONGA:
305 raster_config = 0x16000012;
306 raster_config_1 = 0x0000002a;
307 break;
308 case CHIP_ICELAND:
309 if (num_rb == 1)
310 raster_config = 0x00000000;
311 else
312 raster_config = 0x00000002;
313 raster_config_1 = 0x00000000;
314 break;
315 case CHIP_CARRIZO:
316 raster_config = 0x00000002;
317 raster_config_1 = 0x00000000;
318 break;
319 case CHIP_KAVERI:
320 /* KV should be 0x00000002, but that causes problems with radeon */
321 raster_config = 0x00000000; /* 0x00000002 */
322 raster_config_1 = 0x00000000;
323 break;
324 case CHIP_KABINI:
325 case CHIP_MULLINS:
326 case CHIP_STONEY:
327 raster_config = 0x00000000;
328 raster_config_1 = 0x00000000;
329 break;
330 default:
331 fprintf(stderr,
332 "radeonsi: Unknown GPU, using 0 for raster_config\n");
333 raster_config = 0x00000000;
334 raster_config_1 = 0x00000000;
335 break;
336 }
337
338 /* Always use the default config when all backends are enabled
339 * (or when we failed to determine the enabled backends).
340 */
341 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
342 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
343 raster_config);
344 if (physical_device->rad_info.chip_class >= CIK)
345 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
346 raster_config_1);
347 } else {
348 si_write_harvested_raster_configs(physical_device, cs, raster_config, raster_config_1);
349 }
350
351 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
352 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
353 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
354 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
355 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
356 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
357 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
358
359 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
360 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
361 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
362 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
363 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
364
365 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
366 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
367 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
368 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
369 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
370 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
371
372 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
373 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
374 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
375
376 if (physical_device->rad_info.chip_class >= CIK) {
377 /* If this is 0, Bonaire can hang even if GS isn't being used.
378 * Other chips are unaffected. These are suboptimal values,
379 * but we don't use on-chip GS.
380 */
381 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
382 S_028A44_ES_VERTS_PER_SUBGRP(64) |
383 S_028A44_GS_PRIMS_PER_SUBGRP(4));
384
385 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
386 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
387 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
388 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
389
390 if (physical_device->rad_info.num_good_compute_units /
391 (physical_device->rad_info.max_se * physical_device->rad_info.max_sh_per_se) <= 4) {
392 /* Too few available compute units per SH. Disallowing
393 * VS to run on CU0 could hurt us more than late VS
394 * allocation would help.
395 *
396 * LATE_ALLOC_VS = 2 is the highest safe number.
397 */
398 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
399 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
400 } else {
401 /* Set LATE_ALLOC_VS == 31. It should be less than
402 * the number of scratch waves. Limitations:
403 * - VS can't execute on CU0.
404 * - If HS writes outputs to LDS, LS can't execute on CU0.
405 */
406 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
407 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
408 }
409
410 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
411 }
412
413 if (physical_device->rad_info.chip_class >= VI) {
414 uint32_t vgt_tess_distribution;
415 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
416 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
417 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
418 if (physical_device->rad_info.family < CHIP_POLARIS10)
419 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
420 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
421
422 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
423 S_028B50_ACCUM_TRI(11) |
424 S_028B50_ACCUM_QUAD(11) |
425 S_028B50_DONUT_SPLIT(16);
426
427 if (physical_device->rad_info.family == CHIP_FIJI ||
428 physical_device->rad_info.family >= CHIP_POLARIS10)
429 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
430
431 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
432 vgt_tess_distribution);
433 } else {
434 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
435 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
436 }
437
438 if (physical_device->rad_info.family == CHIP_STONEY)
439 radeon_set_context_reg(cs, R_028C40_PA_SC_SHADER_CONTROL, 0);
440
441 si_emit_compute(physical_device, cs);
442 }
443
444 void si_init_config(struct radv_cmd_buffer *cmd_buffer)
445 {
446 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
447
448 si_emit_config(physical_device, cmd_buffer->cs);
449 }
450
451 void
452 cik_create_gfx_config(struct radv_device *device)
453 {
454 struct radeon_winsys_cs *cs = device->ws->cs_create(device->ws, RING_GFX);
455 if (!cs)
456 return;
457
458 si_emit_config(device->physical_device, cs);
459
460 while (cs->cdw & 7) {
461 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
462 radeon_emit(cs, 0x80000000);
463 else
464 radeon_emit(cs, 0xffff1000);
465 }
466
467 device->gfx_init = device->ws->buffer_create(device->ws,
468 cs->cdw * 4, 4096,
469 RADEON_DOMAIN_GTT,
470 RADEON_FLAG_CPU_ACCESS);
471 if (!device->gfx_init)
472 goto fail;
473
474 void *map = device->ws->buffer_map(device->gfx_init);
475 if (!map) {
476 device->ws->buffer_destroy(device->gfx_init);
477 device->gfx_init = NULL;
478 goto fail;
479 }
480 memcpy(map, cs->buf, cs->cdw * 4);
481
482 device->ws->buffer_unmap(device->gfx_init);
483 device->gfx_init_size_dw = cs->cdw;
484 fail:
485 device->ws->cs_destroy(cs);
486 }
487
488 static void
489 get_viewport_xform(const VkViewport *viewport,
490 float scale[3], float translate[3])
491 {
492 float x = viewport->x;
493 float y = viewport->y;
494 float half_width = 0.5f * viewport->width;
495 float half_height = 0.5f * viewport->height;
496 double n = viewport->minDepth;
497 double f = viewport->maxDepth;
498
499 scale[0] = half_width;
500 translate[0] = half_width + x;
501 scale[1] = half_height;
502 translate[1] = half_height + y;
503
504 scale[2] = (f - n);
505 translate[2] = n;
506 }
507
508 void
509 si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
510 int count, const VkViewport *viewports)
511 {
512 int i;
513
514 assert(count);
515 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
516 first_vp * 4 * 6, count * 6);
517
518 for (i = 0; i < count; i++) {
519 float scale[3], translate[3];
520
521
522 get_viewport_xform(&viewports[i], scale, translate);
523 radeon_emit(cs, fui(scale[0]));
524 radeon_emit(cs, fui(translate[0]));
525 radeon_emit(cs, fui(scale[1]));
526 radeon_emit(cs, fui(translate[1]));
527 radeon_emit(cs, fui(scale[2]));
528 radeon_emit(cs, fui(translate[2]));
529 }
530
531 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
532 first_vp * 4 * 2, count * 2);
533 for (i = 0; i < count; i++) {
534 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
535 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
536 radeon_emit(cs, fui(zmin));
537 radeon_emit(cs, fui(zmax));
538 }
539 }
540
541 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
542 {
543 float scale[3], translate[3];
544 VkRect2D rect;
545
546 get_viewport_xform(viewport, scale, translate);
547
548 rect.offset.x = translate[0] - abs(scale[0]);
549 rect.offset.y = translate[1] - abs(scale[1]);
550 rect.extent.width = ceilf(translate[0] + abs(scale[0])) - rect.offset.x;
551 rect.extent.height = ceilf(translate[1] + abs(scale[1])) - rect.offset.y;
552
553 return rect;
554 }
555
556 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
557 VkRect2D ret;
558 ret.offset.x = MAX2(a->offset.x, b->offset.x);
559 ret.offset.y = MAX2(a->offset.y, b->offset.y);
560 ret.extent.width = MIN2(a->offset.x + a->extent.width,
561 b->offset.x + b->extent.width) - ret.offset.x;
562 ret.extent.height = MIN2(a->offset.y + a->extent.height,
563 b->offset.y + b->extent.height) - ret.offset.y;
564 return ret;
565 }
566
567 void
568 si_write_scissors(struct radeon_winsys_cs *cs, int first,
569 int count, const VkRect2D *scissors,
570 const VkViewport *viewports, bool can_use_guardband)
571 {
572 int i;
573 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
574 const float max_range = 32767.0f;
575 assert(count);
576
577 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
578 for (i = 0; i < count; i++) {
579 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
580 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
581
582 get_viewport_xform(viewports + i, scale, translate);
583 scale[0] = abs(scale[0]);
584 scale[1] = abs(scale[1]);
585
586 if (scale[0] < 0.5)
587 scale[0] = 0.5;
588 if (scale[1] < 0.5)
589 scale[1] = 0.5;
590
591 guardband_x = MIN2(guardband_x, (max_range - abs(translate[0])) / scale[0]);
592 guardband_y = MIN2(guardband_y, (max_range - abs(translate[1])) / scale[1]);
593
594 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
595 S_028250_TL_Y(scissor.offset.y) |
596 S_028250_WINDOW_OFFSET_DISABLE(1));
597 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
598 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
599 }
600 if (!can_use_guardband) {
601 guardband_x = 1.0;
602 guardband_y = 1.0;
603 }
604
605 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
606 radeon_emit(cs, fui(guardband_y));
607 radeon_emit(cs, fui(1.0));
608 radeon_emit(cs, fui(guardband_x));
609 radeon_emit(cs, fui(1.0));
610 }
611
612 static inline unsigned
613 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
614 {
615 if (num == 0)
616 return 0;
617
618 if (info->incr == 0)
619 return 0;
620
621 if (num < info->min)
622 return 0;
623
624 return 1 + ((num - info->min) / info->incr);
625 }
626
627 uint32_t
628 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
629 bool instanced_draw, bool indirect_draw,
630 uint32_t draw_vertex_count)
631 {
632 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
633 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
634 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
635 unsigned prim = cmd_buffer->state.pipeline->graphics.prim;
636 unsigned primgroup_size = 128; /* recommended without a GS */
637 unsigned max_primgroup_in_wave = 2;
638 /* SWITCH_ON_EOP(0) is always preferable. */
639 bool wd_switch_on_eop = false;
640 bool ia_switch_on_eop = false;
641 bool ia_switch_on_eoi = false;
642 bool partial_vs_wave = false;
643 bool partial_es_wave = false;
644 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
645 bool multi_instances_smaller_than_primgroup;
646
647 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
648 primgroup_size = cmd_buffer->state.pipeline->graphics.tess.num_patches;
649 else if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
650 primgroup_size = 64; /* recommended with a GS */
651
652 multi_instances_smaller_than_primgroup = indirect_draw || (instanced_draw &&
653 num_prims < primgroup_size);
654 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline)) {
655 /* SWITCH_ON_EOI must be set if PrimID is used. */
656 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.uses_prim_id ||
657 cmd_buffer->state.pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.uses_prim_id)
658 ia_switch_on_eoi = true;
659
660 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
661 if ((family == CHIP_TAHITI ||
662 family == CHIP_PITCAIRN ||
663 family == CHIP_BONAIRE) &&
664 radv_pipeline_has_gs(cmd_buffer->state.pipeline))
665 partial_vs_wave = true;
666
667 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
668 if (cmd_buffer->device->has_distributed_tess) {
669 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
670 partial_es_wave = true;
671
672 if (family == CHIP_TONGA ||
673 family == CHIP_FIJI ||
674 family == CHIP_POLARIS10 ||
675 family == CHIP_POLARIS11 ||
676 family == CHIP_POLARIS12)
677 partial_vs_wave = true;
678 } else {
679 partial_vs_wave = true;
680 }
681 }
682 }
683 /* TODO linestipple */
684
685 if (chip_class >= CIK) {
686 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
687 * 4 shader engines. Set 1 to pass the assertion below.
688 * The other cases are hardware requirements. */
689 if (info->max_se < 4 ||
690 prim == V_008958_DI_PT_POLYGON ||
691 prim == V_008958_DI_PT_LINELOOP ||
692 prim == V_008958_DI_PT_TRIFAN ||
693 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
694 (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
695 (family < CHIP_POLARIS10 ||
696 (prim != V_008958_DI_PT_POINTLIST &&
697 prim != V_008958_DI_PT_LINESTRIP &&
698 prim != V_008958_DI_PT_TRISTRIP))))
699 wd_switch_on_eop = true;
700
701 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
702 * We don't know that for indirect drawing, so treat it as
703 * always problematic. */
704 if (family == CHIP_HAWAII &&
705 (instanced_draw || indirect_draw))
706 wd_switch_on_eop = true;
707
708 /* Performance recommendation for 4 SE Gfx7-8 parts if
709 * instances are smaller than a primgroup.
710 * Assume indirect draws always use small instances.
711 * This is needed for good VS wave utilization.
712 */
713 if (chip_class <= VI &&
714 info->max_se == 4 &&
715 multi_instances_smaller_than_primgroup)
716 wd_switch_on_eop = true;
717
718 /* Required on CIK and later. */
719 if (info->max_se > 2 && !wd_switch_on_eop)
720 ia_switch_on_eoi = true;
721
722 /* Required by Hawaii and, for some special cases, by VI. */
723 if (ia_switch_on_eoi &&
724 (family == CHIP_HAWAII ||
725 (chip_class == VI &&
726 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
727 partial_vs_wave = true;
728
729 /* Instancing bug on Bonaire. */
730 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
731 (instanced_draw || indirect_draw))
732 partial_vs_wave = true;
733
734 /* If the WD switch is false, the IA switch must be false too. */
735 assert(wd_switch_on_eop || !ia_switch_on_eop);
736 }
737 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
738 if (ia_switch_on_eoi)
739 partial_es_wave = true;
740
741 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
742 /* GS requirement. */
743 if (SI_GS_PER_ES / primgroup_size >= cmd_buffer->device->gs_table_depth - 3)
744 partial_es_wave = true;
745
746 /* Hw bug with single-primitive instances and SWITCH_ON_EOI
747 * on multi-SE chips. */
748 if (info->max_se >= 2 && ia_switch_on_eoi &&
749 ((instanced_draw || indirect_draw) &&
750 num_prims <= 1))
751 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
752 }
753
754 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
755 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
756 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
757 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
758 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
759 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop : 0) |
760 S_028AA8_MAX_PRIMGRP_IN_WAVE(chip_class >= VI ?
761 max_primgroup_in_wave : 0);
762
763 }
764
765 void
766 si_emit_wait_fence(struct radeon_winsys_cs *cs,
767 uint64_t va, uint32_t ref,
768 uint32_t mask)
769 {
770 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
771 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
772 radeon_emit(cs, va);
773 radeon_emit(cs, va >> 32);
774 radeon_emit(cs, ref); /* reference value */
775 radeon_emit(cs, mask); /* mask */
776 radeon_emit(cs, 4); /* poll interval */
777 }
778
779 static void
780 si_emit_acquire_mem(struct radeon_winsys_cs *cs,
781 bool is_mec,
782 unsigned cp_coher_cntl)
783 {
784 if (is_mec) {
785 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0) |
786 PKT3_SHADER_TYPE_S(1));
787 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
788 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
789 radeon_emit(cs, 0xff); /* CP_COHER_SIZE_HI */
790 radeon_emit(cs, 0); /* CP_COHER_BASE */
791 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
792 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
793 } else {
794 /* ACQUIRE_MEM is only required on a compute ring. */
795 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
796 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
797 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
798 radeon_emit(cs, 0); /* CP_COHER_BASE */
799 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
800 }
801 }
802
803 void
804 si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
805 enum chip_class chip_class,
806 bool is_mec,
807 enum radv_cmd_flush_bits flush_bits)
808 {
809 unsigned cp_coher_cntl = 0;
810
811 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
812 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
813 if (flush_bits & RADV_CMD_FLAG_INV_SMEM_L1)
814 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
815
816 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
817 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
818 S_0085F0_CB0_DEST_BASE_ENA(1) |
819 S_0085F0_CB1_DEST_BASE_ENA(1) |
820 S_0085F0_CB2_DEST_BASE_ENA(1) |
821 S_0085F0_CB3_DEST_BASE_ENA(1) |
822 S_0085F0_CB4_DEST_BASE_ENA(1) |
823 S_0085F0_CB5_DEST_BASE_ENA(1) |
824 S_0085F0_CB6_DEST_BASE_ENA(1) |
825 S_0085F0_CB7_DEST_BASE_ENA(1);
826
827 /* Necessary for DCC */
828 if (chip_class >= VI) {
829 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
830 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_DATA_TS) |
831 EVENT_INDEX(5));
832 radeon_emit(cs, 0);
833 radeon_emit(cs, 0);
834 radeon_emit(cs, 0);
835 radeon_emit(cs, 0);
836 }
837 }
838
839 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
840 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
841 S_0085F0_DB_DEST_BASE_ENA(1);
842 }
843
844 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
845 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
846 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
847 }
848
849 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
850 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
851 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
852 }
853
854 if (!(flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
855 RADV_CMD_FLAG_FLUSH_AND_INV_DB))) {
856 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
857 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
858 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
859 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
860 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
861 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
862 }
863 }
864
865 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
866 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
867 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
868 }
869
870 /* VGT state sync */
871 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
872 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
873 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
874 }
875
876 /* Make sure ME is idle (it executes most packets) before continuing.
877 * This prevents read-after-write hazards between PFP and ME.
878 */
879 if ((cp_coher_cntl || (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) &&
880 !is_mec) {
881 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
882 radeon_emit(cs, 0);
883 }
884
885 if ((flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) ||
886 (chip_class <= CIK && (flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) {
887 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
888 if (chip_class >= VI)
889 cp_coher_cntl |= S_0301F0_TC_WB_ACTION_ENA(1);
890 } else if(flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2) {
891 cp_coher_cntl |= S_0301F0_TC_WB_ACTION_ENA(1) |
892 S_0301F0_TC_NC_ACTION_ENA(1);
893
894 /* L2 writeback doesn't combine with L1 invalidate */
895 si_emit_acquire_mem(cs, is_mec, cp_coher_cntl);
896
897 cp_coher_cntl = 0;
898 }
899
900 if (flush_bits & RADV_CMD_FLAG_INV_VMEM_L1)
901 cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
902
903 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
904 * Therefore, it should be last. Done in PFP.
905 */
906 if (cp_coher_cntl)
907 si_emit_acquire_mem(cs, is_mec, cp_coher_cntl);
908 }
909
910 void
911 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
912 {
913 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
914
915 if (is_compute)
916 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
917 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
918 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
919 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
920 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
921 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
922 RADV_CMD_FLAG_VGT_FLUSH);
923
924 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
925
926 si_cs_emit_cache_flush(cmd_buffer->cs,
927 cmd_buffer->device->physical_device->rad_info.chip_class,
928 radv_cmd_buffer_uses_mec(cmd_buffer),
929 cmd_buffer->state.flush_bits);
930
931
932 if (cmd_buffer->state.flush_bits)
933 radv_cmd_buffer_trace_emit(cmd_buffer);
934 cmd_buffer->state.flush_bits = 0;
935 }
936
937
938 /* Set this if you want the 3D engine to wait until CP DMA is done.
939 * It should be set on the last CP DMA packet. */
940 #define R600_CP_DMA_SYNC (1 << 0) /* R600+ */
941
942 /* Set this if the source data was used as a destination in a previous CP DMA
943 * packet. It's for preventing a read-after-write (RAW) hazard between two
944 * CP DMA packets. */
945 #define SI_CP_DMA_RAW_WAIT (1 << 1) /* SI+ */
946 #define CIK_CP_DMA_USE_L2 (1 << 2)
947
948 /* Alignment for optimal performance. */
949 #define CP_DMA_ALIGNMENT 32
950 /* The max number of bytes to copy per packet. */
951 #define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - CP_DMA_ALIGNMENT)
952
953 static void si_emit_cp_dma_copy_buffer(struct radv_cmd_buffer *cmd_buffer,
954 uint64_t dst_va, uint64_t src_va,
955 unsigned size, unsigned flags)
956 {
957 struct radeon_winsys_cs *cs = cmd_buffer->cs;
958 uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? S_411_CP_SYNC(1) : 0;
959 uint32_t wr_confirm = !(flags & R600_CP_DMA_SYNC) ? S_414_DISABLE_WR_CONFIRM_GFX6(1) : 0;
960 uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? S_414_RAW_WAIT(1) : 0;
961 uint32_t sel = flags & CIK_CP_DMA_USE_L2 ?
962 S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2) |
963 S_411_DSL_SEL(V_411_DST_ADDR_TC_L2) : 0;
964
965 assert(size);
966 assert((size & ((1<<21)-1)) == size);
967
968 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
969
970 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
971 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
972 radeon_emit(cs, sync_flag | sel); /* CP_SYNC [31] */
973 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
974 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
975 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
976 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
977 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
978 } else {
979 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
980 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
981 radeon_emit(cs, sync_flag | ((src_va >> 32) & 0xffff)); /* CP_SYNC [31] | SRC_ADDR_HI [15:0] */
982 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
983 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
984 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
985 }
986
987 /* CP DMA is executed in ME, but index buffers are read by PFP.
988 * This ensures that ME (CP DMA) is idle before PFP starts fetching
989 * indices. If we wanted to execute CP DMA in PFP, this packet
990 * should precede it.
991 */
992 if (sync_flag && cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
993 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
994 radeon_emit(cs, 0);
995 }
996
997 radv_cmd_buffer_trace_emit(cmd_buffer);
998 }
999
1000 /* Emit a CP DMA packet to clear a buffer. The size must fit in bits [20:0]. */
1001 static void si_emit_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer,
1002 uint64_t dst_va, unsigned size,
1003 uint32_t clear_value, unsigned flags)
1004 {
1005 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1006 uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? S_411_CP_SYNC(1) : 0;
1007 uint32_t wr_confirm = !(flags & R600_CP_DMA_SYNC) ? S_414_DISABLE_WR_CONFIRM_GFX6(1) : 0;
1008 uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? S_414_RAW_WAIT(1) : 0;
1009 uint32_t dst_sel = flags & CIK_CP_DMA_USE_L2 ? S_411_DSL_SEL(V_411_DST_ADDR_TC_L2) : 0;
1010
1011 assert(size);
1012 assert((size & ((1<<21)-1)) == size);
1013
1014 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1015
1016 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1017 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
1018 radeon_emit(cs, sync_flag | dst_sel | S_411_SRC_SEL(V_411_DATA)); /* CP_SYNC [31] | SRC_SEL[30:29] */
1019 radeon_emit(cs, clear_value); /* DATA [31:0] */
1020 radeon_emit(cs, 0);
1021 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1022 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [15:0] */
1023 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
1024 } else {
1025 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
1026 radeon_emit(cs, clear_value); /* DATA [31:0] */
1027 radeon_emit(cs, sync_flag | S_411_SRC_SEL(V_411_DATA)); /* CP_SYNC [31] | SRC_SEL[30:29] */
1028 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1029 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1030 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
1031 }
1032
1033 /* See "copy_buffer" for explanation. */
1034 if (sync_flag && cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1035 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1036 radeon_emit(cs, 0);
1037 }
1038 radv_cmd_buffer_trace_emit(cmd_buffer);
1039 }
1040
1041 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1042 unsigned size)
1043 {
1044 uint64_t aligned_va = va & ~(CP_DMA_ALIGNMENT - 1);
1045 uint64_t aligned_size = ((va + size + CP_DMA_ALIGNMENT -1) & ~(CP_DMA_ALIGNMENT - 1)) - aligned_va;
1046
1047 si_emit_cp_dma_copy_buffer(cmd_buffer, aligned_va, aligned_va,
1048 aligned_size, CIK_CP_DMA_USE_L2);
1049 }
1050
1051 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1052 uint64_t remaining_size, unsigned *flags)
1053 {
1054
1055 /* Flush the caches for the first copy only.
1056 * Also wait for the previous CP DMA operations.
1057 */
1058 if (cmd_buffer->state.flush_bits) {
1059 si_emit_cache_flush(cmd_buffer);
1060 *flags |= SI_CP_DMA_RAW_WAIT;
1061 }
1062
1063 /* Do the synchronization after the last dma, so that all data
1064 * is written to memory.
1065 */
1066 if (byte_count == remaining_size)
1067 *flags |= R600_CP_DMA_SYNC;
1068 }
1069
1070 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1071 {
1072 uint64_t va;
1073 uint32_t offset;
1074 unsigned dma_flags = 0;
1075 unsigned buf_size = CP_DMA_ALIGNMENT * 2;
1076 void *ptr;
1077
1078 assert(size < CP_DMA_ALIGNMENT);
1079
1080 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, CP_DMA_ALIGNMENT, &offset, &ptr);
1081
1082 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1083 va += offset;
1084
1085 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1086
1087 si_emit_cp_dma_copy_buffer(cmd_buffer, va, va + CP_DMA_ALIGNMENT, size,
1088 dma_flags);
1089 }
1090
1091 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1092 uint64_t src_va, uint64_t dest_va,
1093 uint64_t size)
1094 {
1095 uint64_t main_src_va, main_dest_va;
1096 uint64_t skipped_size = 0, realign_size = 0;
1097
1098
1099 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1100 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1101 /* If the size is not aligned, we must add a dummy copy at the end
1102 * just to align the internal counter. Otherwise, the DMA engine
1103 * would slow down by an order of magnitude for following copies.
1104 */
1105 if (size % CP_DMA_ALIGNMENT)
1106 realign_size = CP_DMA_ALIGNMENT - (size % CP_DMA_ALIGNMENT);
1107
1108 /* If the copy begins unaligned, we must start copying from the next
1109 * aligned block and the skipped part should be copied after everything
1110 * else has been copied. Only the src alignment matters, not dst.
1111 */
1112 if (src_va % CP_DMA_ALIGNMENT) {
1113 skipped_size = CP_DMA_ALIGNMENT - (src_va % CP_DMA_ALIGNMENT);
1114 /* The main part will be skipped if the size is too small. */
1115 skipped_size = MIN2(skipped_size, size);
1116 size -= skipped_size;
1117 }
1118 }
1119 main_src_va = src_va + skipped_size;
1120 main_dest_va = dest_va + skipped_size;
1121
1122 while (size) {
1123 unsigned dma_flags = 0;
1124 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
1125
1126 si_cp_dma_prepare(cmd_buffer, byte_count,
1127 size + skipped_size + realign_size,
1128 &dma_flags);
1129
1130 si_emit_cp_dma_copy_buffer(cmd_buffer, main_dest_va, main_src_va,
1131 byte_count, dma_flags);
1132
1133 size -= byte_count;
1134 main_src_va += byte_count;
1135 main_dest_va += byte_count;
1136 }
1137
1138 if (skipped_size) {
1139 unsigned dma_flags = 0;
1140
1141 si_cp_dma_prepare(cmd_buffer, skipped_size,
1142 size + skipped_size + realign_size,
1143 &dma_flags);
1144
1145 si_emit_cp_dma_copy_buffer(cmd_buffer, dest_va, src_va,
1146 skipped_size, dma_flags);
1147 }
1148 if (realign_size)
1149 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1150 }
1151
1152 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1153 uint64_t size, unsigned value)
1154 {
1155
1156 if (!size)
1157 return;
1158
1159 assert(va % 4 == 0 && size % 4 == 0);
1160
1161 while (size) {
1162 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
1163 unsigned dma_flags = 0;
1164
1165 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1166
1167 /* Emit the clear packet. */
1168 si_emit_cp_dma_clear_buffer(cmd_buffer, va, byte_count, value,
1169 dma_flags);
1170
1171 size -= byte_count;
1172 va += byte_count;
1173 }
1174 }
1175
1176 /* For MSAA sample positions. */
1177 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1178 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
1179 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1180 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1181 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1182
1183
1184 /* 2xMSAA
1185 * There are two locations (4, 4), (-4, -4). */
1186 const uint32_t eg_sample_locs_2x[4] = {
1187 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1188 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1189 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1190 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1191 };
1192 const unsigned eg_max_dist_2x = 4;
1193 /* 4xMSAA
1194 * There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
1195 const uint32_t eg_sample_locs_4x[4] = {
1196 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1197 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1198 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1199 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1200 };
1201 const unsigned eg_max_dist_4x = 6;
1202
1203 /* Cayman 8xMSAA */
1204 static const uint32_t cm_sample_locs_8x[] = {
1205 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1206 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1207 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1208 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1209 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1210 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1211 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1212 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1213 };
1214 static const unsigned cm_max_dist_8x = 8;
1215 /* Cayman 16xMSAA */
1216 static const uint32_t cm_sample_locs_16x[] = {
1217 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1218 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1219 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1220 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1221 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1222 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1223 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1224 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1225 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1226 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1227 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1228 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1229 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1230 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1231 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1232 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1233 };
1234 static const unsigned cm_max_dist_16x = 8;
1235
1236 unsigned radv_cayman_get_maxdist(int log_samples)
1237 {
1238 unsigned max_dist[] = {
1239 0,
1240 eg_max_dist_2x,
1241 eg_max_dist_4x,
1242 cm_max_dist_8x,
1243 cm_max_dist_16x
1244 };
1245 return max_dist[log_samples];
1246 }
1247
1248 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples)
1249 {
1250 switch (nr_samples) {
1251 default:
1252 case 1:
1253 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
1254 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
1255 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
1256 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
1257 break;
1258 case 2:
1259 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
1260 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
1261 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
1262 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
1263 break;
1264 case 4:
1265 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
1266 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
1267 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
1268 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
1269 break;
1270 case 8:
1271 radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1272 radeon_emit(cs, cm_sample_locs_8x[0]);
1273 radeon_emit(cs, cm_sample_locs_8x[4]);
1274 radeon_emit(cs, 0);
1275 radeon_emit(cs, 0);
1276 radeon_emit(cs, cm_sample_locs_8x[1]);
1277 radeon_emit(cs, cm_sample_locs_8x[5]);
1278 radeon_emit(cs, 0);
1279 radeon_emit(cs, 0);
1280 radeon_emit(cs, cm_sample_locs_8x[2]);
1281 radeon_emit(cs, cm_sample_locs_8x[6]);
1282 radeon_emit(cs, 0);
1283 radeon_emit(cs, 0);
1284 radeon_emit(cs, cm_sample_locs_8x[3]);
1285 radeon_emit(cs, cm_sample_locs_8x[7]);
1286 break;
1287 case 16:
1288 radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
1289 radeon_emit(cs, cm_sample_locs_16x[0]);
1290 radeon_emit(cs, cm_sample_locs_16x[4]);
1291 radeon_emit(cs, cm_sample_locs_16x[8]);
1292 radeon_emit(cs, cm_sample_locs_16x[12]);
1293 radeon_emit(cs, cm_sample_locs_16x[1]);
1294 radeon_emit(cs, cm_sample_locs_16x[5]);
1295 radeon_emit(cs, cm_sample_locs_16x[9]);
1296 radeon_emit(cs, cm_sample_locs_16x[13]);
1297 radeon_emit(cs, cm_sample_locs_16x[2]);
1298 radeon_emit(cs, cm_sample_locs_16x[6]);
1299 radeon_emit(cs, cm_sample_locs_16x[10]);
1300 radeon_emit(cs, cm_sample_locs_16x[14]);
1301 radeon_emit(cs, cm_sample_locs_16x[3]);
1302 radeon_emit(cs, cm_sample_locs_16x[7]);
1303 radeon_emit(cs, cm_sample_locs_16x[11]);
1304 radeon_emit(cs, cm_sample_locs_16x[15]);
1305 break;
1306 }
1307 }
1308
1309 static void radv_cayman_get_sample_position(struct radv_device *device,
1310 unsigned sample_count,
1311 unsigned sample_index, float *out_value)
1312 {
1313 int offset, index;
1314 struct {
1315 int idx:4;
1316 } val;
1317 switch (sample_count) {
1318 case 1:
1319 default:
1320 out_value[0] = out_value[1] = 0.5;
1321 break;
1322 case 2:
1323 offset = 4 * (sample_index * 2);
1324 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1325 out_value[0] = (float)(val.idx + 8) / 16.0f;
1326 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1327 out_value[1] = (float)(val.idx + 8) / 16.0f;
1328 break;
1329 case 4:
1330 offset = 4 * (sample_index * 2);
1331 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1332 out_value[0] = (float)(val.idx + 8) / 16.0f;
1333 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1334 out_value[1] = (float)(val.idx + 8) / 16.0f;
1335 break;
1336 case 8:
1337 offset = 4 * (sample_index % 4 * 2);
1338 index = (sample_index / 4) * 4;
1339 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1340 out_value[0] = (float)(val.idx + 8) / 16.0f;
1341 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1342 out_value[1] = (float)(val.idx + 8) / 16.0f;
1343 break;
1344 case 16:
1345 offset = 4 * (sample_index % 4 * 2);
1346 index = (sample_index / 4) * 4;
1347 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1348 out_value[0] = (float)(val.idx + 8) / 16.0f;
1349 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1350 out_value[1] = (float)(val.idx + 8) / 16.0f;
1351 break;
1352 }
1353 }
1354
1355 void radv_device_init_msaa(struct radv_device *device)
1356 {
1357 int i;
1358 radv_cayman_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1359
1360 for (i = 0; i < 2; i++)
1361 radv_cayman_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1362 for (i = 0; i < 4; i++)
1363 radv_cayman_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1364 for (i = 0; i < 8; i++)
1365 radv_cayman_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1366 for (i = 0; i < 16; i++)
1367 radv_cayman_get_sample_position(device, 16, i, device->sample_locations_16x[i]);
1368 }