2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
6 * Copyright © 2015 Advanced Micro Devices, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 /* command buffer handling for AMD GCN */
30 #include "radv_private.h"
31 #include "radv_shader.h"
34 #include "radv_util.h"
35 #include "main/macros.h"
38 si_write_harvested_raster_configs(struct radv_physical_device
*physical_device
,
39 struct radeon_cmdbuf
*cs
,
40 unsigned raster_config
,
41 unsigned raster_config_1
)
43 unsigned num_se
= MAX2(physical_device
->rad_info
.max_se
, 1);
44 unsigned raster_config_se
[4];
47 ac_get_harvested_configs(&physical_device
->rad_info
,
52 for (se
= 0; se
< num_se
; se
++) {
53 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
54 if (physical_device
->rad_info
.chip_class
< GFX7
)
55 radeon_set_config_reg(cs
, R_00802C_GRBM_GFX_INDEX
,
56 S_00802C_SE_INDEX(se
) |
57 S_00802C_SH_BROADCAST_WRITES(1) |
58 S_00802C_INSTANCE_BROADCAST_WRITES(1));
60 radeon_set_uconfig_reg(cs
, R_030800_GRBM_GFX_INDEX
,
61 S_030800_SE_INDEX(se
) | S_030800_SH_BROADCAST_WRITES(1) |
62 S_030800_INSTANCE_BROADCAST_WRITES(1));
63 radeon_set_context_reg(cs
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
[se
]);
66 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
67 if (physical_device
->rad_info
.chip_class
< GFX7
)
68 radeon_set_config_reg(cs
, R_00802C_GRBM_GFX_INDEX
,
69 S_00802C_SE_BROADCAST_WRITES(1) |
70 S_00802C_SH_BROADCAST_WRITES(1) |
71 S_00802C_INSTANCE_BROADCAST_WRITES(1));
73 radeon_set_uconfig_reg(cs
, R_030800_GRBM_GFX_INDEX
,
74 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
75 S_030800_INSTANCE_BROADCAST_WRITES(1));
77 if (physical_device
->rad_info
.chip_class
>= GFX7
)
78 radeon_set_context_reg(cs
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
82 si_emit_compute(struct radv_physical_device
*physical_device
,
83 struct radeon_cmdbuf
*cs
)
85 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
90 radeon_set_sh_reg_seq(cs
, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0
, 2);
91 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
92 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
93 radeon_emit(cs
, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
94 radeon_emit(cs
, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
96 if (physical_device
->rad_info
.chip_class
>= GFX7
) {
97 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
98 radeon_set_sh_reg_seq(cs
,
99 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2
, 2);
100 radeon_emit(cs
, S_00B858_SH0_CU_EN(0xffff) |
101 S_00B858_SH1_CU_EN(0xffff));
102 radeon_emit(cs
, S_00B858_SH0_CU_EN(0xffff) |
103 S_00B858_SH1_CU_EN(0xffff));
106 if (physical_device
->rad_info
.chip_class
>= GFX10
)
107 radeon_set_sh_reg(cs
, R_00B8A0_COMPUTE_PGM_RSRC3
, 0);
109 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
110 * and is now per pipe, so it should be handled in the
111 * kernel if we want to use something other than the default value,
112 * which is now 0x22f.
114 if (physical_device
->rad_info
.chip_class
<= GFX6
) {
115 /* XXX: This should be:
116 * (number of compute units) * 4 * (waves per simd) - 1 */
118 radeon_set_sh_reg(cs
, R_00B82C_COMPUTE_MAX_WAVE_ID
,
119 0x190 /* Default value */);
123 /* 12.4 fixed-point */
124 static unsigned radv_pack_float_12p4(float x
)
127 x
>= 4096 ? 0xffff : x
* 16;
131 si_set_raster_config(struct radv_physical_device
*physical_device
,
132 struct radeon_cmdbuf
*cs
)
134 unsigned num_rb
= MIN2(physical_device
->rad_info
.num_render_backends
, 16);
135 unsigned rb_mask
= physical_device
->rad_info
.enabled_rb_mask
;
136 unsigned raster_config
, raster_config_1
;
138 ac_get_raster_config(&physical_device
->rad_info
,
140 &raster_config_1
, NULL
);
142 /* Always use the default config when all backends are enabled
143 * (or when we failed to determine the enabled backends).
145 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
146 radeon_set_context_reg(cs
, R_028350_PA_SC_RASTER_CONFIG
,
148 if (physical_device
->rad_info
.chip_class
>= GFX7
)
149 radeon_set_context_reg(cs
, R_028354_PA_SC_RASTER_CONFIG_1
,
152 si_write_harvested_raster_configs(physical_device
, cs
,
159 si_emit_graphics(struct radv_physical_device
*physical_device
,
160 struct radeon_cmdbuf
*cs
)
162 bool has_clear_state
= physical_device
->rad_info
.has_clear_state
;
165 radeon_emit(cs
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
166 radeon_emit(cs
, CONTEXT_CONTROL_LOAD_ENABLE(1));
167 radeon_emit(cs
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
169 if (has_clear_state
) {
170 radeon_emit(cs
, PKT3(PKT3_CLEAR_STATE
, 0, 0));
174 if (physical_device
->rad_info
.chip_class
<= GFX8
)
175 si_set_raster_config(physical_device
, cs
);
177 radeon_set_context_reg(cs
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
178 if (!has_clear_state
)
179 radeon_set_context_reg(cs
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
181 /* FIXME calculate these values somehow ??? */
182 if (physical_device
->rad_info
.chip_class
<= GFX8
) {
183 radeon_set_context_reg(cs
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
184 radeon_set_context_reg(cs
, R_028A58_VGT_ES_PER_GS
, 0x40);
187 if (!has_clear_state
) {
188 radeon_set_context_reg(cs
, R_028A5C_VGT_GS_PER_VS
, 0x2);
189 radeon_set_context_reg(cs
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
190 radeon_set_context_reg(cs
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
193 if (physical_device
->rad_info
.chip_class
<= GFX9
)
194 radeon_set_context_reg(cs
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
195 if (!has_clear_state
)
196 radeon_set_context_reg(cs
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
197 if (physical_device
->rad_info
.chip_class
< GFX7
)
198 radeon_set_config_reg(cs
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
199 S_008A14_CLIP_VTX_REORDER_ENA(1));
201 if (!has_clear_state
)
202 radeon_set_context_reg(cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, 0);
204 /* CLEAR_STATE doesn't clear these correctly on certain generations.
205 * I don't know why. Deduced by trial and error.
207 if (physical_device
->rad_info
.chip_class
<= GFX7
|| !has_clear_state
) {
208 radeon_set_context_reg(cs
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
209 radeon_set_context_reg(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
,
210 S_028204_WINDOW_OFFSET_DISABLE(1));
211 radeon_set_context_reg(cs
, R_028240_PA_SC_GENERIC_SCISSOR_TL
,
212 S_028240_WINDOW_OFFSET_DISABLE(1));
213 radeon_set_context_reg(cs
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
214 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
215 radeon_set_context_reg(cs
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
216 radeon_set_context_reg(cs
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
217 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
220 if (!has_clear_state
) {
221 for (i
= 0; i
< 16; i
++) {
222 radeon_set_context_reg(cs
, R_0282D0_PA_SC_VPORT_ZMIN_0
+ i
*8, 0);
223 radeon_set_context_reg(cs
, R_0282D4_PA_SC_VPORT_ZMAX_0
+ i
*8, fui(1.0));
227 if (!has_clear_state
) {
228 radeon_set_context_reg(cs
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
229 radeon_set_context_reg(cs
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
230 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on GFX6 */
231 radeon_set_context_reg(cs
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
232 radeon_set_context_reg(cs
, R_028820_PA_CL_NANINF_CNTL
, 0);
233 radeon_set_context_reg(cs
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
234 radeon_set_context_reg(cs
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
235 radeon_set_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
238 radeon_set_context_reg(cs
, R_02800C_DB_RENDER_OVERRIDE
,
239 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
240 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
));
242 if (physical_device
->rad_info
.chip_class
>= GFX10
) {
243 radeon_set_context_reg(cs
, R_028A98_VGT_DRAW_PAYLOAD_CNTL
, 0);
244 radeon_set_uconfig_reg(cs
, R_030964_GE_MAX_VTX_INDX
, ~0);
245 radeon_set_uconfig_reg(cs
, R_030924_GE_MIN_VTX_INDX
, 0);
246 radeon_set_uconfig_reg(cs
, R_030928_GE_INDX_OFFSET
, 0);
247 radeon_set_uconfig_reg(cs
, R_03097C_GE_STEREO_CNTL
, 0);
248 radeon_set_uconfig_reg(cs
, R_030988_GE_USER_VGPR_EN
, 0);
249 } else if (physical_device
->rad_info
.chip_class
== GFX9
) {
250 radeon_set_uconfig_reg(cs
, R_030920_VGT_MAX_VTX_INDX
, ~0);
251 radeon_set_uconfig_reg(cs
, R_030924_VGT_MIN_VTX_INDX
, 0);
252 radeon_set_uconfig_reg(cs
, R_030928_VGT_INDX_OFFSET
, 0);
254 /* These registers, when written, also overwrite the
255 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
256 * them. It would be an issue if there was another UMD
259 radeon_set_context_reg(cs
, R_028400_VGT_MAX_VTX_INDX
, ~0);
260 radeon_set_context_reg(cs
, R_028404_VGT_MIN_VTX_INDX
, 0);
261 radeon_set_context_reg(cs
, R_028408_VGT_INDX_OFFSET
, 0);
264 if (physical_device
->rad_info
.chip_class
>= GFX7
) {
265 if (physical_device
->rad_info
.chip_class
>= GFX10
) {
266 /* Logical CUs 16 - 31 */
267 radeon_set_sh_reg_idx(physical_device
, cs
, R_00B404_SPI_SHADER_PGM_RSRC4_HS
,
268 3, S_00B404_CU_EN(0xffff));
269 radeon_set_sh_reg_idx(physical_device
, cs
, R_00B104_SPI_SHADER_PGM_RSRC4_VS
,
270 3, S_00B104_CU_EN(0xffff));
271 radeon_set_sh_reg_idx(physical_device
, cs
, R_00B004_SPI_SHADER_PGM_RSRC4_PS
,
272 3, S_00B004_CU_EN(0xffff));
275 if (physical_device
->rad_info
.chip_class
>= GFX9
) {
276 radeon_set_sh_reg_idx(physical_device
, cs
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
277 3, S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
279 radeon_set_sh_reg(cs
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
,
280 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
281 radeon_set_sh_reg(cs
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
282 S_00B41C_WAVE_LIMIT(0x3F));
283 radeon_set_sh_reg(cs
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
,
284 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
285 /* If this is 0, Bonaire can hang even if GS isn't being used.
286 * Other chips are unaffected. These are suboptimal values,
287 * but we don't use on-chip GS.
289 radeon_set_context_reg(cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
290 S_028A44_ES_VERTS_PER_SUBGRP(64) |
291 S_028A44_GS_PRIMS_PER_SUBGRP(4));
294 /* Compute LATE_ALLOC_VS.LIMIT. */
295 unsigned num_cu_per_sh
= physical_device
->rad_info
.num_good_cu_per_sh
;
296 unsigned late_alloc_wave64
= 0; /* The limit is per SH. */
297 unsigned late_alloc_wave64_gs
= 0;
298 unsigned cu_mask_vs
= 0xffff;
299 unsigned cu_mask_gs
= 0xffff;
301 if (physical_device
->rad_info
.chip_class
>= GFX10
) {
302 /* For Wave32, the hw will launch twice the number of late
303 * alloc waves, so 1 == 2x wave32.
305 if (num_cu_per_sh
<= 6) {
306 late_alloc_wave64
= num_cu_per_sh
- 2;
308 late_alloc_wave64
= (num_cu_per_sh
- 2) * 4;
310 /* CU2 & CU3 disabled because of the dual CU design */
312 cu_mask_gs
= 0xfff3; /* NGG only */
315 late_alloc_wave64_gs
= late_alloc_wave64
;
317 /* Don't use late alloc for NGG on Navi14 due to a hw
318 * bug. If NGG is never used, enable all CUs.
320 if (!physical_device
->use_ngg
||
321 physical_device
->rad_info
.family
== CHIP_NAVI14
) {
322 late_alloc_wave64_gs
= 0;
326 if (physical_device
->rad_info
.family
== CHIP_KABINI
) {
327 late_alloc_wave64
= 0; /* Potential hang on Kabini. */
328 } else if (num_cu_per_sh
<= 4) {
329 /* Too few available compute units per SH.
330 * Disallowing VS to run on one CU could hurt
331 * us more than late VS allocation would help.
333 * 2 is the highest safe number that allows us
334 * to keep all CUs enabled.
336 late_alloc_wave64
= 2;
338 /* This is a good initial value, allowing 1
339 * late_alloc wave per SIMD on num_cu - 2.
341 late_alloc_wave64
= (num_cu_per_sh
- 2) * 4;
344 if (late_alloc_wave64
> 2)
345 cu_mask_vs
= 0xfffe; /* 1 CU disabled */
348 radeon_set_sh_reg_idx(physical_device
, cs
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
349 3, S_00B118_CU_EN(cu_mask_vs
) |
350 S_00B118_WAVE_LIMIT(0x3F));
351 radeon_set_sh_reg(cs
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
,
352 S_00B11C_LIMIT(late_alloc_wave64
));
354 radeon_set_sh_reg_idx(physical_device
, cs
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
,
355 3, S_00B21C_CU_EN(cu_mask_gs
) | S_00B21C_WAVE_LIMIT(0x3F));
357 if (physical_device
->rad_info
.chip_class
>= GFX10
) {
358 radeon_set_sh_reg_idx(physical_device
, cs
, R_00B204_SPI_SHADER_PGM_RSRC4_GS
,
359 3, S_00B204_CU_EN(0xffff) |
360 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64_gs
));
363 radeon_set_sh_reg_idx(physical_device
, cs
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
,
364 3, S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
367 if (physical_device
->rad_info
.chip_class
>= GFX10
) {
368 /* Break up a pixel wave if it contains deallocs for more than
369 * half the parameter cache.
371 * To avoid a deadlock where pixel waves aren't launched
372 * because they're waiting for more pixels while the frontend
373 * is stuck waiting for PC space, the maximum allowed value is
374 * the size of the PC minus the largest possible allocation for
375 * a single primitive shader subgroup.
377 radeon_set_context_reg(cs
, R_028C50_PA_SC_NGG_MODE_CNTL
,
378 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
379 radeon_set_context_reg(cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
381 /* Enable CMASK/FMASK/HTILE/DCC caching in L2 for small chips. */
382 unsigned meta_write_policy
, meta_read_policy
;
384 /* TODO: investigate whether LRU improves performance on other chips too */
385 if (physical_device
->rad_info
.num_render_backends
<= 4) {
386 meta_write_policy
= V_02807C_CACHE_LRU_WR
; /* cache writes */
387 meta_read_policy
= V_02807C_CACHE_LRU_RD
; /* cache reads */
389 meta_write_policy
= V_02807C_CACHE_STREAM_WR
; /* write combine */
390 meta_read_policy
= V_02807C_CACHE_NOA_RD
; /* don't cache reads */
393 radeon_set_context_reg(cs
, R_02807C_DB_RMI_L2_CACHE_CONTROL
,
394 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
395 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
396 S_02807C_HTILE_WR_POLICY(meta_write_policy
) |
397 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
398 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD
) |
399 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD
) |
400 S_02807C_HTILE_RD_POLICY(meta_read_policy
));
402 radeon_set_context_reg(cs
, R_028410_CB_RMI_GL2_CACHE_CONTROL
,
403 S_028410_CMASK_WR_POLICY(meta_write_policy
) |
404 S_028410_FMASK_WR_POLICY(meta_write_policy
) |
405 S_028410_DCC_WR_POLICY(meta_write_policy
) |
406 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
407 S_028410_CMASK_RD_POLICY(meta_read_policy
) |
408 S_028410_FMASK_RD_POLICY(meta_read_policy
) |
409 S_028410_DCC_RD_POLICY(meta_read_policy
) |
410 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD
));
411 radeon_set_context_reg(cs
, R_028428_CB_COVERAGE_OUT_CONTROL
, 0);
413 radeon_set_sh_reg(cs
, R_00B0C0_SPI_SHADER_REQ_CTRL_PS
,
414 S_00B0C0_SOFT_GROUPING_EN(1) |
415 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
416 radeon_set_sh_reg(cs
, R_00B1C0_SPI_SHADER_REQ_CTRL_VS
, 0);
418 if (physical_device
->rad_info
.family
== CHIP_NAVI10
||
419 physical_device
->rad_info
.family
== CHIP_NAVI12
||
420 physical_device
->rad_info
.family
== CHIP_NAVI14
) {
421 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
422 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
423 radeon_emit(cs
, EVENT_TYPE(V_028A90_SQ_NON_EVENT
) | EVENT_INDEX(0));
426 /* TODO: For culling, replace 128 with 256. */
427 radeon_set_uconfig_reg(cs
, R_030980_GE_PC_ALLOC
,
428 S_030980_OVERSUB_EN(1) |
429 S_030980_NUM_PC_LINES(128 * physical_device
->rad_info
.max_se
- 1));
432 if (physical_device
->rad_info
.chip_class
>= GFX9
) {
433 radeon_set_context_reg(cs
, R_028B50_VGT_TESS_DISTRIBUTION
,
434 S_028B50_ACCUM_ISOLINE(40) |
435 S_028B50_ACCUM_TRI(30) |
436 S_028B50_ACCUM_QUAD(24) |
437 S_028B50_DONUT_SPLIT(24) |
438 S_028B50_TRAP_SPLIT(6));
439 } else if (physical_device
->rad_info
.chip_class
>= GFX8
) {
440 uint32_t vgt_tess_distribution
;
442 vgt_tess_distribution
= S_028B50_ACCUM_ISOLINE(32) |
443 S_028B50_ACCUM_TRI(11) |
444 S_028B50_ACCUM_QUAD(11) |
445 S_028B50_DONUT_SPLIT(16);
447 if (physical_device
->rad_info
.family
== CHIP_FIJI
||
448 physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
449 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
451 radeon_set_context_reg(cs
, R_028B50_VGT_TESS_DISTRIBUTION
,
452 vgt_tess_distribution
);
453 } else if (!has_clear_state
) {
454 radeon_set_context_reg(cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
455 radeon_set_context_reg(cs
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
458 if (physical_device
->rad_info
.chip_class
>= GFX9
) {
459 radeon_set_context_reg(cs
, R_028C48_PA_SC_BINNER_CNTL_1
,
460 S_028C48_MAX_ALLOC_COUNT(physical_device
->rad_info
.pbb_max_alloc_count
- 1) |
461 S_028C48_MAX_PRIM_PER_BATCH(1023));
462 radeon_set_context_reg(cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
463 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
464 radeon_set_uconfig_reg(cs
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
467 unsigned tmp
= (unsigned)(1.0 * 8.0);
468 radeon_set_context_reg_seq(cs
, R_028A00_PA_SU_POINT_SIZE
, 1);
469 radeon_emit(cs
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
470 radeon_set_context_reg_seq(cs
, R_028A04_PA_SU_POINT_MINMAX
, 1);
471 radeon_emit(cs
, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
472 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
474 if (!has_clear_state
) {
475 radeon_set_context_reg(cs
, R_028004_DB_COUNT_CONTROL
,
476 S_028004_ZPASS_INCREMENT_DISABLE(1));
479 /* Enable the Polaris small primitive filter control.
480 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
481 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
482 * and AMDVLK doesn't have a workaround as well.
484 if (physical_device
->rad_info
.family
>= CHIP_POLARIS10
) {
485 unsigned small_prim_filter_cntl
=
486 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
487 /* Workaround for a hw line bug. */
488 S_028830_LINE_FILTER_DISABLE(physical_device
->rad_info
.family
<= CHIP_POLARIS12
);
490 radeon_set_context_reg(cs
, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
491 small_prim_filter_cntl
);
494 si_emit_compute(physical_device
, cs
);
498 cik_create_gfx_config(struct radv_device
*device
)
500 struct radeon_cmdbuf
*cs
= device
->ws
->cs_create(device
->ws
, RING_GFX
);
504 si_emit_graphics(device
->physical_device
, cs
);
506 while (cs
->cdw
& 7) {
507 if (device
->physical_device
->rad_info
.gfx_ib_pad_with_type2
)
508 radeon_emit(cs
, 0x80000000);
510 radeon_emit(cs
, 0xffff1000);
513 device
->gfx_init
= device
->ws
->buffer_create(device
->ws
,
516 RADEON_FLAG_CPU_ACCESS
|
517 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
518 RADEON_FLAG_READ_ONLY
,
519 RADV_BO_PRIORITY_CS
);
520 if (!device
->gfx_init
)
523 void *map
= device
->ws
->buffer_map(device
->gfx_init
);
525 device
->ws
->buffer_destroy(device
->gfx_init
);
526 device
->gfx_init
= NULL
;
529 memcpy(map
, cs
->buf
, cs
->cdw
* 4);
531 device
->ws
->buffer_unmap(device
->gfx_init
);
532 device
->gfx_init_size_dw
= cs
->cdw
;
534 device
->ws
->cs_destroy(cs
);
538 get_viewport_xform(const VkViewport
*viewport
,
539 float scale
[3], float translate
[3])
541 float x
= viewport
->x
;
542 float y
= viewport
->y
;
543 float half_width
= 0.5f
* viewport
->width
;
544 float half_height
= 0.5f
* viewport
->height
;
545 double n
= viewport
->minDepth
;
546 double f
= viewport
->maxDepth
;
548 scale
[0] = half_width
;
549 translate
[0] = half_width
+ x
;
550 scale
[1] = half_height
;
551 translate
[1] = half_height
+ y
;
558 si_write_viewport(struct radeon_cmdbuf
*cs
, int first_vp
,
559 int count
, const VkViewport
*viewports
)
564 radeon_set_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE
+
565 first_vp
* 4 * 6, count
* 6);
567 for (i
= 0; i
< count
; i
++) {
568 float scale
[3], translate
[3];
571 get_viewport_xform(&viewports
[i
], scale
, translate
);
572 radeon_emit(cs
, fui(scale
[0]));
573 radeon_emit(cs
, fui(translate
[0]));
574 radeon_emit(cs
, fui(scale
[1]));
575 radeon_emit(cs
, fui(translate
[1]));
576 radeon_emit(cs
, fui(scale
[2]));
577 radeon_emit(cs
, fui(translate
[2]));
580 radeon_set_context_reg_seq(cs
, R_0282D0_PA_SC_VPORT_ZMIN_0
+
581 first_vp
* 4 * 2, count
* 2);
582 for (i
= 0; i
< count
; i
++) {
583 float zmin
= MIN2(viewports
[i
].minDepth
, viewports
[i
].maxDepth
);
584 float zmax
= MAX2(viewports
[i
].minDepth
, viewports
[i
].maxDepth
);
585 radeon_emit(cs
, fui(zmin
));
586 radeon_emit(cs
, fui(zmax
));
590 static VkRect2D
si_scissor_from_viewport(const VkViewport
*viewport
)
592 float scale
[3], translate
[3];
595 get_viewport_xform(viewport
, scale
, translate
);
597 rect
.offset
.x
= translate
[0] - fabs(scale
[0]);
598 rect
.offset
.y
= translate
[1] - fabs(scale
[1]);
599 rect
.extent
.width
= ceilf(translate
[0] + fabs(scale
[0])) - rect
.offset
.x
;
600 rect
.extent
.height
= ceilf(translate
[1] + fabs(scale
[1])) - rect
.offset
.y
;
605 static VkRect2D
si_intersect_scissor(const VkRect2D
*a
, const VkRect2D
*b
) {
607 ret
.offset
.x
= MAX2(a
->offset
.x
, b
->offset
.x
);
608 ret
.offset
.y
= MAX2(a
->offset
.y
, b
->offset
.y
);
609 ret
.extent
.width
= MIN2(a
->offset
.x
+ a
->extent
.width
,
610 b
->offset
.x
+ b
->extent
.width
) - ret
.offset
.x
;
611 ret
.extent
.height
= MIN2(a
->offset
.y
+ a
->extent
.height
,
612 b
->offset
.y
+ b
->extent
.height
) - ret
.offset
.y
;
617 si_write_scissors(struct radeon_cmdbuf
*cs
, int first
,
618 int count
, const VkRect2D
*scissors
,
619 const VkViewport
*viewports
, bool can_use_guardband
)
622 float scale
[3], translate
[3], guardband_x
= INFINITY
, guardband_y
= INFINITY
;
623 const float max_range
= 32767.0f
;
627 radeon_set_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
+ first
* 4 * 2, count
* 2);
628 for (i
= 0; i
< count
; i
++) {
629 VkRect2D viewport_scissor
= si_scissor_from_viewport(viewports
+ i
);
630 VkRect2D scissor
= si_intersect_scissor(&scissors
[i
], &viewport_scissor
);
632 get_viewport_xform(viewports
+ i
, scale
, translate
);
633 scale
[0] = fabsf(scale
[0]);
634 scale
[1] = fabsf(scale
[1]);
641 guardband_x
= MIN2(guardband_x
, (max_range
- fabsf(translate
[0])) / scale
[0]);
642 guardband_y
= MIN2(guardband_y
, (max_range
- fabsf(translate
[1])) / scale
[1]);
644 radeon_emit(cs
, S_028250_TL_X(scissor
.offset
.x
) |
645 S_028250_TL_Y(scissor
.offset
.y
) |
646 S_028250_WINDOW_OFFSET_DISABLE(1));
647 radeon_emit(cs
, S_028254_BR_X(scissor
.offset
.x
+ scissor
.extent
.width
) |
648 S_028254_BR_Y(scissor
.offset
.y
+ scissor
.extent
.height
));
650 if (!can_use_guardband
) {
655 radeon_set_context_reg_seq(cs
, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 4);
656 radeon_emit(cs
, fui(guardband_y
));
657 radeon_emit(cs
, fui(1.0));
658 radeon_emit(cs
, fui(guardband_x
));
659 radeon_emit(cs
, fui(1.0));
662 static inline unsigned
663 radv_prims_for_vertices(struct radv_prim_vertex_count
*info
, unsigned num
)
674 return 1 + ((num
- info
->min
) / info
->incr
);
678 si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
679 bool instanced_draw
, bool indirect_draw
,
680 bool count_from_stream_output
,
681 uint32_t draw_vertex_count
)
683 enum chip_class chip_class
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
;
684 enum radeon_family family
= cmd_buffer
->device
->physical_device
->rad_info
.family
;
685 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
686 const unsigned max_primgroup_in_wave
= 2;
687 /* SWITCH_ON_EOP(0) is always preferable. */
688 bool wd_switch_on_eop
= false;
689 bool ia_switch_on_eop
= false;
690 bool ia_switch_on_eoi
= false;
691 bool partial_vs_wave
= false;
692 bool partial_es_wave
= cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.partial_es_wave
;
693 bool multi_instances_smaller_than_primgroup
;
695 multi_instances_smaller_than_primgroup
= indirect_draw
;
696 if (!multi_instances_smaller_than_primgroup
&& instanced_draw
) {
697 uint32_t num_prims
= radv_prims_for_vertices(&cmd_buffer
->state
.pipeline
->graphics
.prim_vertex_count
, draw_vertex_count
);
698 if (num_prims
< cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.primgroup_size
)
699 multi_instances_smaller_than_primgroup
= true;
702 ia_switch_on_eoi
= cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.ia_switch_on_eoi
;
703 partial_vs_wave
= cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.partial_vs_wave
;
705 if (chip_class
>= GFX7
) {
706 wd_switch_on_eop
= cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.wd_switch_on_eop
;
708 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
709 * We don't know that for indirect drawing, so treat it as
710 * always problematic. */
711 if (family
== CHIP_HAWAII
&&
712 (instanced_draw
|| indirect_draw
))
713 wd_switch_on_eop
= true;
715 /* Performance recommendation for 4 SE Gfx7-8 parts if
716 * instances are smaller than a primgroup.
717 * Assume indirect draws always use small instances.
718 * This is needed for good VS wave utilization.
720 if (chip_class
<= GFX8
&&
722 multi_instances_smaller_than_primgroup
)
723 wd_switch_on_eop
= true;
725 /* Required on GFX7 and later. */
726 if (info
->max_se
> 2 && !wd_switch_on_eop
)
727 ia_switch_on_eoi
= true;
729 /* Required by Hawaii and, for some special cases, by GFX8. */
730 if (ia_switch_on_eoi
&&
731 (family
== CHIP_HAWAII
||
732 (chip_class
== GFX8
&&
733 /* max primgroup in wave is always 2 - leave this for documentation */
734 (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
) || max_primgroup_in_wave
!= 2))))
735 partial_vs_wave
= true;
737 /* Instancing bug on Bonaire. */
738 if (family
== CHIP_BONAIRE
&& ia_switch_on_eoi
&&
739 (instanced_draw
|| indirect_draw
))
740 partial_vs_wave
= true;
742 /* Hardware requirement when drawing primitives from a stream
745 if (count_from_stream_output
)
746 wd_switch_on_eop
= true;
748 /* If the WD switch is false, the IA switch must be false too. */
749 assert(wd_switch_on_eop
|| !ia_switch_on_eop
);
751 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
752 if (chip_class
<= GFX8
&& ia_switch_on_eoi
)
753 partial_es_wave
= true;
755 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
)) {
756 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
757 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
758 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
760 if (family
== CHIP_HAWAII
&& ia_switch_on_eoi
) {
761 bool set_vgt_flush
= indirect_draw
;
762 if (!set_vgt_flush
&& instanced_draw
) {
763 uint32_t num_prims
= radv_prims_for_vertices(&cmd_buffer
->state
.pipeline
->graphics
.prim_vertex_count
, draw_vertex_count
);
765 set_vgt_flush
= true;
768 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_FLUSH
;
772 return cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.base
|
773 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
774 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi
) |
775 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
776 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave
) |
777 S_028AA8_WD_SWITCH_ON_EOP(chip_class
>= GFX7
? wd_switch_on_eop
: 0);
781 void si_cs_emit_write_event_eop(struct radeon_cmdbuf
*cs
,
782 enum chip_class chip_class
,
784 unsigned event
, unsigned event_flags
,
785 unsigned dst_sel
, unsigned data_sel
,
788 uint64_t gfx9_eop_bug_va
)
790 unsigned op
= EVENT_TYPE(event
) |
791 EVENT_INDEX(event
== V_028A90_CS_DONE
||
792 event
== V_028A90_PS_DONE
? 6 : 5) |
794 unsigned is_gfx8_mec
= is_mec
&& chip_class
< GFX9
;
795 unsigned sel
= EOP_DST_SEL(dst_sel
) |
796 EOP_DATA_SEL(data_sel
);
798 /* Wait for write confirmation before writing data, but don't send
800 if (data_sel
!= EOP_DATA_SEL_DISCARD
)
801 sel
|= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM
);
803 if (chip_class
>= GFX9
|| is_gfx8_mec
) {
804 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
805 * counters) must immediately precede every timestamp event to
806 * prevent a GPU hang on GFX9.
808 if (chip_class
== GFX9
&& !is_mec
) {
809 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
810 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE
) | EVENT_INDEX(1));
811 radeon_emit(cs
, gfx9_eop_bug_va
);
812 radeon_emit(cs
, gfx9_eop_bug_va
>> 32);
815 radeon_emit(cs
, PKT3(PKT3_RELEASE_MEM
, is_gfx8_mec
? 5 : 6, false));
817 radeon_emit(cs
, sel
);
818 radeon_emit(cs
, va
); /* address lo */
819 radeon_emit(cs
, va
>> 32); /* address hi */
820 radeon_emit(cs
, new_fence
); /* immediate data lo */
821 radeon_emit(cs
, 0); /* immediate data hi */
823 radeon_emit(cs
, 0); /* unused */
825 if (chip_class
== GFX7
||
826 chip_class
== GFX8
) {
827 /* Two EOP events are required to make all engines go idle
828 * (and optional cache flushes executed) before the timestamp
831 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, false));
834 radeon_emit(cs
, ((va
>> 32) & 0xffff) | sel
);
835 radeon_emit(cs
, 0); /* immediate data */
836 radeon_emit(cs
, 0); /* unused */
839 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, false));
842 radeon_emit(cs
, ((va
>> 32) & 0xffff) | sel
);
843 radeon_emit(cs
, new_fence
); /* immediate data */
844 radeon_emit(cs
, 0); /* unused */
849 radv_cp_wait_mem(struct radeon_cmdbuf
*cs
, uint32_t op
, uint64_t va
,
850 uint32_t ref
, uint32_t mask
)
852 assert(op
== WAIT_REG_MEM_EQUAL
||
853 op
== WAIT_REG_MEM_NOT_EQUAL
||
854 op
== WAIT_REG_MEM_GREATER_OR_EQUAL
);
856 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, false));
857 radeon_emit(cs
, op
| WAIT_REG_MEM_MEM_SPACE(1));
859 radeon_emit(cs
, va
>> 32);
860 radeon_emit(cs
, ref
); /* reference value */
861 radeon_emit(cs
, mask
); /* mask */
862 radeon_emit(cs
, 4); /* poll interval */
866 si_emit_acquire_mem(struct radeon_cmdbuf
*cs
,
869 unsigned cp_coher_cntl
)
871 if (is_mec
|| is_gfx9
) {
872 uint32_t hi_val
= is_gfx9
? 0xffffff : 0xff;
873 radeon_emit(cs
, PKT3(PKT3_ACQUIRE_MEM
, 5, false) |
874 PKT3_SHADER_TYPE_S(is_mec
));
875 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
876 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
877 radeon_emit(cs
, hi_val
); /* CP_COHER_SIZE_HI */
878 radeon_emit(cs
, 0); /* CP_COHER_BASE */
879 radeon_emit(cs
, 0); /* CP_COHER_BASE_HI */
880 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
882 /* ACQUIRE_MEM is only required on a compute ring. */
883 radeon_emit(cs
, PKT3(PKT3_SURFACE_SYNC
, 3, false));
884 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
885 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
886 radeon_emit(cs
, 0); /* CP_COHER_BASE */
887 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
892 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
893 enum chip_class chip_class
,
897 enum radv_cmd_flush_bits flush_bits
,
898 uint64_t gfx9_eop_bug_va
)
900 uint32_t gcr_cntl
= 0;
901 unsigned cb_db_event
= 0;
903 /* We don't need these. */
904 assert(!(flush_bits
& (RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
)));
906 if (flush_bits
& RADV_CMD_FLAG_INV_ICACHE
)
907 gcr_cntl
|= S_586_GLI_INV(V_586_GLI_ALL
);
908 if (flush_bits
& RADV_CMD_FLAG_INV_SCACHE
) {
909 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
910 * to FORWARD when both L1 and L2 are written out (WB or INV).
912 gcr_cntl
|= S_586_GL1_INV(1) | S_586_GLK_INV(1);
914 if (flush_bits
& RADV_CMD_FLAG_INV_VCACHE
)
915 gcr_cntl
|= S_586_GL1_INV(1) | S_586_GLV_INV(1);
916 if (flush_bits
& RADV_CMD_FLAG_INV_L2
) {
917 /* Writeback and invalidate everything in L2. */
918 gcr_cntl
|= S_586_GL2_INV(1) | S_586_GL2_WB(1) |
919 S_586_GLM_INV(1) | S_586_GLM_WB(1);
920 } else if (flush_bits
& RADV_CMD_FLAG_WB_L2
) {
921 /* Writeback but do not invalidate.
922 * GLM doesn't support WB alone. If WB is set, INV must be set too.
924 gcr_cntl
|= S_586_GL2_WB(1) |
925 S_586_GLM_WB(1) | S_586_GLM_INV(1);
928 /* TODO: Implement this new flag for GFX9+.
929 else if (flush_bits & RADV_CMD_FLAG_INV_L2_METADATA)
930 gcr_cntl |= S_586_GLM_INV(1) | S_586_GLM_WB(1);
933 if (flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
| RADV_CMD_FLAG_FLUSH_AND_INV_DB
)) {
934 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_CB_META */
935 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_CB
) {
936 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
937 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
938 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META
) |
942 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_DB_META ? */
943 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_DB
) {
944 /* Flush HTILE. Will wait for idle later. */
945 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
946 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META
) |
950 /* First flush CB/DB, then L1/L2. */
951 gcr_cntl
|= S_586_SEQ(V_586_SEQ_FORWARD
);
953 if ((flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
| RADV_CMD_FLAG_FLUSH_AND_INV_DB
)) ==
954 (RADV_CMD_FLAG_FLUSH_AND_INV_CB
| RADV_CMD_FLAG_FLUSH_AND_INV_DB
)) {
955 cb_db_event
= V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT
;
956 } else if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_CB
) {
957 cb_db_event
= V_028A90_FLUSH_AND_INV_CB_DATA_TS
;
958 } else if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_DB
) {
959 cb_db_event
= V_028A90_FLUSH_AND_INV_DB_DATA_TS
;
964 /* Wait for graphics shaders to go idle if requested. */
965 if (flush_bits
& RADV_CMD_FLAG_PS_PARTIAL_FLUSH
) {
966 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
967 radeon_emit(cs
, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
968 } else if (flush_bits
& RADV_CMD_FLAG_VS_PARTIAL_FLUSH
) {
969 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
970 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
974 if (flush_bits
& RADV_CMD_FLAG_CS_PARTIAL_FLUSH
) {
975 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
976 radeon_emit(cs
, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH
| EVENT_INDEX(4)));
980 /* CB/DB flush and invalidate (or possibly just a wait for a
981 * meta flush) via RELEASE_MEM.
983 * Combine this with other cache flushes when possible; this
984 * requires affected shaders to be idle, so do it after the
985 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
988 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
989 unsigned glm_wb
= G_586_GLM_WB(gcr_cntl
);
990 unsigned glm_inv
= G_586_GLM_INV(gcr_cntl
);
991 unsigned glv_inv
= G_586_GLV_INV(gcr_cntl
);
992 unsigned gl1_inv
= G_586_GL1_INV(gcr_cntl
);
993 assert(G_586_GL2_US(gcr_cntl
) == 0);
994 assert(G_586_GL2_RANGE(gcr_cntl
) == 0);
995 assert(G_586_GL2_DISCARD(gcr_cntl
) == 0);
996 unsigned gl2_inv
= G_586_GL2_INV(gcr_cntl
);
997 unsigned gl2_wb
= G_586_GL2_WB(gcr_cntl
);
998 unsigned gcr_seq
= G_586_SEQ(gcr_cntl
);
1000 gcr_cntl
&= C_586_GLM_WB
&
1005 C_586_GL2_WB
; /* keep SEQ */
1010 si_cs_emit_write_event_eop(cs
, chip_class
, false, cb_db_event
,
1011 S_490_GLM_WB(glm_wb
) |
1012 S_490_GLM_INV(glm_inv
) |
1013 S_490_GLV_INV(glv_inv
) |
1014 S_490_GL1_INV(gl1_inv
) |
1015 S_490_GL2_INV(gl2_inv
) |
1016 S_490_GL2_WB(gl2_wb
) |
1019 EOP_DATA_SEL_VALUE_32BIT
,
1020 flush_va
, *flush_cnt
,
1023 radv_cp_wait_mem(cs
, WAIT_REG_MEM_EQUAL
, flush_va
,
1024 *flush_cnt
, 0xffffffff);
1027 /* VGT state sync */
1028 if (flush_bits
& RADV_CMD_FLAG_VGT_FLUSH
) {
1029 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1030 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
1033 /* Ignore fields that only modify the behavior of other fields. */
1034 if (gcr_cntl
& C_586_GL1_RANGE
& C_586_GL2_RANGE
& C_586_SEQ
) {
1035 /* Flush caches and wait for the caches to assert idle.
1036 * The cache flush is executed in the ME, but the PFP waits
1039 radeon_emit(cs
, PKT3(PKT3_ACQUIRE_MEM
, 6, 0));
1040 radeon_emit(cs
, 0); /* CP_COHER_CNTL */
1041 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
1042 radeon_emit(cs
, 0xffffff); /* CP_COHER_SIZE_HI */
1043 radeon_emit(cs
, 0); /* CP_COHER_BASE */
1044 radeon_emit(cs
, 0); /* CP_COHER_BASE_HI */
1045 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
1046 radeon_emit(cs
, gcr_cntl
); /* GCR_CNTL */
1047 } else if ((cb_db_event
||
1048 (flush_bits
& (RADV_CMD_FLAG_VS_PARTIAL_FLUSH
|
1049 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
1050 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)))
1052 /* We need to ensure that PFP waits as well. */
1053 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1057 if (flush_bits
& RADV_CMD_FLAG_START_PIPELINE_STATS
) {
1058 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1059 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_START
) |
1061 } else if (flush_bits
& RADV_CMD_FLAG_STOP_PIPELINE_STATS
) {
1062 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1063 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP
) |
1069 si_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
1070 enum chip_class chip_class
,
1071 uint32_t *flush_cnt
,
1074 enum radv_cmd_flush_bits flush_bits
,
1075 uint64_t gfx9_eop_bug_va
)
1077 unsigned cp_coher_cntl
= 0;
1078 uint32_t flush_cb_db
= flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1079 RADV_CMD_FLAG_FLUSH_AND_INV_DB
);
1081 if (chip_class
>= GFX10
) {
1082 /* GFX10 cache flush handling is quite different. */
1083 gfx10_cs_emit_cache_flush(cs
, chip_class
, flush_cnt
, flush_va
,
1084 is_mec
, flush_bits
, gfx9_eop_bug_va
);
1088 if (flush_bits
& RADV_CMD_FLAG_INV_ICACHE
)
1089 cp_coher_cntl
|= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1090 if (flush_bits
& RADV_CMD_FLAG_INV_SCACHE
)
1091 cp_coher_cntl
|= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1093 if (chip_class
<= GFX8
) {
1094 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_CB
) {
1095 cp_coher_cntl
|= S_0085F0_CB_ACTION_ENA(1) |
1096 S_0085F0_CB0_DEST_BASE_ENA(1) |
1097 S_0085F0_CB1_DEST_BASE_ENA(1) |
1098 S_0085F0_CB2_DEST_BASE_ENA(1) |
1099 S_0085F0_CB3_DEST_BASE_ENA(1) |
1100 S_0085F0_CB4_DEST_BASE_ENA(1) |
1101 S_0085F0_CB5_DEST_BASE_ENA(1) |
1102 S_0085F0_CB6_DEST_BASE_ENA(1) |
1103 S_0085F0_CB7_DEST_BASE_ENA(1);
1105 /* Necessary for DCC */
1106 if (chip_class
>= GFX8
) {
1107 si_cs_emit_write_event_eop(cs
,
1110 V_028A90_FLUSH_AND_INV_CB_DATA_TS
,
1113 EOP_DATA_SEL_DISCARD
,
1118 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_DB
) {
1119 cp_coher_cntl
|= S_0085F0_DB_ACTION_ENA(1) |
1120 S_0085F0_DB_DEST_BASE_ENA(1);
1124 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
) {
1125 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1126 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META
) | EVENT_INDEX(0));
1129 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
) {
1130 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1131 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META
) | EVENT_INDEX(0));
1134 if (flush_bits
& RADV_CMD_FLAG_PS_PARTIAL_FLUSH
) {
1135 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1136 radeon_emit(cs
, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1137 } else if (flush_bits
& RADV_CMD_FLAG_VS_PARTIAL_FLUSH
) {
1138 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1139 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1142 if (flush_bits
& RADV_CMD_FLAG_CS_PARTIAL_FLUSH
) {
1143 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1144 radeon_emit(cs
, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1147 if (chip_class
== GFX9
&& flush_cb_db
) {
1148 unsigned cb_db_event
, tc_flags
;
1150 /* Set the CB/DB flush event. */
1151 cb_db_event
= V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT
;
1153 /* These are the only allowed combinations. If you need to
1154 * do multiple operations at once, do them separately.
1155 * All operations that invalidate L2 also seem to invalidate
1156 * metadata. Volatile (VOL) and WC flushes are not listed here.
1158 * TC | TC_WB = writeback & invalidate L2 & L1
1159 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1160 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1161 * TC | TC_NC = invalidate L2 for MTYPE == NC
1162 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1163 * TCL1 = invalidate L1
1165 tc_flags
= EVENT_TC_ACTION_ENA
|
1166 EVENT_TC_MD_ACTION_ENA
;
1168 /* Ideally flush TC together with CB/DB. */
1169 if (flush_bits
& RADV_CMD_FLAG_INV_L2
) {
1170 /* Writeback and invalidate everything in L2 & L1. */
1171 tc_flags
= EVENT_TC_ACTION_ENA
|
1172 EVENT_TC_WB_ACTION_ENA
;
1175 /* Clear the flags. */
1176 flush_bits
&= ~(RADV_CMD_FLAG_INV_L2
|
1177 RADV_CMD_FLAG_WB_L2
|
1178 RADV_CMD_FLAG_INV_VCACHE
);
1183 si_cs_emit_write_event_eop(cs
, chip_class
, false, cb_db_event
, tc_flags
,
1185 EOP_DATA_SEL_VALUE_32BIT
,
1186 flush_va
, *flush_cnt
,
1188 radv_cp_wait_mem(cs
, WAIT_REG_MEM_EQUAL
, flush_va
,
1189 *flush_cnt
, 0xffffffff);
1192 /* VGT state sync */
1193 if (flush_bits
& RADV_CMD_FLAG_VGT_FLUSH
) {
1194 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1195 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
1198 /* VGT streamout state sync */
1199 if (flush_bits
& RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
) {
1200 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1201 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC
) | EVENT_INDEX(0));
1204 /* Make sure ME is idle (it executes most packets) before continuing.
1205 * This prevents read-after-write hazards between PFP and ME.
1207 if ((cp_coher_cntl
||
1208 (flush_bits
& (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
1209 RADV_CMD_FLAG_INV_VCACHE
|
1210 RADV_CMD_FLAG_INV_L2
|
1211 RADV_CMD_FLAG_WB_L2
))) &&
1213 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1217 if ((flush_bits
& RADV_CMD_FLAG_INV_L2
) ||
1218 (chip_class
<= GFX7
&& (flush_bits
& RADV_CMD_FLAG_WB_L2
))) {
1219 si_emit_acquire_mem(cs
, is_mec
, chip_class
== GFX9
,
1221 S_0085F0_TC_ACTION_ENA(1) |
1222 S_0085F0_TCL1_ACTION_ENA(1) |
1223 S_0301F0_TC_WB_ACTION_ENA(chip_class
>= GFX8
));
1226 if(flush_bits
& RADV_CMD_FLAG_WB_L2
) {
1228 * NC = apply to non-coherent MTYPEs
1229 * (i.e. MTYPE <= 1, which is what we use everywhere)
1231 * WB doesn't work without NC.
1233 si_emit_acquire_mem(cs
, is_mec
,
1236 S_0301F0_TC_WB_ACTION_ENA(1) |
1237 S_0301F0_TC_NC_ACTION_ENA(1));
1240 if (flush_bits
& RADV_CMD_FLAG_INV_VCACHE
) {
1241 si_emit_acquire_mem(cs
, is_mec
,
1244 S_0085F0_TCL1_ACTION_ENA(1));
1249 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1250 * Therefore, it should be last. Done in PFP.
1253 si_emit_acquire_mem(cs
, is_mec
, chip_class
== GFX9
, cp_coher_cntl
);
1255 if (flush_bits
& RADV_CMD_FLAG_START_PIPELINE_STATS
) {
1256 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1257 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_START
) |
1259 } else if (flush_bits
& RADV_CMD_FLAG_STOP_PIPELINE_STATS
) {
1260 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1261 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP
) |
1267 si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
)
1269 bool is_compute
= cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
;
1272 cmd_buffer
->state
.flush_bits
&= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1273 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
1274 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1275 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
|
1276 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
1277 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
|
1278 RADV_CMD_FLAG_VGT_FLUSH
|
1279 RADV_CMD_FLAG_START_PIPELINE_STATS
|
1280 RADV_CMD_FLAG_STOP_PIPELINE_STATS
);
1282 if (!cmd_buffer
->state
.flush_bits
)
1285 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 128);
1287 si_cs_emit_cache_flush(cmd_buffer
->cs
,
1288 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
1289 &cmd_buffer
->gfx9_fence_idx
,
1290 cmd_buffer
->gfx9_fence_va
,
1291 radv_cmd_buffer_uses_mec(cmd_buffer
),
1292 cmd_buffer
->state
.flush_bits
,
1293 cmd_buffer
->gfx9_eop_bug_va
);
1296 if (unlikely(cmd_buffer
->device
->trace_bo
))
1297 radv_cmd_buffer_trace_emit(cmd_buffer
);
1299 /* Clear the caches that have been flushed to avoid syncing too much
1300 * when there is some pending active queries.
1302 cmd_buffer
->active_query_flush_bits
&= ~cmd_buffer
->state
.flush_bits
;
1304 cmd_buffer
->state
.flush_bits
= 0;
1306 /* If the driver used a compute shader for resetting a query pool, it
1307 * should be finished at this point.
1309 cmd_buffer
->pending_reset_query
= false;
1312 /* sets the CP predication state using a boolean stored at va */
1314 si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
,
1315 bool draw_visible
, uint64_t va
)
1320 op
= PRED_OP(PREDICATION_OP_BOOL64
);
1322 /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
1323 * zero, all rendering commands are discarded. Otherwise, they
1324 * are discarded if the value is non zero.
1326 op
|= draw_visible
? PREDICATION_DRAW_VISIBLE
:
1327 PREDICATION_DRAW_NOT_VISIBLE
;
1329 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1330 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_SET_PREDICATION
, 2, 0));
1331 radeon_emit(cmd_buffer
->cs
, op
);
1332 radeon_emit(cmd_buffer
->cs
, va
);
1333 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1335 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_SET_PREDICATION
, 1, 0));
1336 radeon_emit(cmd_buffer
->cs
, va
);
1337 radeon_emit(cmd_buffer
->cs
, op
| ((va
>> 32) & 0xFF));
1341 /* Set this if you want the 3D engine to wait until CP DMA is done.
1342 * It should be set on the last CP DMA packet. */
1343 #define CP_DMA_SYNC (1 << 0)
1345 /* Set this if the source data was used as a destination in a previous CP DMA
1346 * packet. It's for preventing a read-after-write (RAW) hazard between two
1347 * CP DMA packets. */
1348 #define CP_DMA_RAW_WAIT (1 << 1)
1349 #define CP_DMA_USE_L2 (1 << 2)
1350 #define CP_DMA_CLEAR (1 << 3)
1352 /* Alignment for optimal performance. */
1353 #define SI_CPDMA_ALIGNMENT 32
1355 /* The max number of bytes that can be copied per packet. */
1356 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer
*cmd_buffer
)
1358 unsigned max
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
?
1359 S_414_BYTE_COUNT_GFX9(~0u) :
1360 S_414_BYTE_COUNT_GFX6(~0u);
1362 /* make it aligned for optimal performance */
1363 return max
& ~(SI_CPDMA_ALIGNMENT
- 1);
1366 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1367 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1370 static void si_emit_cp_dma(struct radv_cmd_buffer
*cmd_buffer
,
1371 uint64_t dst_va
, uint64_t src_va
,
1372 unsigned size
, unsigned flags
)
1374 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1375 uint32_t header
= 0, command
= 0;
1377 assert(size
<= cp_dma_max_byte_count(cmd_buffer
));
1379 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 9);
1380 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1381 command
|= S_414_BYTE_COUNT_GFX9(size
);
1383 command
|= S_414_BYTE_COUNT_GFX6(size
);
1386 if (flags
& CP_DMA_SYNC
)
1387 header
|= S_411_CP_SYNC(1);
1389 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1390 command
|= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1392 command
|= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1395 if (flags
& CP_DMA_RAW_WAIT
)
1396 command
|= S_414_RAW_WAIT(1);
1398 /* Src and dst flags. */
1399 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1400 !(flags
& CP_DMA_CLEAR
) &&
1402 header
|= S_411_DST_SEL(V_411_NOWHERE
); /* prefetch only */
1403 else if (flags
& CP_DMA_USE_L2
)
1404 header
|= S_411_DST_SEL(V_411_DST_ADDR_TC_L2
);
1406 if (flags
& CP_DMA_CLEAR
)
1407 header
|= S_411_SRC_SEL(V_411_DATA
);
1408 else if (flags
& CP_DMA_USE_L2
)
1409 header
|= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2
);
1411 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1412 radeon_emit(cs
, PKT3(PKT3_DMA_DATA
, 5, cmd_buffer
->state
.predicating
));
1413 radeon_emit(cs
, header
);
1414 radeon_emit(cs
, src_va
); /* SRC_ADDR_LO [31:0] */
1415 radeon_emit(cs
, src_va
>> 32); /* SRC_ADDR_HI [31:0] */
1416 radeon_emit(cs
, dst_va
); /* DST_ADDR_LO [31:0] */
1417 radeon_emit(cs
, dst_va
>> 32); /* DST_ADDR_HI [31:0] */
1418 radeon_emit(cs
, command
);
1420 assert(!(flags
& CP_DMA_USE_L2
));
1421 header
|= S_411_SRC_ADDR_HI(src_va
>> 32);
1422 radeon_emit(cs
, PKT3(PKT3_CP_DMA
, 4, cmd_buffer
->state
.predicating
));
1423 radeon_emit(cs
, src_va
); /* SRC_ADDR_LO [31:0] */
1424 radeon_emit(cs
, header
); /* SRC_ADDR_HI [15:0] + flags. */
1425 radeon_emit(cs
, dst_va
); /* DST_ADDR_LO [31:0] */
1426 radeon_emit(cs
, (dst_va
>> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1427 radeon_emit(cs
, command
);
1430 /* CP DMA is executed in ME, but index buffers are read by PFP.
1431 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1432 * indices. If we wanted to execute CP DMA in PFP, this packet
1433 * should precede it.
1435 if (flags
& CP_DMA_SYNC
) {
1436 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_GENERAL
) {
1437 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1441 /* CP will see the sync flag and wait for all DMAs to complete. */
1442 cmd_buffer
->state
.dma_is_busy
= false;
1445 if (unlikely(cmd_buffer
->device
->trace_bo
))
1446 radv_cmd_buffer_trace_emit(cmd_buffer
);
1449 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1452 uint64_t aligned_va
= va
& ~(SI_CPDMA_ALIGNMENT
- 1);
1453 uint64_t aligned_size
= ((va
+ size
+ SI_CPDMA_ALIGNMENT
-1) & ~(SI_CPDMA_ALIGNMENT
- 1)) - aligned_va
;
1455 si_emit_cp_dma(cmd_buffer
, aligned_va
, aligned_va
,
1456 aligned_size
, CP_DMA_USE_L2
);
1459 static void si_cp_dma_prepare(struct radv_cmd_buffer
*cmd_buffer
, uint64_t byte_count
,
1460 uint64_t remaining_size
, unsigned *flags
)
1463 /* Flush the caches for the first copy only.
1464 * Also wait for the previous CP DMA operations.
1466 if (cmd_buffer
->state
.flush_bits
) {
1467 si_emit_cache_flush(cmd_buffer
);
1468 *flags
|= CP_DMA_RAW_WAIT
;
1471 /* Do the synchronization after the last dma, so that all data
1472 * is written to memory.
1474 if (byte_count
== remaining_size
)
1475 *flags
|= CP_DMA_SYNC
;
1478 static void si_cp_dma_realign_engine(struct radv_cmd_buffer
*cmd_buffer
, unsigned size
)
1482 unsigned dma_flags
= 0;
1483 unsigned buf_size
= SI_CPDMA_ALIGNMENT
* 2;
1486 assert(size
< SI_CPDMA_ALIGNMENT
);
1488 radv_cmd_buffer_upload_alloc(cmd_buffer
, buf_size
, SI_CPDMA_ALIGNMENT
, &offset
, &ptr
);
1490 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1493 si_cp_dma_prepare(cmd_buffer
, size
, size
, &dma_flags
);
1495 si_emit_cp_dma(cmd_buffer
, va
, va
+ SI_CPDMA_ALIGNMENT
, size
,
1499 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1500 uint64_t src_va
, uint64_t dest_va
,
1503 uint64_t main_src_va
, main_dest_va
;
1504 uint64_t skipped_size
= 0, realign_size
= 0;
1506 /* Assume that we are not going to sync after the last DMA operation. */
1507 cmd_buffer
->state
.dma_is_busy
= true;
1509 if (cmd_buffer
->device
->physical_device
->rad_info
.family
<= CHIP_CARRIZO
||
1510 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_STONEY
) {
1511 /* If the size is not aligned, we must add a dummy copy at the end
1512 * just to align the internal counter. Otherwise, the DMA engine
1513 * would slow down by an order of magnitude for following copies.
1515 if (size
% SI_CPDMA_ALIGNMENT
)
1516 realign_size
= SI_CPDMA_ALIGNMENT
- (size
% SI_CPDMA_ALIGNMENT
);
1518 /* If the copy begins unaligned, we must start copying from the next
1519 * aligned block and the skipped part should be copied after everything
1520 * else has been copied. Only the src alignment matters, not dst.
1522 if (src_va
% SI_CPDMA_ALIGNMENT
) {
1523 skipped_size
= SI_CPDMA_ALIGNMENT
- (src_va
% SI_CPDMA_ALIGNMENT
);
1524 /* The main part will be skipped if the size is too small. */
1525 skipped_size
= MIN2(skipped_size
, size
);
1526 size
-= skipped_size
;
1529 main_src_va
= src_va
+ skipped_size
;
1530 main_dest_va
= dest_va
+ skipped_size
;
1533 unsigned dma_flags
= 0;
1534 unsigned byte_count
= MIN2(size
, cp_dma_max_byte_count(cmd_buffer
));
1536 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
1537 /* DMA operations via L2 are coherent and faster.
1538 * TODO: GFX7-GFX9 should also support this but it
1539 * requires tests/benchmarks.
1541 dma_flags
|= CP_DMA_USE_L2
;
1544 si_cp_dma_prepare(cmd_buffer
, byte_count
,
1545 size
+ skipped_size
+ realign_size
,
1548 dma_flags
&= ~CP_DMA_SYNC
;
1550 si_emit_cp_dma(cmd_buffer
, main_dest_va
, main_src_va
,
1551 byte_count
, dma_flags
);
1554 main_src_va
+= byte_count
;
1555 main_dest_va
+= byte_count
;
1559 unsigned dma_flags
= 0;
1561 si_cp_dma_prepare(cmd_buffer
, skipped_size
,
1562 size
+ skipped_size
+ realign_size
,
1565 si_emit_cp_dma(cmd_buffer
, dest_va
, src_va
,
1566 skipped_size
, dma_flags
);
1569 si_cp_dma_realign_engine(cmd_buffer
, realign_size
);
1572 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1573 uint64_t size
, unsigned value
)
1579 assert(va
% 4 == 0 && size
% 4 == 0);
1581 /* Assume that we are not going to sync after the last DMA operation. */
1582 cmd_buffer
->state
.dma_is_busy
= true;
1585 unsigned byte_count
= MIN2(size
, cp_dma_max_byte_count(cmd_buffer
));
1586 unsigned dma_flags
= CP_DMA_CLEAR
;
1588 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
1589 /* DMA operations via L2 are coherent and faster.
1590 * TODO: GFX7-GFX9 should also support this but it
1591 * requires tests/benchmarks.
1593 dma_flags
|= CP_DMA_USE_L2
;
1596 si_cp_dma_prepare(cmd_buffer
, byte_count
, size
, &dma_flags
);
1598 /* Emit the clear packet. */
1599 si_emit_cp_dma(cmd_buffer
, va
, value
, byte_count
,
1607 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer
*cmd_buffer
)
1609 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
< GFX7
)
1612 if (!cmd_buffer
->state
.dma_is_busy
)
1615 /* Issue a dummy DMA that copies zero bytes.
1617 * The DMA engine will see that there's no work to do and skip this
1618 * DMA request, however, the CP will see the sync flag and still wait
1619 * for all DMAs to complete.
1621 si_emit_cp_dma(cmd_buffer
, 0, 0, 0, CP_DMA_SYNC
);
1623 cmd_buffer
->state
.dma_is_busy
= false;
1626 /* For MSAA sample positions. */
1627 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1628 ((((unsigned)(s0x) & 0xf) << 0) | (((unsigned)(s0y) & 0xf) << 4) | \
1629 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1630 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1631 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1633 /* For obtaining location coordinates from registers */
1634 #define SEXT4(x) ((int)((x) | ((x) & 0x8 ? 0xfffffff0 : 0)))
1635 #define GET_SFIELD(reg, index) SEXT4(((reg) >> ((index) * 4)) & 0xf)
1636 #define GET_SX(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2)
1637 #define GET_SY(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2 + 1)
1640 static const uint32_t sample_locs_1x
=
1641 FILL_SREG(0, 0, 0, 0, 0, 0, 0, 0);
1642 static const unsigned max_dist_1x
= 0;
1643 static const uint64_t centroid_priority_1x
= 0x0000000000000000ull
;
1646 static const uint32_t sample_locs_2x
=
1647 FILL_SREG(4,4, -4, -4, 0, 0, 0, 0);
1648 static const unsigned max_dist_2x
= 4;
1649 static const uint64_t centroid_priority_2x
= 0x1010101010101010ull
;
1652 static const uint32_t sample_locs_4x
=
1653 FILL_SREG(-2,-6, 6, -2, -6, 2, 2, 6);
1654 static const unsigned max_dist_4x
= 6;
1655 static const uint64_t centroid_priority_4x
= 0x3210321032103210ull
;
1658 static const uint32_t sample_locs_8x
[] = {
1659 FILL_SREG( 1,-3, -1, 3, 5, 1, -3,-5),
1660 FILL_SREG(-5, 5, -7,-1, 3, 7, 7,-7),
1661 /* The following are unused by hardware, but we emit them to IBs
1662 * instead of multiple SET_CONTEXT_REG packets. */
1666 static const unsigned max_dist_8x
= 7;
1667 static const uint64_t centroid_priority_8x
= 0x7654321076543210ull
;
1669 unsigned radv_get_default_max_sample_dist(int log_samples
)
1671 unsigned max_dist
[] = {
1677 return max_dist
[log_samples
];
1680 void radv_emit_default_sample_locations(struct radeon_cmdbuf
*cs
, int nr_samples
)
1682 switch (nr_samples
) {
1685 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
1686 radeon_emit(cs
, (uint32_t)centroid_priority_1x
);
1687 radeon_emit(cs
, centroid_priority_1x
>> 32);
1688 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_1x
);
1689 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_1x
);
1690 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_1x
);
1691 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_1x
);
1694 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
1695 radeon_emit(cs
, (uint32_t)centroid_priority_2x
);
1696 radeon_emit(cs
, centroid_priority_2x
>> 32);
1697 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_2x
);
1698 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_2x
);
1699 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_2x
);
1700 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_2x
);
1703 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
1704 radeon_emit(cs
, (uint32_t)centroid_priority_4x
);
1705 radeon_emit(cs
, centroid_priority_4x
>> 32);
1706 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_4x
);
1707 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_4x
);
1708 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_4x
);
1709 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_4x
);
1712 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
1713 radeon_emit(cs
, (uint32_t)centroid_priority_8x
);
1714 radeon_emit(cs
, centroid_priority_8x
>> 32);
1715 radeon_set_context_reg_seq(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 14);
1716 radeon_emit_array(cs
, sample_locs_8x
, 4);
1717 radeon_emit_array(cs
, sample_locs_8x
, 4);
1718 radeon_emit_array(cs
, sample_locs_8x
, 4);
1719 radeon_emit_array(cs
, sample_locs_8x
, 2);
1724 static void radv_get_sample_position(struct radv_device
*device
,
1725 unsigned sample_count
,
1726 unsigned sample_index
, float *out_value
)
1728 const uint32_t *sample_locs
;
1730 switch (sample_count
) {
1733 sample_locs
= &sample_locs_1x
;
1736 sample_locs
= &sample_locs_2x
;
1739 sample_locs
= &sample_locs_4x
;
1742 sample_locs
= sample_locs_8x
;
1746 out_value
[0] = (GET_SX(sample_locs
, sample_index
) + 8) / 16.0f
;
1747 out_value
[1] = (GET_SY(sample_locs
, sample_index
) + 8) / 16.0f
;
1750 void radv_device_init_msaa(struct radv_device
*device
)
1754 radv_get_sample_position(device
, 1, 0, device
->sample_locations_1x
[0]);
1756 for (i
= 0; i
< 2; i
++)
1757 radv_get_sample_position(device
, 2, i
, device
->sample_locations_2x
[i
]);
1758 for (i
= 0; i
< 4; i
++)
1759 radv_get_sample_position(device
, 4, i
, device
->sample_locations_4x
[i
]);
1760 for (i
= 0; i
< 8; i
++)
1761 radv_get_sample_position(device
, 8, i
, device
->sample_locations_8x
[i
]);