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ac/radv/radeonsi: refactor raster_config default values getters.
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for SI */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "gfx9d.h"
35 #include "radv_util.h"
36 #include "main/macros.h"
37
38 static void
39 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
40 struct radeon_winsys_cs *cs,
41 unsigned raster_config,
42 unsigned raster_config_1)
43 {
44 unsigned sh_per_se = MAX2(physical_device->rad_info.max_sh_per_se, 1);
45 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
46 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
47 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
48 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
49 unsigned rb_per_se = num_rb / num_se;
50 unsigned se_mask[4];
51 unsigned se;
52
53 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
54 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
55 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
56 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
57
58 assert(num_se == 1 || num_se == 2 || num_se == 4);
59 assert(sh_per_se == 1 || sh_per_se == 2);
60 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
61
62 /* XXX: I can't figure out what the *_XSEL and *_YSEL
63 * fields are for, so I'm leaving them as their default
64 * values. */
65
66 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
67 (!se_mask[2] && !se_mask[3]))) {
68 raster_config_1 &= C_028354_SE_PAIR_MAP;
69
70 if (!se_mask[0] && !se_mask[1]) {
71 raster_config_1 |=
72 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
73 } else {
74 raster_config_1 |=
75 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
76 }
77 }
78
79 for (se = 0; se < num_se; se++) {
80 unsigned raster_config_se = raster_config;
81 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
82 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
83 int idx = (se / 2) * 2;
84
85 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
86 raster_config_se &= C_028350_SE_MAP;
87
88 if (!se_mask[idx]) {
89 raster_config_se |=
90 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
91 } else {
92 raster_config_se |=
93 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
94 }
95 }
96
97 pkr0_mask &= rb_mask;
98 pkr1_mask &= rb_mask;
99 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
100 raster_config_se &= C_028350_PKR_MAP;
101
102 if (!pkr0_mask) {
103 raster_config_se |=
104 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
105 } else {
106 raster_config_se |=
107 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
108 }
109 }
110
111 if (rb_per_se >= 2) {
112 unsigned rb0_mask = 1 << (se * rb_per_se);
113 unsigned rb1_mask = rb0_mask << 1;
114
115 rb0_mask &= rb_mask;
116 rb1_mask &= rb_mask;
117 if (!rb0_mask || !rb1_mask) {
118 raster_config_se &= C_028350_RB_MAP_PKR0;
119
120 if (!rb0_mask) {
121 raster_config_se |=
122 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
123 } else {
124 raster_config_se |=
125 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
126 }
127 }
128
129 if (rb_per_se > 2) {
130 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
131 rb1_mask = rb0_mask << 1;
132 rb0_mask &= rb_mask;
133 rb1_mask &= rb_mask;
134 if (!rb0_mask || !rb1_mask) {
135 raster_config_se &= C_028350_RB_MAP_PKR1;
136
137 if (!rb0_mask) {
138 raster_config_se |=
139 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
140 } else {
141 raster_config_se |=
142 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
143 }
144 }
145 }
146 }
147
148 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
149 if (physical_device->rad_info.chip_class < CIK)
150 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
151 S_00802C_SE_INDEX(se) |
152 S_00802C_SH_BROADCAST_WRITES(1) |
153 S_00802C_INSTANCE_BROADCAST_WRITES(1));
154 else
155 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
156 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
157 S_030800_INSTANCE_BROADCAST_WRITES(1));
158 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
159 if (physical_device->rad_info.chip_class >= CIK)
160 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
161 }
162
163 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
164 if (physical_device->rad_info.chip_class < CIK)
165 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
166 S_00802C_SE_BROADCAST_WRITES(1) |
167 S_00802C_SH_BROADCAST_WRITES(1) |
168 S_00802C_INSTANCE_BROADCAST_WRITES(1));
169 else
170 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
171 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
172 S_030800_INSTANCE_BROADCAST_WRITES(1));
173 }
174
175 static void
176 si_emit_compute(struct radv_physical_device *physical_device,
177 struct radeon_winsys_cs *cs)
178 {
179 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
180 radeon_emit(cs, 0);
181 radeon_emit(cs, 0);
182 radeon_emit(cs, 0);
183
184 radeon_set_sh_reg_seq(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
185 S_00B854_WAVES_PER_SH(0x3));
186 radeon_emit(cs, 0);
187 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
188 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
189 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
190
191 if (physical_device->rad_info.chip_class >= CIK) {
192 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
193 radeon_set_sh_reg_seq(cs,
194 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
195 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
196 S_00B864_SH1_CU_EN(0xffff));
197 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
198 S_00B868_SH1_CU_EN(0xffff));
199 }
200
201 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
202 * and is now per pipe, so it should be handled in the
203 * kernel if we want to use something other than the default value,
204 * which is now 0x22f.
205 */
206 if (physical_device->rad_info.chip_class <= SI) {
207 /* XXX: This should be:
208 * (number of compute units) * 4 * (waves per simd) - 1 */
209
210 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
211 0x190 /* Default value */);
212 }
213 }
214
215 void
216 si_init_compute(struct radv_cmd_buffer *cmd_buffer)
217 {
218 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
219 si_emit_compute(physical_device, cmd_buffer->cs);
220 }
221
222 /* 12.4 fixed-point */
223 static unsigned radv_pack_float_12p4(float x)
224 {
225 return x <= 0 ? 0 :
226 x >= 4096 ? 0xffff : x * 16;
227 }
228
229 static void
230 si_set_raster_config(struct radv_physical_device *physical_device,
231 struct radeon_winsys_cs *cs)
232 {
233 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
234 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
235 unsigned raster_config, raster_config_1;
236
237 ac_get_raster_config(&physical_device->rad_info,
238 &raster_config,
239 &raster_config_1);
240
241 /* Always use the default config when all backends are enabled
242 * (or when we failed to determine the enabled backends).
243 */
244 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
245 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
246 raster_config);
247 if (physical_device->rad_info.chip_class >= CIK)
248 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
249 raster_config_1);
250 } else {
251 si_write_harvested_raster_configs(physical_device, cs,
252 raster_config,
253 raster_config_1);
254 }
255 }
256
257 static void
258 si_emit_config(struct radv_physical_device *physical_device,
259 struct radeon_winsys_cs *cs)
260 {
261 int i;
262
263 /* Only SI can disable CLEAR_STATE for now. */
264 assert(physical_device->has_clear_state ||
265 physical_device->rad_info.chip_class == SI);
266
267 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
268 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
269 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
270
271 if (physical_device->has_clear_state) {
272 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
273 radeon_emit(cs, 0);
274 }
275
276 if (physical_device->rad_info.chip_class <= VI)
277 si_set_raster_config(physical_device, cs);
278
279 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
280 if (!physical_device->has_clear_state)
281 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
282
283 /* FIXME calculate these values somehow ??? */
284 if (physical_device->rad_info.chip_class <= VI) {
285 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
286 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
287 }
288
289 if (!physical_device->has_clear_state) {
290 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
291 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
292 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
293 }
294
295 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
296 if (!physical_device->has_clear_state)
297 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
298 if (physical_device->rad_info.chip_class < CIK)
299 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
300 S_008A14_CLIP_VTX_REORDER_ENA(1));
301
302 radeon_set_context_reg(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
303 radeon_set_context_reg(cs, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
304
305 if (!physical_device->has_clear_state)
306 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
307
308 /* CLEAR_STATE doesn't clear these correctly on certain generations.
309 * I don't know why. Deduced by trial and error.
310 */
311 if (physical_device->rad_info.chip_class <= CIK) {
312 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
313 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
314 S_028204_WINDOW_OFFSET_DISABLE(1));
315 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
316 S_028240_WINDOW_OFFSET_DISABLE(1));
317 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
318 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
319 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
320 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
321 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
322 }
323
324 if (!physical_device->has_clear_state) {
325 for (i = 0; i < 16; i++) {
326 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
327 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
328 }
329 }
330
331 if (!physical_device->has_clear_state) {
332 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
333 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
334 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
335 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
336 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
337 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
338 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
339 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
340 }
341
342 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
343 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
344 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
345
346 if (physical_device->rad_info.chip_class >= GFX9) {
347 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
348 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
349 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
350 } else {
351 /* These registers, when written, also overwrite the
352 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
353 * them. It would be an issue if there was another UMD
354 * changing them.
355 */
356 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
357 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
358 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
359 }
360
361 if (physical_device->rad_info.chip_class >= CIK) {
362 if (physical_device->rad_info.chip_class >= GFX9) {
363 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
364 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
365 } else {
366 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
367 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
368 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
369 S_00B41C_WAVE_LIMIT(0x3F));
370 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
371 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
372 /* If this is 0, Bonaire can hang even if GS isn't being used.
373 * Other chips are unaffected. These are suboptimal values,
374 * but we don't use on-chip GS.
375 */
376 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
377 S_028A44_ES_VERTS_PER_SUBGRP(64) |
378 S_028A44_GS_PRIMS_PER_SUBGRP(4));
379 }
380 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
381 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
382
383 if (physical_device->rad_info.num_good_compute_units /
384 (physical_device->rad_info.max_se * physical_device->rad_info.max_sh_per_se) <= 4) {
385 /* Too few available compute units per SH. Disallowing
386 * VS to run on CU0 could hurt us more than late VS
387 * allocation would help.
388 *
389 * LATE_ALLOC_VS = 2 is the highest safe number.
390 */
391 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
392 S_00B118_CU_EN(0xffff) | S_00B118_WAVE_LIMIT(0x3F) );
393 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
394 } else {
395 /* Set LATE_ALLOC_VS == 31. It should be less than
396 * the number of scratch waves. Limitations:
397 * - VS can't execute on CU0.
398 * - If HS writes outputs to LDS, LS can't execute on CU0.
399 */
400 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
401 S_00B118_CU_EN(0xfffe) | S_00B118_WAVE_LIMIT(0x3F));
402 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
403 }
404
405 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
406 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
407 }
408
409 if (physical_device->rad_info.chip_class >= VI) {
410 uint32_t vgt_tess_distribution;
411 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
412 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
413 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
414
415 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
416 S_028B50_ACCUM_TRI(11) |
417 S_028B50_ACCUM_QUAD(11) |
418 S_028B50_DONUT_SPLIT(16);
419
420 if (physical_device->rad_info.family == CHIP_FIJI ||
421 physical_device->rad_info.family >= CHIP_POLARIS10)
422 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
423
424 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
425 vgt_tess_distribution);
426 } else if (!physical_device->has_clear_state) {
427 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
428 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
429 }
430
431 if (physical_device->rad_info.chip_class >= GFX9) {
432 unsigned num_se = physical_device->rad_info.max_se;
433 unsigned pc_lines = 0;
434
435 switch (physical_device->rad_info.family) {
436 case CHIP_VEGA10:
437 case CHIP_VEGA12:
438 pc_lines = 4096;
439 break;
440 case CHIP_RAVEN:
441 pc_lines = 1024;
442 break;
443 default:
444 assert(0);
445 }
446
447 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
448 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
449 S_028C48_MAX_PRIM_PER_BATCH(1023));
450 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
451 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
452 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
453 }
454
455 unsigned tmp = (unsigned)(1.0 * 8.0);
456 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
457 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
458 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
459 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
460 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
461
462 if (!physical_device->has_clear_state) {
463 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
464 S_028004_ZPASS_INCREMENT_DISABLE(1));
465 }
466
467 /* Enable the Polaris small primitive filter control.
468 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
469 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
470 * and AMDVLK doesn't have a workaround as well.
471 */
472 if (physical_device->rad_info.family >= CHIP_POLARIS10) {
473 unsigned small_prim_filter_cntl =
474 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
475 /* Workaround for a hw line bug. */
476 S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12);
477
478 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
479 small_prim_filter_cntl);
480 }
481
482 si_emit_compute(physical_device, cs);
483 }
484
485 void si_init_config(struct radv_cmd_buffer *cmd_buffer)
486 {
487 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
488
489 si_emit_config(physical_device, cmd_buffer->cs);
490 }
491
492 void
493 cik_create_gfx_config(struct radv_device *device)
494 {
495 struct radeon_winsys_cs *cs = device->ws->cs_create(device->ws, RING_GFX);
496 if (!cs)
497 return;
498
499 si_emit_config(device->physical_device, cs);
500
501 while (cs->cdw & 7) {
502 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
503 radeon_emit(cs, 0x80000000);
504 else
505 radeon_emit(cs, 0xffff1000);
506 }
507
508 device->gfx_init = device->ws->buffer_create(device->ws,
509 cs->cdw * 4, 4096,
510 RADEON_DOMAIN_GTT,
511 RADEON_FLAG_CPU_ACCESS|
512 RADEON_FLAG_NO_INTERPROCESS_SHARING |
513 RADEON_FLAG_READ_ONLY);
514 if (!device->gfx_init)
515 goto fail;
516
517 void *map = device->ws->buffer_map(device->gfx_init);
518 if (!map) {
519 device->ws->buffer_destroy(device->gfx_init);
520 device->gfx_init = NULL;
521 goto fail;
522 }
523 memcpy(map, cs->buf, cs->cdw * 4);
524
525 device->ws->buffer_unmap(device->gfx_init);
526 device->gfx_init_size_dw = cs->cdw;
527 fail:
528 device->ws->cs_destroy(cs);
529 }
530
531 static void
532 get_viewport_xform(const VkViewport *viewport,
533 float scale[3], float translate[3])
534 {
535 float x = viewport->x;
536 float y = viewport->y;
537 float half_width = 0.5f * viewport->width;
538 float half_height = 0.5f * viewport->height;
539 double n = viewport->minDepth;
540 double f = viewport->maxDepth;
541
542 scale[0] = half_width;
543 translate[0] = half_width + x;
544 scale[1] = half_height;
545 translate[1] = half_height + y;
546
547 scale[2] = (f - n);
548 translate[2] = n;
549 }
550
551 void
552 si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
553 int count, const VkViewport *viewports)
554 {
555 int i;
556
557 assert(count);
558 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
559 first_vp * 4 * 6, count * 6);
560
561 for (i = 0; i < count; i++) {
562 float scale[3], translate[3];
563
564
565 get_viewport_xform(&viewports[i], scale, translate);
566 radeon_emit(cs, fui(scale[0]));
567 radeon_emit(cs, fui(translate[0]));
568 radeon_emit(cs, fui(scale[1]));
569 radeon_emit(cs, fui(translate[1]));
570 radeon_emit(cs, fui(scale[2]));
571 radeon_emit(cs, fui(translate[2]));
572 }
573
574 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
575 first_vp * 4 * 2, count * 2);
576 for (i = 0; i < count; i++) {
577 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
578 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
579 radeon_emit(cs, fui(zmin));
580 radeon_emit(cs, fui(zmax));
581 }
582 }
583
584 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
585 {
586 float scale[3], translate[3];
587 VkRect2D rect;
588
589 get_viewport_xform(viewport, scale, translate);
590
591 rect.offset.x = translate[0] - fabs(scale[0]);
592 rect.offset.y = translate[1] - fabs(scale[1]);
593 rect.extent.width = ceilf(translate[0] + fabs(scale[0])) - rect.offset.x;
594 rect.extent.height = ceilf(translate[1] + fabs(scale[1])) - rect.offset.y;
595
596 return rect;
597 }
598
599 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
600 VkRect2D ret;
601 ret.offset.x = MAX2(a->offset.x, b->offset.x);
602 ret.offset.y = MAX2(a->offset.y, b->offset.y);
603 ret.extent.width = MIN2(a->offset.x + a->extent.width,
604 b->offset.x + b->extent.width) - ret.offset.x;
605 ret.extent.height = MIN2(a->offset.y + a->extent.height,
606 b->offset.y + b->extent.height) - ret.offset.y;
607 return ret;
608 }
609
610 void
611 si_write_scissors(struct radeon_winsys_cs *cs, int first,
612 int count, const VkRect2D *scissors,
613 const VkViewport *viewports, bool can_use_guardband)
614 {
615 int i;
616 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
617 const float max_range = 32767.0f;
618 if (!count)
619 return;
620
621 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
622 for (i = 0; i < count; i++) {
623 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
624 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
625
626 get_viewport_xform(viewports + i, scale, translate);
627 scale[0] = abs(scale[0]);
628 scale[1] = abs(scale[1]);
629
630 if (scale[0] < 0.5)
631 scale[0] = 0.5;
632 if (scale[1] < 0.5)
633 scale[1] = 0.5;
634
635 guardband_x = MIN2(guardband_x, (max_range - abs(translate[0])) / scale[0]);
636 guardband_y = MIN2(guardband_y, (max_range - abs(translate[1])) / scale[1]);
637
638 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
639 S_028250_TL_Y(scissor.offset.y) |
640 S_028250_WINDOW_OFFSET_DISABLE(1));
641 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
642 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
643 }
644 if (!can_use_guardband) {
645 guardband_x = 1.0;
646 guardband_y = 1.0;
647 }
648
649 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
650 radeon_emit(cs, fui(guardband_y));
651 radeon_emit(cs, fui(1.0));
652 radeon_emit(cs, fui(guardband_x));
653 radeon_emit(cs, fui(1.0));
654 }
655
656 static inline unsigned
657 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
658 {
659 if (num == 0)
660 return 0;
661
662 if (info->incr == 0)
663 return 0;
664
665 if (num < info->min)
666 return 0;
667
668 return 1 + ((num - info->min) / info->incr);
669 }
670
671 uint32_t
672 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
673 bool instanced_draw, bool indirect_draw,
674 uint32_t draw_vertex_count)
675 {
676 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
677 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
678 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
679 const unsigned max_primgroup_in_wave = 2;
680 /* SWITCH_ON_EOP(0) is always preferable. */
681 bool wd_switch_on_eop = false;
682 bool ia_switch_on_eop = false;
683 bool ia_switch_on_eoi = false;
684 bool partial_vs_wave = false;
685 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave;
686 bool multi_instances_smaller_than_primgroup;
687
688 multi_instances_smaller_than_primgroup = indirect_draw;
689 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
690 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
691 if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size)
692 multi_instances_smaller_than_primgroup = true;
693 }
694
695 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
696 partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
697
698 if (chip_class >= CIK) {
699 wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.wd_switch_on_eop;
700
701 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
702 * We don't know that for indirect drawing, so treat it as
703 * always problematic. */
704 if (family == CHIP_HAWAII &&
705 (instanced_draw || indirect_draw))
706 wd_switch_on_eop = true;
707
708 /* Performance recommendation for 4 SE Gfx7-8 parts if
709 * instances are smaller than a primgroup.
710 * Assume indirect draws always use small instances.
711 * This is needed for good VS wave utilization.
712 */
713 if (chip_class <= VI &&
714 info->max_se == 4 &&
715 multi_instances_smaller_than_primgroup)
716 wd_switch_on_eop = true;
717
718 /* Required on CIK and later. */
719 if (info->max_se > 2 && !wd_switch_on_eop)
720 ia_switch_on_eoi = true;
721
722 /* Required by Hawaii and, for some special cases, by VI. */
723 if (ia_switch_on_eoi &&
724 (family == CHIP_HAWAII ||
725 (chip_class == VI &&
726 /* max primgroup in wave is always 2 - leave this for documentation */
727 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
728 partial_vs_wave = true;
729
730 /* Instancing bug on Bonaire. */
731 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
732 (instanced_draw || indirect_draw))
733 partial_vs_wave = true;
734
735 /* If the WD switch is false, the IA switch must be false too. */
736 assert(wd_switch_on_eop || !ia_switch_on_eop);
737 }
738 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
739 if (chip_class <= VI && ia_switch_on_eoi)
740 partial_es_wave = true;
741
742 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
743 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
744 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
745 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
746 */
747 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
748 bool set_vgt_flush = indirect_draw;
749 if (!set_vgt_flush && instanced_draw) {
750 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
751 if (num_prims <= 1)
752 set_vgt_flush = true;
753 }
754 if (set_vgt_flush)
755 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
756 }
757 }
758
759 return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base |
760 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
761 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
762 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
763 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
764 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop : 0);
765
766 }
767
768 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
769 bool predicated,
770 enum chip_class chip_class,
771 bool is_mec,
772 unsigned event, unsigned event_flags,
773 unsigned data_sel,
774 uint64_t va,
775 uint32_t old_fence,
776 uint32_t new_fence)
777 {
778 unsigned op = EVENT_TYPE(event) |
779 EVENT_INDEX(5) |
780 event_flags;
781 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
782
783 if (chip_class >= GFX9 || is_gfx8_mec) {
784 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, predicated));
785 radeon_emit(cs, op);
786 radeon_emit(cs, EOP_DATA_SEL(data_sel));
787 radeon_emit(cs, va); /* address lo */
788 radeon_emit(cs, va >> 32); /* address hi */
789 radeon_emit(cs, new_fence); /* immediate data lo */
790 radeon_emit(cs, 0); /* immediate data hi */
791 if (!is_gfx8_mec)
792 radeon_emit(cs, 0); /* unused */
793 } else {
794 if (chip_class == CIK ||
795 chip_class == VI) {
796 /* Two EOP events are required to make all engines go idle
797 * (and optional cache flushes executed) before the timestamp
798 * is written.
799 */
800 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated));
801 radeon_emit(cs, op);
802 radeon_emit(cs, va);
803 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
804 radeon_emit(cs, old_fence); /* immediate data */
805 radeon_emit(cs, 0); /* unused */
806 }
807
808 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated));
809 radeon_emit(cs, op);
810 radeon_emit(cs, va);
811 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
812 radeon_emit(cs, new_fence); /* immediate data */
813 radeon_emit(cs, 0); /* unused */
814 }
815 }
816
817 void
818 si_emit_wait_fence(struct radeon_winsys_cs *cs,
819 bool predicated,
820 uint64_t va, uint32_t ref,
821 uint32_t mask)
822 {
823 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, predicated));
824 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
825 radeon_emit(cs, va);
826 radeon_emit(cs, va >> 32);
827 radeon_emit(cs, ref); /* reference value */
828 radeon_emit(cs, mask); /* mask */
829 radeon_emit(cs, 4); /* poll interval */
830 }
831
832 static void
833 si_emit_acquire_mem(struct radeon_winsys_cs *cs,
834 bool is_mec,
835 bool predicated,
836 bool is_gfx9,
837 unsigned cp_coher_cntl)
838 {
839 if (is_mec || is_gfx9) {
840 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
841 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, predicated) |
842 PKT3_SHADER_TYPE_S(is_mec));
843 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
844 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
845 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
846 radeon_emit(cs, 0); /* CP_COHER_BASE */
847 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
848 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
849 } else {
850 /* ACQUIRE_MEM is only required on a compute ring. */
851 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, predicated));
852 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
853 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
854 radeon_emit(cs, 0); /* CP_COHER_BASE */
855 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
856 }
857 }
858
859 void
860 si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
861 enum chip_class chip_class,
862 uint32_t *flush_cnt,
863 uint64_t flush_va,
864 bool is_mec,
865 enum radv_cmd_flush_bits flush_bits)
866 {
867 unsigned cp_coher_cntl = 0;
868 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
869 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
870
871 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
872 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
873 if (flush_bits & RADV_CMD_FLAG_INV_SMEM_L1)
874 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
875
876 if (chip_class <= VI) {
877 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
878 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
879 S_0085F0_CB0_DEST_BASE_ENA(1) |
880 S_0085F0_CB1_DEST_BASE_ENA(1) |
881 S_0085F0_CB2_DEST_BASE_ENA(1) |
882 S_0085F0_CB3_DEST_BASE_ENA(1) |
883 S_0085F0_CB4_DEST_BASE_ENA(1) |
884 S_0085F0_CB5_DEST_BASE_ENA(1) |
885 S_0085F0_CB6_DEST_BASE_ENA(1) |
886 S_0085F0_CB7_DEST_BASE_ENA(1);
887
888 /* Necessary for DCC */
889 if (chip_class >= VI) {
890 si_cs_emit_write_event_eop(cs,
891 false,
892 chip_class,
893 is_mec,
894 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
895 0, 0, 0, 0, 0);
896 }
897 }
898 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
899 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
900 S_0085F0_DB_DEST_BASE_ENA(1);
901 }
902 }
903
904 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
905 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
906 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
907 }
908
909 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
910 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
911 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
912 }
913
914 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
915 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
916 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
917 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
918 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
919 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
920 }
921
922 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
923 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
924 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
925 }
926
927 if (chip_class >= GFX9 && flush_cb_db) {
928 unsigned cb_db_event, tc_flags;
929
930 #if 0
931 /* This breaks a bunch of:
932 dEQP-VK.renderpass.dedicated_allocation.formats.d32_sfloat_s8_uint.input*.
933 use the big hammer always.
934 */
935 /* Set the CB/DB flush event. */
936 switch (flush_cb_db) {
937 case RADV_CMD_FLAG_FLUSH_AND_INV_CB:
938 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
939 break;
940 case RADV_CMD_FLAG_FLUSH_AND_INV_DB:
941 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
942 break;
943 default:
944 /* both CB & DB */
945 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
946 }
947 #else
948 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
949 #endif
950 /* These are the only allowed combinations. If you need to
951 * do multiple operations at once, do them separately.
952 * All operations that invalidate L2 also seem to invalidate
953 * metadata. Volatile (VOL) and WC flushes are not listed here.
954 *
955 * TC | TC_WB = writeback & invalidate L2 & L1
956 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
957 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
958 * TC | TC_NC = invalidate L2 for MTYPE == NC
959 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
960 * TCL1 = invalidate L1
961 */
962 tc_flags = EVENT_TC_ACTION_ENA |
963 EVENT_TC_MD_ACTION_ENA;
964
965 /* Ideally flush TC together with CB/DB. */
966 if (flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) {
967 /* Writeback and invalidate everything in L2 & L1. */
968 tc_flags = EVENT_TC_ACTION_ENA |
969 EVENT_TC_WB_ACTION_ENA;
970
971
972 /* Clear the flags. */
973 flush_bits &= ~(RADV_CMD_FLAG_INV_GLOBAL_L2 |
974 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 |
975 RADV_CMD_FLAG_INV_VMEM_L1);
976 }
977 assert(flush_cnt);
978 uint32_t old_fence = (*flush_cnt)++;
979
980 si_cs_emit_write_event_eop(cs, false, chip_class, false, cb_db_event, tc_flags, 1,
981 flush_va, old_fence, *flush_cnt);
982 si_emit_wait_fence(cs, false, flush_va, *flush_cnt, 0xffffffff);
983 }
984
985 /* VGT state sync */
986 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
987 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
988 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
989 }
990
991 /* Make sure ME is idle (it executes most packets) before continuing.
992 * This prevents read-after-write hazards between PFP and ME.
993 */
994 if ((cp_coher_cntl ||
995 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
996 RADV_CMD_FLAG_INV_VMEM_L1 |
997 RADV_CMD_FLAG_INV_GLOBAL_L2 |
998 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) &&
999 !is_mec) {
1000 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1001 radeon_emit(cs, 0);
1002 }
1003
1004 if ((flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) ||
1005 (chip_class <= CIK && (flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) {
1006 si_emit_acquire_mem(cs, is_mec, false, chip_class >= GFX9,
1007 cp_coher_cntl |
1008 S_0085F0_TC_ACTION_ENA(1) |
1009 S_0085F0_TCL1_ACTION_ENA(1) |
1010 S_0301F0_TC_WB_ACTION_ENA(chip_class >= VI));
1011 cp_coher_cntl = 0;
1012 } else {
1013 if(flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2) {
1014 /* WB = write-back
1015 * NC = apply to non-coherent MTYPEs
1016 * (i.e. MTYPE <= 1, which is what we use everywhere)
1017 *
1018 * WB doesn't work without NC.
1019 */
1020 si_emit_acquire_mem(cs, is_mec, false,
1021 chip_class >= GFX9,
1022 cp_coher_cntl |
1023 S_0301F0_TC_WB_ACTION_ENA(1) |
1024 S_0301F0_TC_NC_ACTION_ENA(1));
1025 cp_coher_cntl = 0;
1026 }
1027 if (flush_bits & RADV_CMD_FLAG_INV_VMEM_L1) {
1028 si_emit_acquire_mem(cs, is_mec,
1029 false, chip_class >= GFX9,
1030 cp_coher_cntl |
1031 S_0085F0_TCL1_ACTION_ENA(1));
1032 cp_coher_cntl = 0;
1033 }
1034 }
1035
1036 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1037 * Therefore, it should be last. Done in PFP.
1038 */
1039 if (cp_coher_cntl)
1040 si_emit_acquire_mem(cs, is_mec, false, chip_class >= GFX9, cp_coher_cntl);
1041 }
1042
1043 void
1044 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
1045 {
1046 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1047
1048 if (is_compute)
1049 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1050 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1051 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1052 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1053 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1054 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1055 RADV_CMD_FLAG_VGT_FLUSH);
1056
1057 if (!cmd_buffer->state.flush_bits)
1058 return;
1059
1060 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
1061 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1062
1063 uint32_t *ptr = NULL;
1064 uint64_t va = 0;
1065 if (chip_class == GFX9) {
1066 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) + cmd_buffer->gfx9_fence_offset;
1067 ptr = &cmd_buffer->gfx9_fence_idx;
1068 }
1069 si_cs_emit_cache_flush(cmd_buffer->cs,
1070 cmd_buffer->device->physical_device->rad_info.chip_class,
1071 ptr, va,
1072 radv_cmd_buffer_uses_mec(cmd_buffer),
1073 cmd_buffer->state.flush_bits);
1074
1075
1076 if (unlikely(cmd_buffer->device->trace_bo))
1077 radv_cmd_buffer_trace_emit(cmd_buffer);
1078
1079 cmd_buffer->state.flush_bits = 0;
1080 }
1081
1082 /* sets the CP predication state using a boolean stored at va */
1083 void
1084 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
1085 {
1086 uint32_t op = 0;
1087
1088 if (va)
1089 op = PRED_OP(PREDICATION_OP_BOOL64) | PREDICATION_DRAW_VISIBLE;
1090 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1091 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1092 radeon_emit(cmd_buffer->cs, op);
1093 radeon_emit(cmd_buffer->cs, va);
1094 radeon_emit(cmd_buffer->cs, va >> 32);
1095 } else {
1096 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1097 radeon_emit(cmd_buffer->cs, va);
1098 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1099 }
1100 }
1101
1102 /* Set this if you want the 3D engine to wait until CP DMA is done.
1103 * It should be set on the last CP DMA packet. */
1104 #define CP_DMA_SYNC (1 << 0)
1105
1106 /* Set this if the source data was used as a destination in a previous CP DMA
1107 * packet. It's for preventing a read-after-write (RAW) hazard between two
1108 * CP DMA packets. */
1109 #define CP_DMA_RAW_WAIT (1 << 1)
1110 #define CP_DMA_USE_L2 (1 << 2)
1111 #define CP_DMA_CLEAR (1 << 3)
1112
1113 /* Alignment for optimal performance. */
1114 #define SI_CPDMA_ALIGNMENT 32
1115
1116 /* The max number of bytes that can be copied per packet. */
1117 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1118 {
1119 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1120 S_414_BYTE_COUNT_GFX9(~0u) :
1121 S_414_BYTE_COUNT_GFX6(~0u);
1122
1123 /* make it aligned for optimal performance */
1124 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1125 }
1126
1127 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1128 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1129 * clear value.
1130 */
1131 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1132 uint64_t dst_va, uint64_t src_va,
1133 unsigned size, unsigned flags)
1134 {
1135 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1136 uint32_t header = 0, command = 0;
1137
1138 assert(size);
1139 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1140
1141 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1142 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1143 command |= S_414_BYTE_COUNT_GFX9(size);
1144 else
1145 command |= S_414_BYTE_COUNT_GFX6(size);
1146
1147 /* Sync flags. */
1148 if (flags & CP_DMA_SYNC)
1149 header |= S_411_CP_SYNC(1);
1150 else {
1151 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1152 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1153 else
1154 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1155 }
1156
1157 if (flags & CP_DMA_RAW_WAIT)
1158 command |= S_414_RAW_WAIT(1);
1159
1160 /* Src and dst flags. */
1161 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1162 !(flags & CP_DMA_CLEAR) &&
1163 src_va == dst_va)
1164 header |= S_411_DSL_SEL(V_411_NOWHERE); /* prefetch only */
1165 else if (flags & CP_DMA_USE_L2)
1166 header |= S_411_DSL_SEL(V_411_DST_ADDR_TC_L2);
1167
1168 if (flags & CP_DMA_CLEAR)
1169 header |= S_411_SRC_SEL(V_411_DATA);
1170 else if (flags & CP_DMA_USE_L2)
1171 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1172
1173 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1174 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1175 radeon_emit(cs, header);
1176 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1177 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1178 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1179 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1180 radeon_emit(cs, command);
1181 } else {
1182 assert(!(flags & CP_DMA_USE_L2));
1183 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1184 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1185 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1186 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1187 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1188 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1189 radeon_emit(cs, command);
1190 }
1191
1192 /* CP DMA is executed in ME, but index buffers are read by PFP.
1193 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1194 * indices. If we wanted to execute CP DMA in PFP, this packet
1195 * should precede it.
1196 */
1197 if ((flags & CP_DMA_SYNC) && cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1198 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1199 radeon_emit(cs, 0);
1200 }
1201
1202 if (unlikely(cmd_buffer->device->trace_bo))
1203 radv_cmd_buffer_trace_emit(cmd_buffer);
1204 }
1205
1206 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1207 unsigned size)
1208 {
1209 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1210 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1211
1212 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1213 aligned_size, CP_DMA_USE_L2);
1214 }
1215
1216 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1217 uint64_t remaining_size, unsigned *flags)
1218 {
1219
1220 /* Flush the caches for the first copy only.
1221 * Also wait for the previous CP DMA operations.
1222 */
1223 if (cmd_buffer->state.flush_bits) {
1224 si_emit_cache_flush(cmd_buffer);
1225 *flags |= CP_DMA_RAW_WAIT;
1226 }
1227
1228 /* Do the synchronization after the last dma, so that all data
1229 * is written to memory.
1230 */
1231 if (byte_count == remaining_size)
1232 *flags |= CP_DMA_SYNC;
1233 }
1234
1235 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1236 {
1237 uint64_t va;
1238 uint32_t offset;
1239 unsigned dma_flags = 0;
1240 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1241 void *ptr;
1242
1243 assert(size < SI_CPDMA_ALIGNMENT);
1244
1245 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1246
1247 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1248 va += offset;
1249
1250 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1251
1252 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1253 dma_flags);
1254 }
1255
1256 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1257 uint64_t src_va, uint64_t dest_va,
1258 uint64_t size)
1259 {
1260 uint64_t main_src_va, main_dest_va;
1261 uint64_t skipped_size = 0, realign_size = 0;
1262
1263
1264 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1265 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1266 /* If the size is not aligned, we must add a dummy copy at the end
1267 * just to align the internal counter. Otherwise, the DMA engine
1268 * would slow down by an order of magnitude for following copies.
1269 */
1270 if (size % SI_CPDMA_ALIGNMENT)
1271 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1272
1273 /* If the copy begins unaligned, we must start copying from the next
1274 * aligned block and the skipped part should be copied after everything
1275 * else has been copied. Only the src alignment matters, not dst.
1276 */
1277 if (src_va % SI_CPDMA_ALIGNMENT) {
1278 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1279 /* The main part will be skipped if the size is too small. */
1280 skipped_size = MIN2(skipped_size, size);
1281 size -= skipped_size;
1282 }
1283 }
1284 main_src_va = src_va + skipped_size;
1285 main_dest_va = dest_va + skipped_size;
1286
1287 while (size) {
1288 unsigned dma_flags = 0;
1289 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1290
1291 si_cp_dma_prepare(cmd_buffer, byte_count,
1292 size + skipped_size + realign_size,
1293 &dma_flags);
1294
1295 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1296 byte_count, dma_flags);
1297
1298 size -= byte_count;
1299 main_src_va += byte_count;
1300 main_dest_va += byte_count;
1301 }
1302
1303 if (skipped_size) {
1304 unsigned dma_flags = 0;
1305
1306 si_cp_dma_prepare(cmd_buffer, skipped_size,
1307 size + skipped_size + realign_size,
1308 &dma_flags);
1309
1310 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1311 skipped_size, dma_flags);
1312 }
1313 if (realign_size)
1314 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1315 }
1316
1317 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1318 uint64_t size, unsigned value)
1319 {
1320
1321 if (!size)
1322 return;
1323
1324 assert(va % 4 == 0 && size % 4 == 0);
1325
1326 while (size) {
1327 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1328 unsigned dma_flags = CP_DMA_CLEAR;
1329
1330 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1331
1332 /* Emit the clear packet. */
1333 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1334 dma_flags);
1335
1336 size -= byte_count;
1337 va += byte_count;
1338 }
1339 }
1340
1341 /* For MSAA sample positions. */
1342 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1343 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
1344 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1345 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1346 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1347
1348
1349 /* 2xMSAA
1350 * There are two locations (4, 4), (-4, -4). */
1351 const uint32_t eg_sample_locs_2x[4] = {
1352 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1353 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1354 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1355 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1356 };
1357 const unsigned eg_max_dist_2x = 4;
1358 /* 4xMSAA
1359 * There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
1360 const uint32_t eg_sample_locs_4x[4] = {
1361 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1362 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1363 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1364 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1365 };
1366 const unsigned eg_max_dist_4x = 6;
1367
1368 /* Cayman 8xMSAA */
1369 static const uint32_t cm_sample_locs_8x[] = {
1370 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1371 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1372 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1373 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1374 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1375 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1376 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1377 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1378 };
1379 static const unsigned cm_max_dist_8x = 8;
1380 /* Cayman 16xMSAA */
1381 static const uint32_t cm_sample_locs_16x[] = {
1382 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1383 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1384 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1385 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1386 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1387 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1388 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1389 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1390 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1391 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1392 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1393 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1394 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1395 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1396 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1397 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1398 };
1399 static const unsigned cm_max_dist_16x = 8;
1400
1401 unsigned radv_cayman_get_maxdist(int log_samples)
1402 {
1403 unsigned max_dist[] = {
1404 0,
1405 eg_max_dist_2x,
1406 eg_max_dist_4x,
1407 cm_max_dist_8x,
1408 cm_max_dist_16x
1409 };
1410 return max_dist[log_samples];
1411 }
1412
1413 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples)
1414 {
1415 switch (nr_samples) {
1416 default:
1417 case 1:
1418 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
1419 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
1420 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
1421 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
1422 break;
1423 case 2:
1424 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
1425 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
1426 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
1427 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
1428 break;
1429 case 4:
1430 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
1431 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
1432 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
1433 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
1434 break;
1435 case 8:
1436 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1437 radeon_emit(cs, cm_sample_locs_8x[0]);
1438 radeon_emit(cs, cm_sample_locs_8x[4]);
1439 radeon_emit(cs, 0);
1440 radeon_emit(cs, 0);
1441 radeon_emit(cs, cm_sample_locs_8x[1]);
1442 radeon_emit(cs, cm_sample_locs_8x[5]);
1443 radeon_emit(cs, 0);
1444 radeon_emit(cs, 0);
1445 radeon_emit(cs, cm_sample_locs_8x[2]);
1446 radeon_emit(cs, cm_sample_locs_8x[6]);
1447 radeon_emit(cs, 0);
1448 radeon_emit(cs, 0);
1449 radeon_emit(cs, cm_sample_locs_8x[3]);
1450 radeon_emit(cs, cm_sample_locs_8x[7]);
1451 break;
1452 case 16:
1453 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
1454 radeon_emit(cs, cm_sample_locs_16x[0]);
1455 radeon_emit(cs, cm_sample_locs_16x[4]);
1456 radeon_emit(cs, cm_sample_locs_16x[8]);
1457 radeon_emit(cs, cm_sample_locs_16x[12]);
1458 radeon_emit(cs, cm_sample_locs_16x[1]);
1459 radeon_emit(cs, cm_sample_locs_16x[5]);
1460 radeon_emit(cs, cm_sample_locs_16x[9]);
1461 radeon_emit(cs, cm_sample_locs_16x[13]);
1462 radeon_emit(cs, cm_sample_locs_16x[2]);
1463 radeon_emit(cs, cm_sample_locs_16x[6]);
1464 radeon_emit(cs, cm_sample_locs_16x[10]);
1465 radeon_emit(cs, cm_sample_locs_16x[14]);
1466 radeon_emit(cs, cm_sample_locs_16x[3]);
1467 radeon_emit(cs, cm_sample_locs_16x[7]);
1468 radeon_emit(cs, cm_sample_locs_16x[11]);
1469 radeon_emit(cs, cm_sample_locs_16x[15]);
1470 break;
1471 }
1472 }
1473
1474 static void radv_cayman_get_sample_position(struct radv_device *device,
1475 unsigned sample_count,
1476 unsigned sample_index, float *out_value)
1477 {
1478 int offset, index;
1479 struct {
1480 int idx:4;
1481 } val;
1482 switch (sample_count) {
1483 case 1:
1484 default:
1485 out_value[0] = out_value[1] = 0.5;
1486 break;
1487 case 2:
1488 offset = 4 * (sample_index * 2);
1489 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1490 out_value[0] = (float)(val.idx + 8) / 16.0f;
1491 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1492 out_value[1] = (float)(val.idx + 8) / 16.0f;
1493 break;
1494 case 4:
1495 offset = 4 * (sample_index * 2);
1496 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1497 out_value[0] = (float)(val.idx + 8) / 16.0f;
1498 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1499 out_value[1] = (float)(val.idx + 8) / 16.0f;
1500 break;
1501 case 8:
1502 offset = 4 * (sample_index % 4 * 2);
1503 index = (sample_index / 4) * 4;
1504 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1505 out_value[0] = (float)(val.idx + 8) / 16.0f;
1506 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1507 out_value[1] = (float)(val.idx + 8) / 16.0f;
1508 break;
1509 case 16:
1510 offset = 4 * (sample_index % 4 * 2);
1511 index = (sample_index / 4) * 4;
1512 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1513 out_value[0] = (float)(val.idx + 8) / 16.0f;
1514 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1515 out_value[1] = (float)(val.idx + 8) / 16.0f;
1516 break;
1517 }
1518 }
1519
1520 void radv_device_init_msaa(struct radv_device *device)
1521 {
1522 int i;
1523 radv_cayman_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1524
1525 for (i = 0; i < 2; i++)
1526 radv_cayman_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1527 for (i = 0; i < 4; i++)
1528 radv_cayman_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1529 for (i = 0; i < 8; i++)
1530 radv_cayman_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1531 for (i = 0; i < 16; i++)
1532 radv_cayman_get_sample_position(device, 16, i, device->sample_locations_16x[i]);
1533 }