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radv/gfx10: initialize GE_{MAX,MIN}_VTX_INDX/INDX_OFFSET
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for AMD GCN */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "radv_util.h"
35 #include "main/macros.h"
36
37 static void
38 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
39 struct radeon_cmdbuf *cs,
40 unsigned raster_config,
41 unsigned raster_config_1)
42 {
43 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
44 unsigned raster_config_se[4];
45 unsigned se;
46
47 ac_get_harvested_configs(&physical_device->rad_info,
48 raster_config,
49 &raster_config_1,
50 raster_config_se);
51
52 for (se = 0; se < num_se; se++) {
53 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
54 if (physical_device->rad_info.chip_class < GFX7)
55 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
56 S_00802C_SE_INDEX(se) |
57 S_00802C_SH_BROADCAST_WRITES(1) |
58 S_00802C_INSTANCE_BROADCAST_WRITES(1));
59 else
60 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
61 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
62 S_030800_INSTANCE_BROADCAST_WRITES(1));
63 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
64 }
65
66 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
67 if (physical_device->rad_info.chip_class < GFX7)
68 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
69 S_00802C_SE_BROADCAST_WRITES(1) |
70 S_00802C_SH_BROADCAST_WRITES(1) |
71 S_00802C_INSTANCE_BROADCAST_WRITES(1));
72 else
73 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
74 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
75 S_030800_INSTANCE_BROADCAST_WRITES(1));
76
77 if (physical_device->rad_info.chip_class >= GFX7)
78 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
79 }
80
81 void
82 si_emit_compute(struct radv_physical_device *physical_device,
83 struct radeon_cmdbuf *cs)
84 {
85 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
86 radeon_emit(cs, 0);
87 radeon_emit(cs, 0);
88 radeon_emit(cs, 0);
89
90 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
91 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
92 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
93 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
94
95 if (physical_device->rad_info.chip_class >= GFX7) {
96 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
97 radeon_set_sh_reg_seq(cs,
98 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
99 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
100 S_00B858_SH1_CU_EN(0xffff));
101 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
102 S_00B858_SH1_CU_EN(0xffff));
103 }
104
105 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
106 * and is now per pipe, so it should be handled in the
107 * kernel if we want to use something other than the default value,
108 * which is now 0x22f.
109 */
110 if (physical_device->rad_info.chip_class <= GFX6) {
111 /* XXX: This should be:
112 * (number of compute units) * 4 * (waves per simd) - 1 */
113
114 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
115 0x190 /* Default value */);
116 }
117 }
118
119 /* 12.4 fixed-point */
120 static unsigned radv_pack_float_12p4(float x)
121 {
122 return x <= 0 ? 0 :
123 x >= 4096 ? 0xffff : x * 16;
124 }
125
126 static void
127 si_set_raster_config(struct radv_physical_device *physical_device,
128 struct radeon_cmdbuf *cs)
129 {
130 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
131 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
132 unsigned raster_config, raster_config_1;
133
134 ac_get_raster_config(&physical_device->rad_info,
135 &raster_config,
136 &raster_config_1, NULL);
137
138 /* Always use the default config when all backends are enabled
139 * (or when we failed to determine the enabled backends).
140 */
141 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
142 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
143 raster_config);
144 if (physical_device->rad_info.chip_class >= GFX7)
145 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
146 raster_config_1);
147 } else {
148 si_write_harvested_raster_configs(physical_device, cs,
149 raster_config,
150 raster_config_1);
151 }
152 }
153
154 void
155 si_emit_graphics(struct radv_physical_device *physical_device,
156 struct radeon_cmdbuf *cs)
157 {
158 int i;
159
160 /* Only GFX6 can disable CLEAR_STATE for now. */
161 assert(physical_device->has_clear_state ||
162 physical_device->rad_info.chip_class == GFX6);
163
164 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
165 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
166 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
167
168 if (physical_device->has_clear_state) {
169 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
170 radeon_emit(cs, 0);
171 }
172
173 if (physical_device->rad_info.chip_class <= GFX8)
174 si_set_raster_config(physical_device, cs);
175
176 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
177 if (!physical_device->has_clear_state)
178 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
179
180 /* FIXME calculate these values somehow ??? */
181 if (physical_device->rad_info.chip_class <= GFX8) {
182 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
183 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
184 }
185
186 if (!physical_device->has_clear_state) {
187 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
188 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
189 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
190 }
191
192 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
193 if (!physical_device->has_clear_state)
194 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
195 if (physical_device->rad_info.chip_class < GFX7)
196 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
197 S_008A14_CLIP_VTX_REORDER_ENA(1));
198
199 if (!physical_device->has_clear_state)
200 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
201
202 /* CLEAR_STATE doesn't clear these correctly on certain generations.
203 * I don't know why. Deduced by trial and error.
204 */
205 if (physical_device->rad_info.chip_class <= GFX7) {
206 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
207 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
208 S_028204_WINDOW_OFFSET_DISABLE(1));
209 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
210 S_028240_WINDOW_OFFSET_DISABLE(1));
211 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
212 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
213 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
214 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
215 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
216 }
217
218 if (!physical_device->has_clear_state) {
219 for (i = 0; i < 16; i++) {
220 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
221 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
222 }
223 }
224
225 if (!physical_device->has_clear_state) {
226 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
227 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
228 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on GFX6 */
229 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
230 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
231 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
232 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
233 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
234 }
235
236 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
237 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
238 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
239
240 if (physical_device->rad_info.chip_class >= GFX10) {
241 radeon_set_uconfig_reg(cs, R_030964_GE_MAX_VTX_INDX, ~0);
242 radeon_set_uconfig_reg(cs, R_030924_GE_MIN_VTX_INDX, 0);
243 radeon_set_uconfig_reg(cs, R_030928_GE_INDX_OFFSET, 0);
244 } else if (physical_device->rad_info.chip_class >= GFX9) {
245 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
246 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
247 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
248 } else {
249 /* These registers, when written, also overwrite the
250 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
251 * them. It would be an issue if there was another UMD
252 * changing them.
253 */
254 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
255 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
256 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
257 }
258
259 if (physical_device->rad_info.chip_class >= GFX7) {
260 if (physical_device->rad_info.chip_class >= GFX9) {
261 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
262 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
263 } else {
264 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
265 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
266 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
267 S_00B41C_WAVE_LIMIT(0x3F));
268 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
269 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
270 /* If this is 0, Bonaire can hang even if GS isn't being used.
271 * Other chips are unaffected. These are suboptimal values,
272 * but we don't use on-chip GS.
273 */
274 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
275 S_028A44_ES_VERTS_PER_SUBGRP(64) |
276 S_028A44_GS_PRIMS_PER_SUBGRP(4));
277 }
278 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
279 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
280
281 if (physical_device->rad_info.num_good_cu_per_sh <= 4) {
282 /* Too few available compute units per SH. Disallowing
283 * VS to run on CU0 could hurt us more than late VS
284 * allocation would help.
285 *
286 * LATE_ALLOC_VS = 2 is the highest safe number.
287 */
288 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
289 S_00B118_CU_EN(0xffff) | S_00B118_WAVE_LIMIT(0x3F) );
290 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
291 } else {
292 /* Set LATE_ALLOC_VS == 31. It should be less than
293 * the number of scratch waves. Limitations:
294 * - VS can't execute on CU0.
295 * - If HS writes outputs to LDS, LS can't execute on CU0.
296 */
297 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
298 S_00B118_CU_EN(0xfffe) | S_00B118_WAVE_LIMIT(0x3F));
299 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
300 }
301
302 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
303 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
304 }
305
306 if (physical_device->rad_info.chip_class >= GFX10) {
307 radeon_set_context_reg(cs, R_02835C_PA_SC_TILE_STEERING_OVERRIDE,
308 physical_device->rad_info.pa_sc_tile_steering_override);
309 radeon_set_context_reg(cs, R_02807C_DB_RMI_L2_CACHE_CONTROL,
310 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
311 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
312 S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
313 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
314 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
315 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
316 S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD));
317
318 radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
319 S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
320 S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
321 S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR) |
322 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
323 S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
324 S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
325 S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD) |
326 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
327 }
328
329 if (physical_device->rad_info.chip_class >= GFX8) {
330 uint32_t vgt_tess_distribution;
331
332 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
333 S_028B50_ACCUM_TRI(11) |
334 S_028B50_ACCUM_QUAD(11) |
335 S_028B50_DONUT_SPLIT(16);
336
337 if (physical_device->rad_info.family == CHIP_FIJI ||
338 physical_device->rad_info.family >= CHIP_POLARIS10)
339 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
340
341 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
342 vgt_tess_distribution);
343 } else if (!physical_device->has_clear_state) {
344 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
345 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
346 }
347
348 if (physical_device->rad_info.chip_class >= GFX9) {
349 unsigned num_se = physical_device->rad_info.max_se;
350 unsigned pc_lines = 0;
351 unsigned max_alloc_count = 0;
352
353 switch (physical_device->rad_info.family) {
354 case CHIP_VEGA10:
355 case CHIP_VEGA12:
356 case CHIP_VEGA20:
357 pc_lines = 4096;
358 break;
359 case CHIP_RAVEN:
360 case CHIP_RAVEN2:
361 case CHIP_NAVI10:
362 case CHIP_NAVI12:
363 pc_lines = 1024;
364 break;
365 case CHIP_NAVI14:
366 pc_lines = 512;
367 break;
368 default:
369 assert(0);
370 }
371
372 if (physical_device->rad_info.chip_class >= GFX10) {
373 max_alloc_count = pc_lines / 3;
374 } else {
375 max_alloc_count = MIN2(128, pc_lines / (4 * num_se));
376 }
377
378 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
379 S_028C48_MAX_ALLOC_COUNT(max_alloc_count) |
380 S_028C48_MAX_PRIM_PER_BATCH(1023));
381 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
382 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
383 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
384 }
385
386 unsigned tmp = (unsigned)(1.0 * 8.0);
387 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
388 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
389 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
390 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
391 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
392
393 if (!physical_device->has_clear_state) {
394 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
395 S_028004_ZPASS_INCREMENT_DISABLE(1));
396 }
397
398 /* Enable the Polaris small primitive filter control.
399 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
400 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
401 * and AMDVLK doesn't have a workaround as well.
402 */
403 if (physical_device->rad_info.family >= CHIP_POLARIS10) {
404 unsigned small_prim_filter_cntl =
405 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
406 /* Workaround for a hw line bug. */
407 S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12);
408
409 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
410 small_prim_filter_cntl);
411 }
412
413 si_emit_compute(physical_device, cs);
414 }
415
416 void
417 cik_create_gfx_config(struct radv_device *device)
418 {
419 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX);
420 if (!cs)
421 return;
422
423 si_emit_graphics(device->physical_device, cs);
424
425 while (cs->cdw & 7) {
426 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
427 radeon_emit(cs, 0x80000000);
428 else
429 radeon_emit(cs, 0xffff1000);
430 }
431
432 device->gfx_init = device->ws->buffer_create(device->ws,
433 cs->cdw * 4, 4096,
434 RADEON_DOMAIN_GTT,
435 RADEON_FLAG_CPU_ACCESS|
436 RADEON_FLAG_NO_INTERPROCESS_SHARING |
437 RADEON_FLAG_READ_ONLY,
438 RADV_BO_PRIORITY_CS);
439 if (!device->gfx_init)
440 goto fail;
441
442 void *map = device->ws->buffer_map(device->gfx_init);
443 if (!map) {
444 device->ws->buffer_destroy(device->gfx_init);
445 device->gfx_init = NULL;
446 goto fail;
447 }
448 memcpy(map, cs->buf, cs->cdw * 4);
449
450 device->ws->buffer_unmap(device->gfx_init);
451 device->gfx_init_size_dw = cs->cdw;
452 fail:
453 device->ws->cs_destroy(cs);
454 }
455
456 static void
457 get_viewport_xform(const VkViewport *viewport,
458 float scale[3], float translate[3])
459 {
460 float x = viewport->x;
461 float y = viewport->y;
462 float half_width = 0.5f * viewport->width;
463 float half_height = 0.5f * viewport->height;
464 double n = viewport->minDepth;
465 double f = viewport->maxDepth;
466
467 scale[0] = half_width;
468 translate[0] = half_width + x;
469 scale[1] = half_height;
470 translate[1] = half_height + y;
471
472 scale[2] = (f - n);
473 translate[2] = n;
474 }
475
476 void
477 si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
478 int count, const VkViewport *viewports)
479 {
480 int i;
481
482 assert(count);
483 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
484 first_vp * 4 * 6, count * 6);
485
486 for (i = 0; i < count; i++) {
487 float scale[3], translate[3];
488
489
490 get_viewport_xform(&viewports[i], scale, translate);
491 radeon_emit(cs, fui(scale[0]));
492 radeon_emit(cs, fui(translate[0]));
493 radeon_emit(cs, fui(scale[1]));
494 radeon_emit(cs, fui(translate[1]));
495 radeon_emit(cs, fui(scale[2]));
496 radeon_emit(cs, fui(translate[2]));
497 }
498
499 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
500 first_vp * 4 * 2, count * 2);
501 for (i = 0; i < count; i++) {
502 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
503 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
504 radeon_emit(cs, fui(zmin));
505 radeon_emit(cs, fui(zmax));
506 }
507 }
508
509 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
510 {
511 float scale[3], translate[3];
512 VkRect2D rect;
513
514 get_viewport_xform(viewport, scale, translate);
515
516 rect.offset.x = translate[0] - fabs(scale[0]);
517 rect.offset.y = translate[1] - fabs(scale[1]);
518 rect.extent.width = ceilf(translate[0] + fabs(scale[0])) - rect.offset.x;
519 rect.extent.height = ceilf(translate[1] + fabs(scale[1])) - rect.offset.y;
520
521 return rect;
522 }
523
524 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
525 VkRect2D ret;
526 ret.offset.x = MAX2(a->offset.x, b->offset.x);
527 ret.offset.y = MAX2(a->offset.y, b->offset.y);
528 ret.extent.width = MIN2(a->offset.x + a->extent.width,
529 b->offset.x + b->extent.width) - ret.offset.x;
530 ret.extent.height = MIN2(a->offset.y + a->extent.height,
531 b->offset.y + b->extent.height) - ret.offset.y;
532 return ret;
533 }
534
535 void
536 si_write_scissors(struct radeon_cmdbuf *cs, int first,
537 int count, const VkRect2D *scissors,
538 const VkViewport *viewports, bool can_use_guardband)
539 {
540 int i;
541 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
542 const float max_range = 32767.0f;
543 if (!count)
544 return;
545
546 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
547 for (i = 0; i < count; i++) {
548 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
549 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
550
551 get_viewport_xform(viewports + i, scale, translate);
552 scale[0] = fabsf(scale[0]);
553 scale[1] = fabsf(scale[1]);
554
555 if (scale[0] < 0.5)
556 scale[0] = 0.5;
557 if (scale[1] < 0.5)
558 scale[1] = 0.5;
559
560 guardband_x = MIN2(guardband_x, (max_range - fabsf(translate[0])) / scale[0]);
561 guardband_y = MIN2(guardband_y, (max_range - fabsf(translate[1])) / scale[1]);
562
563 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
564 S_028250_TL_Y(scissor.offset.y) |
565 S_028250_WINDOW_OFFSET_DISABLE(1));
566 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
567 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
568 }
569 if (!can_use_guardband) {
570 guardband_x = 1.0;
571 guardband_y = 1.0;
572 }
573
574 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
575 radeon_emit(cs, fui(guardband_y));
576 radeon_emit(cs, fui(1.0));
577 radeon_emit(cs, fui(guardband_x));
578 radeon_emit(cs, fui(1.0));
579 }
580
581 static inline unsigned
582 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
583 {
584 if (num == 0)
585 return 0;
586
587 if (info->incr == 0)
588 return 0;
589
590 if (num < info->min)
591 return 0;
592
593 return 1 + ((num - info->min) / info->incr);
594 }
595
596 uint32_t
597 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
598 bool instanced_draw, bool indirect_draw,
599 bool count_from_stream_output,
600 uint32_t draw_vertex_count)
601 {
602 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
603 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
604 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
605 const unsigned max_primgroup_in_wave = 2;
606 /* SWITCH_ON_EOP(0) is always preferable. */
607 bool wd_switch_on_eop = false;
608 bool ia_switch_on_eop = false;
609 bool ia_switch_on_eoi = false;
610 bool partial_vs_wave = false;
611 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave;
612 bool multi_instances_smaller_than_primgroup;
613
614 multi_instances_smaller_than_primgroup = indirect_draw;
615 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
616 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
617 if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size)
618 multi_instances_smaller_than_primgroup = true;
619 }
620
621 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
622 partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
623
624 if (chip_class >= GFX7) {
625 wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.wd_switch_on_eop;
626
627 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
628 * We don't know that for indirect drawing, so treat it as
629 * always problematic. */
630 if (family == CHIP_HAWAII &&
631 (instanced_draw || indirect_draw))
632 wd_switch_on_eop = true;
633
634 /* Performance recommendation for 4 SE Gfx7-8 parts if
635 * instances are smaller than a primgroup.
636 * Assume indirect draws always use small instances.
637 * This is needed for good VS wave utilization.
638 */
639 if (chip_class <= GFX8 &&
640 info->max_se == 4 &&
641 multi_instances_smaller_than_primgroup)
642 wd_switch_on_eop = true;
643
644 /* Required on GFX7 and later. */
645 if (info->max_se > 2 && !wd_switch_on_eop)
646 ia_switch_on_eoi = true;
647
648 /* Required by Hawaii and, for some special cases, by GFX8. */
649 if (ia_switch_on_eoi &&
650 (family == CHIP_HAWAII ||
651 (chip_class == GFX8 &&
652 /* max primgroup in wave is always 2 - leave this for documentation */
653 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
654 partial_vs_wave = true;
655
656 /* Instancing bug on Bonaire. */
657 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
658 (instanced_draw || indirect_draw))
659 partial_vs_wave = true;
660
661 /* Hardware requirement when drawing primitives from a stream
662 * output buffer.
663 */
664 if (count_from_stream_output)
665 wd_switch_on_eop = true;
666
667 /* If the WD switch is false, the IA switch must be false too. */
668 assert(wd_switch_on_eop || !ia_switch_on_eop);
669 }
670 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
671 if (chip_class <= GFX8 && ia_switch_on_eoi)
672 partial_es_wave = true;
673
674 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
675 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
676 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
677 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
678 */
679 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
680 bool set_vgt_flush = indirect_draw;
681 if (!set_vgt_flush && instanced_draw) {
682 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
683 if (num_prims <= 1)
684 set_vgt_flush = true;
685 }
686 if (set_vgt_flush)
687 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
688 }
689 }
690
691 return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base |
692 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
693 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
694 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
695 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
696 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= GFX7 ? wd_switch_on_eop : 0);
697
698 }
699
700 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
701 enum chip_class chip_class,
702 bool is_mec,
703 unsigned event, unsigned event_flags,
704 unsigned data_sel,
705 uint64_t va,
706 uint32_t new_fence,
707 uint64_t gfx9_eop_bug_va)
708 {
709 unsigned op = EVENT_TYPE(event) |
710 EVENT_INDEX(5) |
711 event_flags;
712 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
713 unsigned sel = EOP_DATA_SEL(data_sel);
714
715 /* Wait for write confirmation before writing data, but don't send
716 * an interrupt. */
717 if (data_sel != EOP_DATA_SEL_DISCARD)
718 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
719
720 if (chip_class >= GFX9 || is_gfx8_mec) {
721 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
722 * counters) must immediately precede every timestamp event to
723 * prevent a GPU hang on GFX9.
724 */
725 if (chip_class == GFX9 && !is_mec) {
726 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
727 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
728 radeon_emit(cs, gfx9_eop_bug_va);
729 radeon_emit(cs, gfx9_eop_bug_va >> 32);
730 }
731
732 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false));
733 radeon_emit(cs, op);
734 radeon_emit(cs, sel);
735 radeon_emit(cs, va); /* address lo */
736 radeon_emit(cs, va >> 32); /* address hi */
737 radeon_emit(cs, new_fence); /* immediate data lo */
738 radeon_emit(cs, 0); /* immediate data hi */
739 if (!is_gfx8_mec)
740 radeon_emit(cs, 0); /* unused */
741 } else {
742 if (chip_class == GFX7 ||
743 chip_class == GFX8) {
744 /* Two EOP events are required to make all engines go idle
745 * (and optional cache flushes executed) before the timestamp
746 * is written.
747 */
748 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
749 radeon_emit(cs, op);
750 radeon_emit(cs, va);
751 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
752 radeon_emit(cs, 0); /* immediate data */
753 radeon_emit(cs, 0); /* unused */
754 }
755
756 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
757 radeon_emit(cs, op);
758 radeon_emit(cs, va);
759 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
760 radeon_emit(cs, new_fence); /* immediate data */
761 radeon_emit(cs, 0); /* unused */
762 }
763 }
764
765 void
766 radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
767 uint32_t ref, uint32_t mask)
768 {
769 assert(op == WAIT_REG_MEM_EQUAL ||
770 op == WAIT_REG_MEM_NOT_EQUAL ||
771 op == WAIT_REG_MEM_GREATER_OR_EQUAL);
772
773 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false));
774 radeon_emit(cs, op | WAIT_REG_MEM_MEM_SPACE(1));
775 radeon_emit(cs, va);
776 radeon_emit(cs, va >> 32);
777 radeon_emit(cs, ref); /* reference value */
778 radeon_emit(cs, mask); /* mask */
779 radeon_emit(cs, 4); /* poll interval */
780 }
781
782 static void
783 si_emit_acquire_mem(struct radeon_cmdbuf *cs,
784 bool is_mec,
785 bool is_gfx9,
786 unsigned cp_coher_cntl)
787 {
788 if (is_mec || is_gfx9) {
789 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
790 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) |
791 PKT3_SHADER_TYPE_S(is_mec));
792 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
793 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
794 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
795 radeon_emit(cs, 0); /* CP_COHER_BASE */
796 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
797 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
798 } else {
799 /* ACQUIRE_MEM is only required on a compute ring. */
800 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false));
801 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
802 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
803 radeon_emit(cs, 0); /* CP_COHER_BASE */
804 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
805 }
806 }
807
808 void
809 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
810 enum chip_class chip_class,
811 uint32_t *flush_cnt,
812 uint64_t flush_va,
813 bool is_mec,
814 enum radv_cmd_flush_bits flush_bits,
815 uint64_t gfx9_eop_bug_va)
816 {
817 unsigned cp_coher_cntl = 0;
818 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
819 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
820
821 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
822 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
823 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE)
824 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
825
826 if (chip_class <= GFX8) {
827 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
828 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
829 S_0085F0_CB0_DEST_BASE_ENA(1) |
830 S_0085F0_CB1_DEST_BASE_ENA(1) |
831 S_0085F0_CB2_DEST_BASE_ENA(1) |
832 S_0085F0_CB3_DEST_BASE_ENA(1) |
833 S_0085F0_CB4_DEST_BASE_ENA(1) |
834 S_0085F0_CB5_DEST_BASE_ENA(1) |
835 S_0085F0_CB6_DEST_BASE_ENA(1) |
836 S_0085F0_CB7_DEST_BASE_ENA(1);
837
838 /* Necessary for DCC */
839 if (chip_class >= GFX8) {
840 si_cs_emit_write_event_eop(cs,
841 chip_class,
842 is_mec,
843 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
844 0,
845 EOP_DATA_SEL_DISCARD,
846 0, 0,
847 gfx9_eop_bug_va);
848 }
849 }
850 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
851 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
852 S_0085F0_DB_DEST_BASE_ENA(1);
853 }
854 }
855
856 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
857 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
858 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
859 }
860
861 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
862 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
863 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
864 }
865
866 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
867 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
868 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
869 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
870 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
871 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
872 }
873
874 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
875 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
876 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
877 }
878
879 if (chip_class >= GFX9 && flush_cb_db) {
880 unsigned cb_db_event, tc_flags;
881
882 /* Set the CB/DB flush event. */
883 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
884
885 /* These are the only allowed combinations. If you need to
886 * do multiple operations at once, do them separately.
887 * All operations that invalidate L2 also seem to invalidate
888 * metadata. Volatile (VOL) and WC flushes are not listed here.
889 *
890 * TC | TC_WB = writeback & invalidate L2 & L1
891 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
892 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
893 * TC | TC_NC = invalidate L2 for MTYPE == NC
894 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
895 * TCL1 = invalidate L1
896 */
897 tc_flags = EVENT_TC_ACTION_ENA |
898 EVENT_TC_MD_ACTION_ENA;
899
900 /* Ideally flush TC together with CB/DB. */
901 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
902 /* Writeback and invalidate everything in L2 & L1. */
903 tc_flags = EVENT_TC_ACTION_ENA |
904 EVENT_TC_WB_ACTION_ENA;
905
906
907 /* Clear the flags. */
908 flush_bits &= ~(RADV_CMD_FLAG_INV_L2 |
909 RADV_CMD_FLAG_WB_L2 |
910 RADV_CMD_FLAG_INV_VCACHE);
911 }
912 assert(flush_cnt);
913 (*flush_cnt)++;
914
915 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags,
916 EOP_DATA_SEL_VALUE_32BIT,
917 flush_va, *flush_cnt,
918 gfx9_eop_bug_va);
919 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
920 *flush_cnt, 0xffffffff);
921 }
922
923 /* VGT state sync */
924 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
925 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
926 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
927 }
928
929 /* VGT streamout state sync */
930 if (flush_bits & RADV_CMD_FLAG_VGT_STREAMOUT_SYNC) {
931 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
932 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
933 }
934
935 /* Make sure ME is idle (it executes most packets) before continuing.
936 * This prevents read-after-write hazards between PFP and ME.
937 */
938 if ((cp_coher_cntl ||
939 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
940 RADV_CMD_FLAG_INV_VCACHE |
941 RADV_CMD_FLAG_INV_L2 |
942 RADV_CMD_FLAG_WB_L2))) &&
943 !is_mec) {
944 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
945 radeon_emit(cs, 0);
946 }
947
948 if ((flush_bits & RADV_CMD_FLAG_INV_L2) ||
949 (chip_class <= GFX7 && (flush_bits & RADV_CMD_FLAG_WB_L2))) {
950 si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9,
951 cp_coher_cntl |
952 S_0085F0_TC_ACTION_ENA(1) |
953 S_0085F0_TCL1_ACTION_ENA(1) |
954 S_0301F0_TC_WB_ACTION_ENA(chip_class >= GFX8));
955 cp_coher_cntl = 0;
956 } else {
957 if(flush_bits & RADV_CMD_FLAG_WB_L2) {
958 /* WB = write-back
959 * NC = apply to non-coherent MTYPEs
960 * (i.e. MTYPE <= 1, which is what we use everywhere)
961 *
962 * WB doesn't work without NC.
963 */
964 si_emit_acquire_mem(cs, is_mec,
965 chip_class >= GFX9,
966 cp_coher_cntl |
967 S_0301F0_TC_WB_ACTION_ENA(1) |
968 S_0301F0_TC_NC_ACTION_ENA(1));
969 cp_coher_cntl = 0;
970 }
971 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE) {
972 si_emit_acquire_mem(cs, is_mec,
973 chip_class >= GFX9,
974 cp_coher_cntl |
975 S_0085F0_TCL1_ACTION_ENA(1));
976 cp_coher_cntl = 0;
977 }
978 }
979
980 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
981 * Therefore, it should be last. Done in PFP.
982 */
983 if (cp_coher_cntl)
984 si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9, cp_coher_cntl);
985
986 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
987 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
988 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
989 EVENT_INDEX(0));
990 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
991 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
992 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
993 EVENT_INDEX(0));
994 }
995 }
996
997 void
998 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
999 {
1000 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1001
1002 if (is_compute)
1003 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1004 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1005 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1006 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1007 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1008 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1009 RADV_CMD_FLAG_VGT_FLUSH |
1010 RADV_CMD_FLAG_START_PIPELINE_STATS |
1011 RADV_CMD_FLAG_STOP_PIPELINE_STATS);
1012
1013 if (!cmd_buffer->state.flush_bits)
1014 return;
1015
1016 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1017
1018 si_cs_emit_cache_flush(cmd_buffer->cs,
1019 cmd_buffer->device->physical_device->rad_info.chip_class,
1020 &cmd_buffer->gfx9_fence_idx,
1021 cmd_buffer->gfx9_fence_va,
1022 radv_cmd_buffer_uses_mec(cmd_buffer),
1023 cmd_buffer->state.flush_bits,
1024 cmd_buffer->gfx9_eop_bug_va);
1025
1026
1027 if (unlikely(cmd_buffer->device->trace_bo))
1028 radv_cmd_buffer_trace_emit(cmd_buffer);
1029
1030 /* Clear the caches that have been flushed to avoid syncing too much
1031 * when there is some pending active queries.
1032 */
1033 cmd_buffer->active_query_flush_bits &= ~cmd_buffer->state.flush_bits;
1034
1035 cmd_buffer->state.flush_bits = 0;
1036
1037 /* If the driver used a compute shader for resetting a query pool, it
1038 * should be finished at this point.
1039 */
1040 cmd_buffer->pending_reset_query = false;
1041 }
1042
1043 /* sets the CP predication state using a boolean stored at va */
1044 void
1045 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1046 bool draw_visible, uint64_t va)
1047 {
1048 uint32_t op = 0;
1049
1050 if (va) {
1051 op = PRED_OP(PREDICATION_OP_BOOL64);
1052
1053 /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
1054 * zero, all rendering commands are discarded. Otherwise, they
1055 * are discarded if the value is non zero.
1056 */
1057 op |= draw_visible ? PREDICATION_DRAW_VISIBLE :
1058 PREDICATION_DRAW_NOT_VISIBLE;
1059 }
1060 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1061 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1062 radeon_emit(cmd_buffer->cs, op);
1063 radeon_emit(cmd_buffer->cs, va);
1064 radeon_emit(cmd_buffer->cs, va >> 32);
1065 } else {
1066 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1067 radeon_emit(cmd_buffer->cs, va);
1068 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1069 }
1070 }
1071
1072 /* Set this if you want the 3D engine to wait until CP DMA is done.
1073 * It should be set on the last CP DMA packet. */
1074 #define CP_DMA_SYNC (1 << 0)
1075
1076 /* Set this if the source data was used as a destination in a previous CP DMA
1077 * packet. It's for preventing a read-after-write (RAW) hazard between two
1078 * CP DMA packets. */
1079 #define CP_DMA_RAW_WAIT (1 << 1)
1080 #define CP_DMA_USE_L2 (1 << 2)
1081 #define CP_DMA_CLEAR (1 << 3)
1082
1083 /* Alignment for optimal performance. */
1084 #define SI_CPDMA_ALIGNMENT 32
1085
1086 /* The max number of bytes that can be copied per packet. */
1087 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1088 {
1089 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1090 S_414_BYTE_COUNT_GFX9(~0u) :
1091 S_414_BYTE_COUNT_GFX6(~0u);
1092
1093 /* make it aligned for optimal performance */
1094 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1095 }
1096
1097 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1098 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1099 * clear value.
1100 */
1101 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1102 uint64_t dst_va, uint64_t src_va,
1103 unsigned size, unsigned flags)
1104 {
1105 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1106 uint32_t header = 0, command = 0;
1107
1108 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1109
1110 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1111 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1112 command |= S_414_BYTE_COUNT_GFX9(size);
1113 else
1114 command |= S_414_BYTE_COUNT_GFX6(size);
1115
1116 /* Sync flags. */
1117 if (flags & CP_DMA_SYNC)
1118 header |= S_411_CP_SYNC(1);
1119 else {
1120 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1121 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1122 else
1123 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1124 }
1125
1126 if (flags & CP_DMA_RAW_WAIT)
1127 command |= S_414_RAW_WAIT(1);
1128
1129 /* Src and dst flags. */
1130 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1131 !(flags & CP_DMA_CLEAR) &&
1132 src_va == dst_va)
1133 header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
1134 else if (flags & CP_DMA_USE_L2)
1135 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
1136
1137 if (flags & CP_DMA_CLEAR)
1138 header |= S_411_SRC_SEL(V_411_DATA);
1139 else if (flags & CP_DMA_USE_L2)
1140 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1141
1142 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1143 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1144 radeon_emit(cs, header);
1145 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1146 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1147 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1148 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1149 radeon_emit(cs, command);
1150 } else {
1151 assert(!(flags & CP_DMA_USE_L2));
1152 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1153 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1154 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1155 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1156 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1157 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1158 radeon_emit(cs, command);
1159 }
1160
1161 /* CP DMA is executed in ME, but index buffers are read by PFP.
1162 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1163 * indices. If we wanted to execute CP DMA in PFP, this packet
1164 * should precede it.
1165 */
1166 if (flags & CP_DMA_SYNC) {
1167 if (cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1168 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1169 radeon_emit(cs, 0);
1170 }
1171
1172 /* CP will see the sync flag and wait for all DMAs to complete. */
1173 cmd_buffer->state.dma_is_busy = false;
1174 }
1175
1176 if (unlikely(cmd_buffer->device->trace_bo))
1177 radv_cmd_buffer_trace_emit(cmd_buffer);
1178 }
1179
1180 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1181 unsigned size)
1182 {
1183 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1184 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1185
1186 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1187 aligned_size, CP_DMA_USE_L2);
1188 }
1189
1190 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1191 uint64_t remaining_size, unsigned *flags)
1192 {
1193
1194 /* Flush the caches for the first copy only.
1195 * Also wait for the previous CP DMA operations.
1196 */
1197 if (cmd_buffer->state.flush_bits) {
1198 si_emit_cache_flush(cmd_buffer);
1199 *flags |= CP_DMA_RAW_WAIT;
1200 }
1201
1202 /* Do the synchronization after the last dma, so that all data
1203 * is written to memory.
1204 */
1205 if (byte_count == remaining_size)
1206 *flags |= CP_DMA_SYNC;
1207 }
1208
1209 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1210 {
1211 uint64_t va;
1212 uint32_t offset;
1213 unsigned dma_flags = 0;
1214 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1215 void *ptr;
1216
1217 assert(size < SI_CPDMA_ALIGNMENT);
1218
1219 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1220
1221 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1222 va += offset;
1223
1224 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1225
1226 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1227 dma_flags);
1228 }
1229
1230 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1231 uint64_t src_va, uint64_t dest_va,
1232 uint64_t size)
1233 {
1234 uint64_t main_src_va, main_dest_va;
1235 uint64_t skipped_size = 0, realign_size = 0;
1236
1237 /* Assume that we are not going to sync after the last DMA operation. */
1238 cmd_buffer->state.dma_is_busy = true;
1239
1240 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1241 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1242 /* If the size is not aligned, we must add a dummy copy at the end
1243 * just to align the internal counter. Otherwise, the DMA engine
1244 * would slow down by an order of magnitude for following copies.
1245 */
1246 if (size % SI_CPDMA_ALIGNMENT)
1247 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1248
1249 /* If the copy begins unaligned, we must start copying from the next
1250 * aligned block and the skipped part should be copied after everything
1251 * else has been copied. Only the src alignment matters, not dst.
1252 */
1253 if (src_va % SI_CPDMA_ALIGNMENT) {
1254 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1255 /* The main part will be skipped if the size is too small. */
1256 skipped_size = MIN2(skipped_size, size);
1257 size -= skipped_size;
1258 }
1259 }
1260 main_src_va = src_va + skipped_size;
1261 main_dest_va = dest_va + skipped_size;
1262
1263 while (size) {
1264 unsigned dma_flags = 0;
1265 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1266
1267 si_cp_dma_prepare(cmd_buffer, byte_count,
1268 size + skipped_size + realign_size,
1269 &dma_flags);
1270
1271 dma_flags &= ~CP_DMA_SYNC;
1272
1273 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1274 byte_count, dma_flags);
1275
1276 size -= byte_count;
1277 main_src_va += byte_count;
1278 main_dest_va += byte_count;
1279 }
1280
1281 if (skipped_size) {
1282 unsigned dma_flags = 0;
1283
1284 si_cp_dma_prepare(cmd_buffer, skipped_size,
1285 size + skipped_size + realign_size,
1286 &dma_flags);
1287
1288 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1289 skipped_size, dma_flags);
1290 }
1291 if (realign_size)
1292 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1293 }
1294
1295 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1296 uint64_t size, unsigned value)
1297 {
1298
1299 if (!size)
1300 return;
1301
1302 assert(va % 4 == 0 && size % 4 == 0);
1303
1304 /* Assume that we are not going to sync after the last DMA operation. */
1305 cmd_buffer->state.dma_is_busy = true;
1306
1307 while (size) {
1308 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1309 unsigned dma_flags = CP_DMA_CLEAR;
1310
1311 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1312
1313 /* Emit the clear packet. */
1314 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1315 dma_flags);
1316
1317 size -= byte_count;
1318 va += byte_count;
1319 }
1320 }
1321
1322 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
1323 {
1324 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX7)
1325 return;
1326
1327 if (!cmd_buffer->state.dma_is_busy)
1328 return;
1329
1330 /* Issue a dummy DMA that copies zero bytes.
1331 *
1332 * The DMA engine will see that there's no work to do and skip this
1333 * DMA request, however, the CP will see the sync flag and still wait
1334 * for all DMAs to complete.
1335 */
1336 si_emit_cp_dma(cmd_buffer, 0, 0, 0, CP_DMA_SYNC);
1337
1338 cmd_buffer->state.dma_is_busy = false;
1339 }
1340
1341 /* For MSAA sample positions. */
1342 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1343 ((((unsigned)(s0x) & 0xf) << 0) | (((unsigned)(s0y) & 0xf) << 4) | \
1344 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1345 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1346 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1347
1348 /* For obtaining location coordinates from registers */
1349 #define SEXT4(x) ((int)((x) | ((x) & 0x8 ? 0xfffffff0 : 0)))
1350 #define GET_SFIELD(reg, index) SEXT4(((reg) >> ((index) * 4)) & 0xf)
1351 #define GET_SX(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2)
1352 #define GET_SY(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2 + 1)
1353
1354 /* 1x MSAA */
1355 static const uint32_t sample_locs_1x =
1356 FILL_SREG(0, 0, 0, 0, 0, 0, 0, 0);
1357 static const unsigned max_dist_1x = 0;
1358 static const uint64_t centroid_priority_1x = 0x0000000000000000ull;
1359
1360 /* 2xMSAA */
1361 static const uint32_t sample_locs_2x =
1362 FILL_SREG(4,4, -4, -4, 0, 0, 0, 0);
1363 static const unsigned max_dist_2x = 4;
1364 static const uint64_t centroid_priority_2x = 0x1010101010101010ull;
1365
1366 /* 4xMSAA */
1367 static const uint32_t sample_locs_4x =
1368 FILL_SREG(-2,-6, 6, -2, -6, 2, 2, 6);
1369 static const unsigned max_dist_4x = 6;
1370 static const uint64_t centroid_priority_4x = 0x3210321032103210ull;
1371
1372 /* 8xMSAA */
1373 static const uint32_t sample_locs_8x[] = {
1374 FILL_SREG( 1,-3, -1, 3, 5, 1, -3,-5),
1375 FILL_SREG(-5, 5, -7,-1, 3, 7, 7,-7),
1376 /* The following are unused by hardware, but we emit them to IBs
1377 * instead of multiple SET_CONTEXT_REG packets. */
1378 0,
1379 0,
1380 };
1381 static const unsigned max_dist_8x = 7;
1382 static const uint64_t centroid_priority_8x = 0x7654321076543210ull;
1383
1384 unsigned radv_get_default_max_sample_dist(int log_samples)
1385 {
1386 unsigned max_dist[] = {
1387 max_dist_1x,
1388 max_dist_2x,
1389 max_dist_4x,
1390 max_dist_8x,
1391 };
1392 return max_dist[log_samples];
1393 }
1394
1395 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples)
1396 {
1397 switch (nr_samples) {
1398 default:
1399 case 1:
1400 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1401 radeon_emit(cs, (uint32_t)centroid_priority_1x);
1402 radeon_emit(cs, centroid_priority_1x >> 32);
1403 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_1x);
1404 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_1x);
1405 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_1x);
1406 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_1x);
1407 break;
1408 case 2:
1409 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1410 radeon_emit(cs, (uint32_t)centroid_priority_2x);
1411 radeon_emit(cs, centroid_priority_2x >> 32);
1412 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x);
1413 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x);
1414 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x);
1415 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x);
1416 break;
1417 case 4:
1418 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1419 radeon_emit(cs, (uint32_t)centroid_priority_4x);
1420 radeon_emit(cs, centroid_priority_4x >> 32);
1421 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x);
1422 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x);
1423 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x);
1424 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x);
1425 break;
1426 case 8:
1427 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1428 radeon_emit(cs, (uint32_t)centroid_priority_8x);
1429 radeon_emit(cs, centroid_priority_8x >> 32);
1430 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1431 radeon_emit_array(cs, sample_locs_8x, 4);
1432 radeon_emit_array(cs, sample_locs_8x, 4);
1433 radeon_emit_array(cs, sample_locs_8x, 4);
1434 radeon_emit_array(cs, sample_locs_8x, 2);
1435 break;
1436 }
1437 }
1438
1439 static void radv_get_sample_position(struct radv_device *device,
1440 unsigned sample_count,
1441 unsigned sample_index, float *out_value)
1442 {
1443 const uint32_t *sample_locs;
1444
1445 switch (sample_count) {
1446 case 1:
1447 default:
1448 sample_locs = &sample_locs_1x;
1449 break;
1450 case 2:
1451 sample_locs = &sample_locs_2x;
1452 break;
1453 case 4:
1454 sample_locs = &sample_locs_4x;
1455 break;
1456 case 8:
1457 sample_locs = sample_locs_8x;
1458 break;
1459 }
1460
1461 out_value[0] = (GET_SX(sample_locs, sample_index) + 8) / 16.0f;
1462 out_value[1] = (GET_SY(sample_locs, sample_index) + 8) / 16.0f;
1463 }
1464
1465 void radv_device_init_msaa(struct radv_device *device)
1466 {
1467 int i;
1468
1469 radv_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1470
1471 for (i = 0; i < 2; i++)
1472 radv_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1473 for (i = 0; i < 4; i++)
1474 radv_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1475 for (i = 0; i < 8; i++)
1476 radv_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1477 }