projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: disable CPU caching for IBS to reduce fetch latency
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for AMD GCN */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "radv_util.h"
35
36 static void
37 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
38 struct radeon_cmdbuf *cs,
39 unsigned raster_config,
40 unsigned raster_config_1)
41 {
42 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
43 unsigned raster_config_se[4];
44 unsigned se;
45
46 ac_get_harvested_configs(&physical_device->rad_info,
47 raster_config,
48 &raster_config_1,
49 raster_config_se);
50
51 for (se = 0; se < num_se; se++) {
52 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
53 if (physical_device->rad_info.chip_class < GFX7)
54 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
55 S_00802C_SE_INDEX(se) |
56 S_00802C_SH_BROADCAST_WRITES(1) |
57 S_00802C_INSTANCE_BROADCAST_WRITES(1));
58 else
59 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
60 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
61 S_030800_INSTANCE_BROADCAST_WRITES(1));
62 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
63 }
64
65 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
66 if (physical_device->rad_info.chip_class < GFX7)
67 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
68 S_00802C_SE_BROADCAST_WRITES(1) |
69 S_00802C_SH_BROADCAST_WRITES(1) |
70 S_00802C_INSTANCE_BROADCAST_WRITES(1));
71 else
72 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
73 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
74 S_030800_INSTANCE_BROADCAST_WRITES(1));
75
76 if (physical_device->rad_info.chip_class >= GFX7)
77 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
78 }
79
80 void
81 si_emit_compute(struct radv_physical_device *physical_device,
82 struct radeon_cmdbuf *cs)
83 {
84 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
85 radeon_emit(cs, 0);
86 radeon_emit(cs, 0);
87 radeon_emit(cs, 0);
88
89 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
90 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
91 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
92 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
93 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
94
95 if (physical_device->rad_info.chip_class >= GFX7) {
96 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
97 radeon_set_sh_reg_seq(cs,
98 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
99 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
100 S_00B858_SH1_CU_EN(0xffff));
101 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
102 S_00B858_SH1_CU_EN(0xffff));
103 }
104
105 if (physical_device->rad_info.chip_class >= GFX10)
106 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
107
108 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
109 * and is now per pipe, so it should be handled in the
110 * kernel if we want to use something other than the default value,
111 * which is now 0x22f.
112 */
113 if (physical_device->rad_info.chip_class <= GFX6) {
114 /* XXX: This should be:
115 * (number of compute units) * 4 * (waves per simd) - 1 */
116
117 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
118 0x190 /* Default value */);
119 }
120 }
121
122 /* 12.4 fixed-point */
123 static unsigned radv_pack_float_12p4(float x)
124 {
125 return x <= 0 ? 0 :
126 x >= 4096 ? 0xffff : x * 16;
127 }
128
129 static void
130 si_set_raster_config(struct radv_physical_device *physical_device,
131 struct radeon_cmdbuf *cs)
132 {
133 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
134 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
135 unsigned raster_config, raster_config_1;
136
137 ac_get_raster_config(&physical_device->rad_info,
138 &raster_config,
139 &raster_config_1, NULL);
140
141 /* Always use the default config when all backends are enabled
142 * (or when we failed to determine the enabled backends).
143 */
144 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
145 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
146 raster_config);
147 if (physical_device->rad_info.chip_class >= GFX7)
148 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
149 raster_config_1);
150 } else {
151 si_write_harvested_raster_configs(physical_device, cs,
152 raster_config,
153 raster_config_1);
154 }
155 }
156
157 void
158 si_emit_graphics(struct radv_device *device,
159 struct radeon_cmdbuf *cs)
160 {
161 struct radv_physical_device *physical_device = device->physical_device;
162
163 bool has_clear_state = physical_device->rad_info.has_clear_state;
164 int i;
165
166 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
167 radeon_emit(cs, CC0_UPDATE_LOAD_ENABLES(1));
168 radeon_emit(cs, CC1_UPDATE_SHADOW_ENABLES(1));
169
170 if (has_clear_state) {
171 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
172 radeon_emit(cs, 0);
173 }
174
175 if (physical_device->rad_info.chip_class <= GFX8)
176 si_set_raster_config(physical_device, cs);
177
178 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
179 if (!has_clear_state)
180 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
181
182 /* FIXME calculate these values somehow ??? */
183 if (physical_device->rad_info.chip_class <= GFX8) {
184 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
185 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
186 }
187
188 if (!has_clear_state) {
189 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
190 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
191 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
192 }
193
194 if (physical_device->rad_info.chip_class <= GFX9)
195 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
196 if (!has_clear_state)
197 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
198 if (physical_device->rad_info.chip_class < GFX7)
199 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
200 S_008A14_CLIP_VTX_REORDER_ENA(1));
201
202 if (!has_clear_state)
203 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
204
205 /* CLEAR_STATE doesn't clear these correctly on certain generations.
206 * I don't know why. Deduced by trial and error.
207 */
208 if (physical_device->rad_info.chip_class <= GFX7 || !has_clear_state) {
209 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
210 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
211 S_028204_WINDOW_OFFSET_DISABLE(1));
212 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
213 S_028240_WINDOW_OFFSET_DISABLE(1));
214 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
215 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
216 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
217 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
218 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
219 }
220
221 if (!has_clear_state) {
222 for (i = 0; i < 16; i++) {
223 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
224 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
225 }
226 }
227
228 if (!has_clear_state) {
229 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
230 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
231 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on GFX6 */
232 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
233 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
234 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
235 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
236 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
237 }
238
239 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
240 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
241 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
242
243 if (physical_device->rad_info.chip_class >= GFX10) {
244 radeon_set_context_reg(cs, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0);
245 radeon_set_uconfig_reg(cs, R_030964_GE_MAX_VTX_INDX, ~0);
246 radeon_set_uconfig_reg(cs, R_030924_GE_MIN_VTX_INDX, 0);
247 radeon_set_uconfig_reg(cs, R_030928_GE_INDX_OFFSET, 0);
248 radeon_set_uconfig_reg(cs, R_03097C_GE_STEREO_CNTL, 0);
249 radeon_set_uconfig_reg(cs, R_030988_GE_USER_VGPR_EN, 0);
250 } else if (physical_device->rad_info.chip_class == GFX9) {
251 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
252 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
253 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
254 } else {
255 /* These registers, when written, also overwrite the
256 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
257 * them. It would be an issue if there was another UMD
258 * changing them.
259 */
260 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
261 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
262 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
263 }
264
265 if (physical_device->rad_info.chip_class >= GFX7) {
266 if (physical_device->rad_info.chip_class >= GFX10) {
267 /* Logical CUs 16 - 31 */
268 radeon_set_sh_reg_idx(physical_device, cs, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
269 3, S_00B404_CU_EN(0xffff));
270 radeon_set_sh_reg_idx(physical_device, cs, R_00B104_SPI_SHADER_PGM_RSRC4_VS,
271 3, S_00B104_CU_EN(0xffff));
272 radeon_set_sh_reg_idx(physical_device, cs, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
273 3, S_00B004_CU_EN(0xffff));
274 }
275
276 if (physical_device->rad_info.chip_class >= GFX9) {
277 radeon_set_sh_reg_idx(physical_device, cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
278 3, S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
279 } else {
280 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
281 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
282 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
283 S_00B41C_WAVE_LIMIT(0x3F));
284 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
285 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
286 /* If this is 0, Bonaire can hang even if GS isn't being used.
287 * Other chips are unaffected. These are suboptimal values,
288 * but we don't use on-chip GS.
289 */
290 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
291 S_028A44_ES_VERTS_PER_SUBGRP(64) |
292 S_028A44_GS_PRIMS_PER_SUBGRP(4));
293 }
294
295 /* Compute LATE_ALLOC_VS.LIMIT. */
296 unsigned num_cu_per_sh = physical_device->rad_info.min_good_cu_per_sa;
297 unsigned late_alloc_wave64 = 0; /* The limit is per SA. */
298 unsigned late_alloc_wave64_gs = 0;
299 unsigned cu_mask_vs = 0xffff;
300 unsigned cu_mask_gs = 0xffff;
301
302 if (physical_device->rad_info.chip_class >= GFX10) {
303 /* For Wave32, the hw will launch twice the number of late
304 * alloc waves, so 1 == 2x wave32.
305 */
306 if (!physical_device->rad_info.use_late_alloc) {
307 late_alloc_wave64 = 0;
308 } else if (num_cu_per_sh <= 6) {
309 late_alloc_wave64 = num_cu_per_sh - 2;
310 } else {
311 late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
312
313 /* CU2 & CU3 disabled because of the dual CU design */
314 cu_mask_vs = 0xfff3;
315 cu_mask_gs = 0xfff3; /* NGG only */
316 }
317
318 late_alloc_wave64_gs = late_alloc_wave64;
319
320 /* Don't use late alloc for NGG on Navi14 due to a hw
321 * bug. If NGG is never used, enable all CUs.
322 */
323 if (!physical_device->use_ngg ||
324 physical_device->rad_info.family == CHIP_NAVI14) {
325 late_alloc_wave64_gs = 0;
326 cu_mask_gs = 0xffff;
327 }
328 } else {
329 if (!physical_device->rad_info.use_late_alloc) {
330 late_alloc_wave64 = 0;
331 } else if (num_cu_per_sh <= 4) {
332 /* Too few available compute units per SA.
333 * Disallowing VS to run on one CU could hurt
334 * us more than late VS allocation would help.
335 *
336 * 2 is the highest safe number that allows us
337 * to keep all CUs enabled.
338 */
339 late_alloc_wave64 = 2;
340 } else {
341 /* This is a good initial value, allowing 1
342 * late_alloc wave per SIMD on num_cu - 2.
343 */
344 late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
345 }
346
347 if (late_alloc_wave64 > 2)
348 cu_mask_vs = 0xfffe; /* 1 CU disabled */
349 }
350
351 radeon_set_sh_reg_idx(physical_device, cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
352 3, S_00B118_CU_EN(cu_mask_vs) |
353 S_00B118_WAVE_LIMIT(0x3F));
354 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
355 S_00B11C_LIMIT(late_alloc_wave64));
356
357 radeon_set_sh_reg_idx(physical_device, cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
358 3, S_00B21C_CU_EN(cu_mask_gs) | S_00B21C_WAVE_LIMIT(0x3F));
359
360 if (physical_device->rad_info.chip_class >= GFX10) {
361 radeon_set_sh_reg_idx(physical_device, cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
362 3, S_00B204_CU_EN(0xffff) |
363 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64_gs));
364 }
365
366 radeon_set_sh_reg_idx(physical_device, cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
367 3, S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
368 }
369
370 if (physical_device->rad_info.chip_class >= GFX10) {
371 /* Break up a pixel wave if it contains deallocs for more than
372 * half the parameter cache.
373 *
374 * To avoid a deadlock where pixel waves aren't launched
375 * because they're waiting for more pixels while the frontend
376 * is stuck waiting for PC space, the maximum allowed value is
377 * the size of the PC minus the largest possible allocation for
378 * a single primitive shader subgroup.
379 */
380 radeon_set_context_reg(cs, R_028C50_PA_SC_NGG_MODE_CNTL,
381 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
382 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
383
384 /* Enable CMASK/FMASK/HTILE/DCC caching in L2 for small chips. */
385 unsigned meta_write_policy, meta_read_policy;
386
387 /* TODO: investigate whether LRU improves performance on other chips too */
388 if (physical_device->rad_info.num_render_backends <= 4) {
389 meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */
390 meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */
391 } else {
392 meta_write_policy = V_02807C_CACHE_STREAM_WR; /* write combine */
393 meta_read_policy = V_02807C_CACHE_NOA_RD; /* don't cache reads */
394 }
395
396 radeon_set_context_reg(cs, R_02807C_DB_RMI_L2_CACHE_CONTROL,
397 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
398 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
399 S_02807C_HTILE_WR_POLICY(meta_write_policy) |
400 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
401 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
402 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
403 S_02807C_HTILE_RD_POLICY(meta_read_policy));
404
405 radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
406 S_028410_CMASK_WR_POLICY(meta_write_policy) |
407 S_028410_FMASK_WR_POLICY(meta_write_policy) |
408 S_028410_DCC_WR_POLICY(meta_write_policy) |
409 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
410 S_028410_CMASK_RD_POLICY(meta_read_policy) |
411 S_028410_FMASK_RD_POLICY(meta_read_policy) |
412 S_028410_DCC_RD_POLICY(meta_read_policy) |
413 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
414 radeon_set_context_reg(cs, R_028428_CB_COVERAGE_OUT_CONTROL, 0);
415
416 radeon_set_sh_reg(cs, R_00B0C0_SPI_SHADER_REQ_CTRL_PS,
417 S_00B0C0_SOFT_GROUPING_EN(1) |
418 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
419 radeon_set_sh_reg(cs, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
420
421 if (physical_device->rad_info.chip_class >= GFX10_3) {
422 radeon_set_context_reg(cs, R_028750_SX_PS_DOWNCONVERT_CONTROL_GFX103, 0xff);
423 }
424
425 if (physical_device->rad_info.chip_class == GFX10) {
426 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
427 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
428 radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
429 }
430
431 /* TODO: For culling, replace 128 with 256. */
432 radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC,
433 S_030980_OVERSUB_EN(physical_device->rad_info.use_late_alloc) |
434 S_030980_NUM_PC_LINES(128 * physical_device->rad_info.max_se - 1));
435 }
436
437 if (physical_device->rad_info.chip_class >= GFX9) {
438 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
439 S_028B50_ACCUM_ISOLINE(40) |
440 S_028B50_ACCUM_TRI(30) |
441 S_028B50_ACCUM_QUAD(24) |
442 S_028B50_DONUT_SPLIT(24) |
443 S_028B50_TRAP_SPLIT(6));
444 } else if (physical_device->rad_info.chip_class >= GFX8) {
445 uint32_t vgt_tess_distribution;
446
447 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
448 S_028B50_ACCUM_TRI(11) |
449 S_028B50_ACCUM_QUAD(11) |
450 S_028B50_DONUT_SPLIT(16);
451
452 if (physical_device->rad_info.family == CHIP_FIJI ||
453 physical_device->rad_info.family >= CHIP_POLARIS10)
454 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
455
456 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
457 vgt_tess_distribution);
458 } else if (!has_clear_state) {
459 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
460 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
461 }
462
463 if (device->border_color_data.bo) {
464 uint64_t border_color_va = radv_buffer_get_va(device->border_color_data.bo);
465
466 radeon_set_context_reg(cs, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
467 if (physical_device->rad_info.chip_class >= GFX7) {
468 radeon_set_context_reg(cs, R_028084_TA_BC_BASE_ADDR_HI,
469 S_028084_ADDRESS(border_color_va >> 40));
470 }
471 }
472
473 if (physical_device->rad_info.chip_class >= GFX9) {
474 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
475 S_028C48_MAX_ALLOC_COUNT(physical_device->rad_info.pbb_max_alloc_count - 1) |
476 S_028C48_MAX_PRIM_PER_BATCH(1023));
477 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
478 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
479 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
480 }
481
482 unsigned tmp = (unsigned)(1.0 * 8.0);
483 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
484 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
485 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
486 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
487 S_028A04_MAX_SIZE(radv_pack_float_12p4(8191.875/2)));
488
489 if (!has_clear_state) {
490 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
491 S_028004_ZPASS_INCREMENT_DISABLE(1));
492 }
493
494 /* Enable the Polaris small primitive filter control.
495 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
496 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
497 * and AMDVLK doesn't have a workaround as well.
498 */
499 if (physical_device->rad_info.family >= CHIP_POLARIS10) {
500 unsigned small_prim_filter_cntl =
501 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
502 /* Workaround for a hw line bug. */
503 S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12);
504
505 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
506 small_prim_filter_cntl);
507 }
508
509 si_emit_compute(physical_device, cs);
510 }
511
512 void
513 cik_create_gfx_config(struct radv_device *device)
514 {
515 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX);
516 if (!cs)
517 return;
518
519 si_emit_graphics(device, cs);
520
521 while (cs->cdw & 7) {
522 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
523 radeon_emit(cs, PKT2_NOP_PAD);
524 else
525 radeon_emit(cs, PKT3_NOP_PAD);
526 }
527
528 device->gfx_init = device->ws->buffer_create(device->ws,
529 cs->cdw * 4, 4096,
530 RADEON_DOMAIN_GTT,
531 RADEON_FLAG_CPU_ACCESS|
532 RADEON_FLAG_NO_INTERPROCESS_SHARING |
533 RADEON_FLAG_READ_ONLY |
534 RADEON_FLAG_GTT_WC,
535 RADV_BO_PRIORITY_CS);
536 if (!device->gfx_init)
537 goto fail;
538
539 void *map = device->ws->buffer_map(device->gfx_init);
540 if (!map) {
541 device->ws->buffer_destroy(device->gfx_init);
542 device->gfx_init = NULL;
543 goto fail;
544 }
545 memcpy(map, cs->buf, cs->cdw * 4);
546
547 device->ws->buffer_unmap(device->gfx_init);
548 device->gfx_init_size_dw = cs->cdw;
549 fail:
550 device->ws->cs_destroy(cs);
551 }
552
553 static void
554 get_viewport_xform(const VkViewport *viewport,
555 float scale[3], float translate[3])
556 {
557 float x = viewport->x;
558 float y = viewport->y;
559 float half_width = 0.5f * viewport->width;
560 float half_height = 0.5f * viewport->height;
561 double n = viewport->minDepth;
562 double f = viewport->maxDepth;
563
564 scale[0] = half_width;
565 translate[0] = half_width + x;
566 scale[1] = half_height;
567 translate[1] = half_height + y;
568
569 scale[2] = (f - n);
570 translate[2] = n;
571 }
572
573 void
574 si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
575 int count, const VkViewport *viewports)
576 {
577 int i;
578
579 assert(count);
580 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
581 first_vp * 4 * 6, count * 6);
582
583 for (i = 0; i < count; i++) {
584 float scale[3], translate[3];
585
586
587 get_viewport_xform(&viewports[i], scale, translate);
588 radeon_emit(cs, fui(scale[0]));
589 radeon_emit(cs, fui(translate[0]));
590 radeon_emit(cs, fui(scale[1]));
591 radeon_emit(cs, fui(translate[1]));
592 radeon_emit(cs, fui(scale[2]));
593 radeon_emit(cs, fui(translate[2]));
594 }
595
596 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
597 first_vp * 4 * 2, count * 2);
598 for (i = 0; i < count; i++) {
599 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
600 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
601 radeon_emit(cs, fui(zmin));
602 radeon_emit(cs, fui(zmax));
603 }
604 }
605
606 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
607 {
608 float scale[3], translate[3];
609 VkRect2D rect;
610
611 get_viewport_xform(viewport, scale, translate);
612
613 rect.offset.x = translate[0] - fabsf(scale[0]);
614 rect.offset.y = translate[1] - fabsf(scale[1]);
615 rect.extent.width = ceilf(translate[0] + fabsf(scale[0])) - rect.offset.x;
616 rect.extent.height = ceilf(translate[1] + fabsf(scale[1])) - rect.offset.y;
617
618 return rect;
619 }
620
621 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
622 VkRect2D ret;
623 ret.offset.x = MAX2(a->offset.x, b->offset.x);
624 ret.offset.y = MAX2(a->offset.y, b->offset.y);
625 ret.extent.width = MIN2(a->offset.x + a->extent.width,
626 b->offset.x + b->extent.width) - ret.offset.x;
627 ret.extent.height = MIN2(a->offset.y + a->extent.height,
628 b->offset.y + b->extent.height) - ret.offset.y;
629 return ret;
630 }
631
632 void
633 si_write_scissors(struct radeon_cmdbuf *cs, int first,
634 int count, const VkRect2D *scissors,
635 const VkViewport *viewports, bool can_use_guardband)
636 {
637 int i;
638 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
639 const float max_range = 32767.0f;
640 if (!count)
641 return;
642
643 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
644 for (i = 0; i < count; i++) {
645 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
646 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
647
648 get_viewport_xform(viewports + i, scale, translate);
649 scale[0] = fabsf(scale[0]);
650 scale[1] = fabsf(scale[1]);
651
652 if (scale[0] < 0.5)
653 scale[0] = 0.5;
654 if (scale[1] < 0.5)
655 scale[1] = 0.5;
656
657 guardband_x = MIN2(guardband_x, (max_range - fabsf(translate[0])) / scale[0]);
658 guardband_y = MIN2(guardband_y, (max_range - fabsf(translate[1])) / scale[1]);
659
660 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
661 S_028250_TL_Y(scissor.offset.y) |
662 S_028250_WINDOW_OFFSET_DISABLE(1));
663 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
664 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
665 }
666 if (!can_use_guardband) {
667 guardband_x = 1.0;
668 guardband_y = 1.0;
669 }
670
671 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
672 radeon_emit(cs, fui(guardband_y));
673 radeon_emit(cs, fui(1.0));
674 radeon_emit(cs, fui(guardband_x));
675 radeon_emit(cs, fui(1.0));
676 }
677
678 static inline unsigned
679 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
680 {
681 if (num == 0)
682 return 0;
683
684 if (info->incr == 0)
685 return 0;
686
687 if (num < info->min)
688 return 0;
689
690 return 1 + ((num - info->min) / info->incr);
691 }
692
693 static const struct radv_prim_vertex_count prim_size_table[] = {
694 [V_008958_DI_PT_NONE] = {0, 0},
695 [V_008958_DI_PT_POINTLIST] = {1, 1},
696 [V_008958_DI_PT_LINELIST] = {2, 2},
697 [V_008958_DI_PT_LINESTRIP] = {2, 1},
698 [V_008958_DI_PT_TRILIST] = {3, 3},
699 [V_008958_DI_PT_TRIFAN] = {3, 1},
700 [V_008958_DI_PT_TRISTRIP] = {3, 1},
701 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
702 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
703 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
704 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
705 [V_008958_DI_PT_RECTLIST] = {3, 3},
706 [V_008958_DI_PT_LINELOOP] = {2, 1},
707 [V_008958_DI_PT_POLYGON] = {3, 1},
708 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
709 };
710
711 uint32_t
712 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
713 bool instanced_draw, bool indirect_draw,
714 bool count_from_stream_output,
715 uint32_t draw_vertex_count,
716 unsigned topology)
717 {
718 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
719 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
720 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
721 const unsigned max_primgroup_in_wave = 2;
722 /* SWITCH_ON_EOP(0) is always preferable. */
723 bool wd_switch_on_eop = false;
724 bool ia_switch_on_eop = false;
725 bool ia_switch_on_eoi = false;
726 bool partial_vs_wave = false;
727 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave;
728 bool multi_instances_smaller_than_primgroup;
729 struct radv_prim_vertex_count prim_vertex_count = prim_size_table[topology];
730
731 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline)) {
732 if (topology == V_008958_DI_PT_PATCH) {
733 prim_vertex_count.min = cmd_buffer->state.pipeline->graphics.tess_patch_control_points;
734 prim_vertex_count.incr = 1;
735 }
736 }
737
738 multi_instances_smaller_than_primgroup = indirect_draw;
739 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
740 uint32_t num_prims = radv_prims_for_vertices(&prim_vertex_count, draw_vertex_count);
741 if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size)
742 multi_instances_smaller_than_primgroup = true;
743 }
744
745 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
746 partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
747
748 if (chip_class >= GFX7) {
749 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
750 * 4 shader engines. Set 1 to pass the assertion below.
751 * The other cases are hardware requirements. */
752 if (cmd_buffer->device->physical_device->rad_info.max_se < 4 ||
753 topology == V_008958_DI_PT_POLYGON ||
754 topology == V_008958_DI_PT_LINELOOP ||
755 topology == V_008958_DI_PT_TRIFAN ||
756 topology == V_008958_DI_PT_TRISTRIP_ADJ ||
757 (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
758 (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
759 (topology != V_008958_DI_PT_POINTLIST &&
760 topology != V_008958_DI_PT_LINESTRIP))))
761 wd_switch_on_eop = true;
762
763 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
764 * We don't know that for indirect drawing, so treat it as
765 * always problematic. */
766 if (family == CHIP_HAWAII &&
767 (instanced_draw || indirect_draw))
768 wd_switch_on_eop = true;
769
770 /* Performance recommendation for 4 SE Gfx7-8 parts if
771 * instances are smaller than a primgroup.
772 * Assume indirect draws always use small instances.
773 * This is needed for good VS wave utilization.
774 */
775 if (chip_class <= GFX8 &&
776 info->max_se == 4 &&
777 multi_instances_smaller_than_primgroup)
778 wd_switch_on_eop = true;
779
780 /* Required on GFX7 and later. */
781 if (info->max_se > 2 && !wd_switch_on_eop)
782 ia_switch_on_eoi = true;
783
784 /* Required by Hawaii and, for some special cases, by GFX8. */
785 if (ia_switch_on_eoi &&
786 (family == CHIP_HAWAII ||
787 (chip_class == GFX8 &&
788 /* max primgroup in wave is always 2 - leave this for documentation */
789 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
790 partial_vs_wave = true;
791
792 /* Instancing bug on Bonaire. */
793 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
794 (instanced_draw || indirect_draw))
795 partial_vs_wave = true;
796
797 /* Hardware requirement when drawing primitives from a stream
798 * output buffer.
799 */
800 if (count_from_stream_output)
801 wd_switch_on_eop = true;
802
803 /* If the WD switch is false, the IA switch must be false too. */
804 assert(wd_switch_on_eop || !ia_switch_on_eop);
805 }
806 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
807 if (chip_class <= GFX8 && ia_switch_on_eoi)
808 partial_es_wave = true;
809
810 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
811 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
812 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
813 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
814 */
815 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
816 bool set_vgt_flush = indirect_draw;
817 if (!set_vgt_flush && instanced_draw) {
818 uint32_t num_prims = radv_prims_for_vertices(&prim_vertex_count, draw_vertex_count);
819 if (num_prims <= 1)
820 set_vgt_flush = true;
821 }
822 if (set_vgt_flush)
823 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
824 }
825 }
826
827 /* Workaround for a VGT hang when strip primitive types are used with
828 * primitive restart.
829 */
830 if (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
831 (topology == V_008958_DI_PT_LINESTRIP ||
832 topology == V_008958_DI_PT_TRISTRIP ||
833 topology == V_008958_DI_PT_LINESTRIP_ADJ ||
834 topology == V_008958_DI_PT_TRISTRIP_ADJ)) {
835 partial_vs_wave = true;
836 }
837
838 return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base |
839 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
840 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
841 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
842 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
843 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= GFX7 ? wd_switch_on_eop : 0);
844
845 }
846
847 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
848 enum chip_class chip_class,
849 bool is_mec,
850 unsigned event, unsigned event_flags,
851 unsigned dst_sel, unsigned data_sel,
852 uint64_t va,
853 uint32_t new_fence,
854 uint64_t gfx9_eop_bug_va)
855 {
856 unsigned op = EVENT_TYPE(event) |
857 EVENT_INDEX(event == V_028A90_CS_DONE ||
858 event == V_028A90_PS_DONE ? 6 : 5) |
859 event_flags;
860 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
861 unsigned sel = EOP_DST_SEL(dst_sel) |
862 EOP_DATA_SEL(data_sel);
863
864 /* Wait for write confirmation before writing data, but don't send
865 * an interrupt. */
866 if (data_sel != EOP_DATA_SEL_DISCARD)
867 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
868
869 if (chip_class >= GFX9 || is_gfx8_mec) {
870 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
871 * counters) must immediately precede every timestamp event to
872 * prevent a GPU hang on GFX9.
873 */
874 if (chip_class == GFX9 && !is_mec) {
875 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
876 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
877 radeon_emit(cs, gfx9_eop_bug_va);
878 radeon_emit(cs, gfx9_eop_bug_va >> 32);
879 }
880
881 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false));
882 radeon_emit(cs, op);
883 radeon_emit(cs, sel);
884 radeon_emit(cs, va); /* address lo */
885 radeon_emit(cs, va >> 32); /* address hi */
886 radeon_emit(cs, new_fence); /* immediate data lo */
887 radeon_emit(cs, 0); /* immediate data hi */
888 if (!is_gfx8_mec)
889 radeon_emit(cs, 0); /* unused */
890 } else {
891 if (chip_class == GFX7 ||
892 chip_class == GFX8) {
893 /* Two EOP events are required to make all engines go idle
894 * (and optional cache flushes executed) before the timestamp
895 * is written.
896 */
897 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
898 radeon_emit(cs, op);
899 radeon_emit(cs, va);
900 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
901 radeon_emit(cs, 0); /* immediate data */
902 radeon_emit(cs, 0); /* unused */
903 }
904
905 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
906 radeon_emit(cs, op);
907 radeon_emit(cs, va);
908 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
909 radeon_emit(cs, new_fence); /* immediate data */
910 radeon_emit(cs, 0); /* unused */
911 }
912 }
913
914 void
915 radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
916 uint32_t ref, uint32_t mask)
917 {
918 assert(op == WAIT_REG_MEM_EQUAL ||
919 op == WAIT_REG_MEM_NOT_EQUAL ||
920 op == WAIT_REG_MEM_GREATER_OR_EQUAL);
921
922 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false));
923 radeon_emit(cs, op | WAIT_REG_MEM_MEM_SPACE(1));
924 radeon_emit(cs, va);
925 radeon_emit(cs, va >> 32);
926 radeon_emit(cs, ref); /* reference value */
927 radeon_emit(cs, mask); /* mask */
928 radeon_emit(cs, 4); /* poll interval */
929 }
930
931 static void
932 si_emit_acquire_mem(struct radeon_cmdbuf *cs,
933 bool is_mec,
934 bool is_gfx9,
935 unsigned cp_coher_cntl)
936 {
937 if (is_mec || is_gfx9) {
938 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
939 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) |
940 PKT3_SHADER_TYPE_S(is_mec));
941 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
942 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
943 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
944 radeon_emit(cs, 0); /* CP_COHER_BASE */
945 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
946 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
947 } else {
948 /* ACQUIRE_MEM is only required on a compute ring. */
949 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false));
950 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
951 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
952 radeon_emit(cs, 0); /* CP_COHER_BASE */
953 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
954 }
955 }
956
957 static void
958 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
959 enum chip_class chip_class,
960 uint32_t *flush_cnt,
961 uint64_t flush_va,
962 bool is_mec,
963 enum radv_cmd_flush_bits flush_bits,
964 uint64_t gfx9_eop_bug_va)
965 {
966 uint32_t gcr_cntl = 0;
967 unsigned cb_db_event = 0;
968
969 /* We don't need these. */
970 assert(!(flush_bits & (RADV_CMD_FLAG_VGT_STREAMOUT_SYNC)));
971
972 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
973 gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
974 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE) {
975 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
976 * to FORWARD when both L1 and L2 are written out (WB or INV).
977 */
978 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
979 }
980 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE)
981 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
982 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
983 /* Writeback and invalidate everything in L2. */
984 gcr_cntl |= S_586_GL2_INV(1) | S_586_GL2_WB(1) |
985 S_586_GLM_INV(1) | S_586_GLM_WB(1);
986 } else if (flush_bits & RADV_CMD_FLAG_WB_L2) {
987 /* Writeback but do not invalidate.
988 * GLM doesn't support WB alone. If WB is set, INV must be set too.
989 */
990 gcr_cntl |= S_586_GL2_WB(1) |
991 S_586_GLM_WB(1) | S_586_GLM_INV(1);
992 }
993
994 /* TODO: Implement this new flag for GFX9+.
995 else if (flush_bits & RADV_CMD_FLAG_INV_L2_METADATA)
996 gcr_cntl |= S_586_GLM_INV(1) | S_586_GLM_WB(1);
997 */
998
999 if (flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
1000 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_CB_META */
1001 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
1002 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
1003 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1004 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
1005 EVENT_INDEX(0));
1006 }
1007
1008 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_DB_META ? */
1009 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
1010 /* Flush HTILE. Will wait for idle later. */
1011 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1012 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) |
1013 EVENT_INDEX(0));
1014 }
1015
1016 /* First flush CB/DB, then L1/L2. */
1017 gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
1018
1019 if ((flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) ==
1020 (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
1021 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1022 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
1023 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1024 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
1025 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1026 } else {
1027 assert(0);
1028 }
1029 } else {
1030 /* Wait for graphics shaders to go idle if requested. */
1031 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
1032 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1033 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1034 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
1035 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1036 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1037 }
1038 }
1039
1040 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
1041 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1042 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
1043 }
1044
1045 if (cb_db_event) {
1046 /* CB/DB flush and invalidate (or possibly just a wait for a
1047 * meta flush) via RELEASE_MEM.
1048 *
1049 * Combine this with other cache flushes when possible; this
1050 * requires affected shaders to be idle, so do it after the
1051 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
1052 * implied).
1053 */
1054 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
1055 unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
1056 unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
1057 unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
1058 unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
1059 assert(G_586_GL2_US(gcr_cntl) == 0);
1060 assert(G_586_GL2_RANGE(gcr_cntl) == 0);
1061 assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
1062 unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
1063 unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
1064 unsigned gcr_seq = G_586_SEQ(gcr_cntl);
1065
1066 gcr_cntl &= C_586_GLM_WB &
1067 C_586_GLM_INV &
1068 C_586_GLV_INV &
1069 C_586_GL1_INV &
1070 C_586_GL2_INV &
1071 C_586_GL2_WB; /* keep SEQ */
1072
1073 assert(flush_cnt);
1074 (*flush_cnt)++;
1075
1076 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event,
1077 S_490_GLM_WB(glm_wb) |
1078 S_490_GLM_INV(glm_inv) |
1079 S_490_GLV_INV(glv_inv) |
1080 S_490_GL1_INV(gl1_inv) |
1081 S_490_GL2_INV(gl2_inv) |
1082 S_490_GL2_WB(gl2_wb) |
1083 S_490_SEQ(gcr_seq),
1084 EOP_DST_SEL_MEM,
1085 EOP_DATA_SEL_VALUE_32BIT,
1086 flush_va, *flush_cnt,
1087 gfx9_eop_bug_va);
1088
1089 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
1090 *flush_cnt, 0xffffffff);
1091 }
1092
1093 /* VGT state sync */
1094 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1095 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1096 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1097 }
1098
1099 /* Ignore fields that only modify the behavior of other fields. */
1100 if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
1101 /* Flush caches and wait for the caches to assert idle.
1102 * The cache flush is executed in the ME, but the PFP waits
1103 * for completion.
1104 */
1105 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
1106 radeon_emit(cs, 0); /* CP_COHER_CNTL */
1107 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1108 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1109 radeon_emit(cs, 0); /* CP_COHER_BASE */
1110 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1111 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1112 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
1113 } else if ((cb_db_event ||
1114 (flush_bits & (RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1115 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1116 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)))
1117 && !is_mec) {
1118 /* We need to ensure that PFP waits as well. */
1119 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1120 radeon_emit(cs, 0);
1121 }
1122
1123 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1124 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1125 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1126 EVENT_INDEX(0));
1127 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1128 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1129 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1130 EVENT_INDEX(0));
1131 }
1132 }
1133
1134 void
1135 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1136 enum chip_class chip_class,
1137 uint32_t *flush_cnt,
1138 uint64_t flush_va,
1139 bool is_mec,
1140 enum radv_cmd_flush_bits flush_bits,
1141 uint64_t gfx9_eop_bug_va)
1142 {
1143 unsigned cp_coher_cntl = 0;
1144 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1145 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
1146
1147 if (chip_class >= GFX10) {
1148 /* GFX10 cache flush handling is quite different. */
1149 gfx10_cs_emit_cache_flush(cs, chip_class, flush_cnt, flush_va,
1150 is_mec, flush_bits, gfx9_eop_bug_va);
1151 return;
1152 }
1153
1154 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
1155 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1156 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE)
1157 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1158
1159 if (chip_class <= GFX8) {
1160 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
1161 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
1162 S_0085F0_CB0_DEST_BASE_ENA(1) |
1163 S_0085F0_CB1_DEST_BASE_ENA(1) |
1164 S_0085F0_CB2_DEST_BASE_ENA(1) |
1165 S_0085F0_CB3_DEST_BASE_ENA(1) |
1166 S_0085F0_CB4_DEST_BASE_ENA(1) |
1167 S_0085F0_CB5_DEST_BASE_ENA(1) |
1168 S_0085F0_CB6_DEST_BASE_ENA(1) |
1169 S_0085F0_CB7_DEST_BASE_ENA(1);
1170
1171 /* Necessary for DCC */
1172 if (chip_class >= GFX8) {
1173 si_cs_emit_write_event_eop(cs,
1174 chip_class,
1175 is_mec,
1176 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
1177 0,
1178 EOP_DST_SEL_MEM,
1179 EOP_DATA_SEL_DISCARD,
1180 0, 0,
1181 gfx9_eop_bug_va);
1182 }
1183 }
1184 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
1185 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
1186 S_0085F0_DB_DEST_BASE_ENA(1);
1187 }
1188 }
1189
1190 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
1191 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1192 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1193 }
1194
1195 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
1196 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1197 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1198 }
1199
1200 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
1201 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1202 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1203 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
1204 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1205 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1206 }
1207
1208 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
1209 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1210 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1211 }
1212
1213 if (chip_class == GFX9 && flush_cb_db) {
1214 unsigned cb_db_event, tc_flags;
1215
1216 /* Set the CB/DB flush event. */
1217 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1218
1219 /* These are the only allowed combinations. If you need to
1220 * do multiple operations at once, do them separately.
1221 * All operations that invalidate L2 also seem to invalidate
1222 * metadata. Volatile (VOL) and WC flushes are not listed here.
1223 *
1224 * TC | TC_WB = writeback & invalidate L2 & L1
1225 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1226 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1227 * TC | TC_NC = invalidate L2 for MTYPE == NC
1228 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1229 * TCL1 = invalidate L1
1230 */
1231 tc_flags = EVENT_TC_ACTION_ENA |
1232 EVENT_TC_MD_ACTION_ENA;
1233
1234 /* Ideally flush TC together with CB/DB. */
1235 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
1236 /* Writeback and invalidate everything in L2 & L1. */
1237 tc_flags = EVENT_TC_ACTION_ENA |
1238 EVENT_TC_WB_ACTION_ENA;
1239
1240
1241 /* Clear the flags. */
1242 flush_bits &= ~(RADV_CMD_FLAG_INV_L2 |
1243 RADV_CMD_FLAG_WB_L2 |
1244 RADV_CMD_FLAG_INV_VCACHE);
1245 }
1246 assert(flush_cnt);
1247 (*flush_cnt)++;
1248
1249 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags,
1250 EOP_DST_SEL_MEM,
1251 EOP_DATA_SEL_VALUE_32BIT,
1252 flush_va, *flush_cnt,
1253 gfx9_eop_bug_va);
1254 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
1255 *flush_cnt, 0xffffffff);
1256 }
1257
1258 /* VGT state sync */
1259 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1260 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1261 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1262 }
1263
1264 /* VGT streamout state sync */
1265 if (flush_bits & RADV_CMD_FLAG_VGT_STREAMOUT_SYNC) {
1266 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1267 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1268 }
1269
1270 /* Make sure ME is idle (it executes most packets) before continuing.
1271 * This prevents read-after-write hazards between PFP and ME.
1272 */
1273 if ((cp_coher_cntl ||
1274 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1275 RADV_CMD_FLAG_INV_VCACHE |
1276 RADV_CMD_FLAG_INV_L2 |
1277 RADV_CMD_FLAG_WB_L2))) &&
1278 !is_mec) {
1279 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1280 radeon_emit(cs, 0);
1281 }
1282
1283 if ((flush_bits & RADV_CMD_FLAG_INV_L2) ||
1284 (chip_class <= GFX7 && (flush_bits & RADV_CMD_FLAG_WB_L2))) {
1285 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9,
1286 cp_coher_cntl |
1287 S_0085F0_TC_ACTION_ENA(1) |
1288 S_0085F0_TCL1_ACTION_ENA(1) |
1289 S_0301F0_TC_WB_ACTION_ENA(chip_class >= GFX8));
1290 cp_coher_cntl = 0;
1291 } else {
1292 if(flush_bits & RADV_CMD_FLAG_WB_L2) {
1293 /* WB = write-back
1294 * NC = apply to non-coherent MTYPEs
1295 * (i.e. MTYPE <= 1, which is what we use everywhere)
1296 *
1297 * WB doesn't work without NC.
1298 */
1299 si_emit_acquire_mem(cs, is_mec,
1300 chip_class == GFX9,
1301 cp_coher_cntl |
1302 S_0301F0_TC_WB_ACTION_ENA(1) |
1303 S_0301F0_TC_NC_ACTION_ENA(1));
1304 cp_coher_cntl = 0;
1305 }
1306 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE) {
1307 si_emit_acquire_mem(cs, is_mec,
1308 chip_class == GFX9,
1309 cp_coher_cntl |
1310 S_0085F0_TCL1_ACTION_ENA(1));
1311 cp_coher_cntl = 0;
1312 }
1313 }
1314
1315 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1316 * Therefore, it should be last. Done in PFP.
1317 */
1318 if (cp_coher_cntl)
1319 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9, cp_coher_cntl);
1320
1321 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1322 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1323 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1324 EVENT_INDEX(0));
1325 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1326 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1327 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1328 EVENT_INDEX(0));
1329 }
1330 }
1331
1332 void
1333 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
1334 {
1335 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1336
1337 if (is_compute)
1338 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1339 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1340 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1341 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1342 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1343 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1344 RADV_CMD_FLAG_VGT_FLUSH |
1345 RADV_CMD_FLAG_START_PIPELINE_STATS |
1346 RADV_CMD_FLAG_STOP_PIPELINE_STATS);
1347
1348 if (!cmd_buffer->state.flush_bits)
1349 return;
1350
1351 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1352
1353 si_cs_emit_cache_flush(cmd_buffer->cs,
1354 cmd_buffer->device->physical_device->rad_info.chip_class,
1355 &cmd_buffer->gfx9_fence_idx,
1356 cmd_buffer->gfx9_fence_va,
1357 radv_cmd_buffer_uses_mec(cmd_buffer),
1358 cmd_buffer->state.flush_bits,
1359 cmd_buffer->gfx9_eop_bug_va);
1360
1361
1362 if (unlikely(cmd_buffer->device->trace_bo))
1363 radv_cmd_buffer_trace_emit(cmd_buffer);
1364
1365 /* Clear the caches that have been flushed to avoid syncing too much
1366 * when there is some pending active queries.
1367 */
1368 cmd_buffer->active_query_flush_bits &= ~cmd_buffer->state.flush_bits;
1369
1370 cmd_buffer->state.flush_bits = 0;
1371
1372 /* If the driver used a compute shader for resetting a query pool, it
1373 * should be finished at this point.
1374 */
1375 cmd_buffer->pending_reset_query = false;
1376 }
1377
1378 /* sets the CP predication state using a boolean stored at va */
1379 void
1380 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1381 bool draw_visible, uint64_t va)
1382 {
1383 uint32_t op = 0;
1384
1385 if (va) {
1386 op = PRED_OP(PREDICATION_OP_BOOL64);
1387
1388 /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
1389 * zero, all rendering commands are discarded. Otherwise, they
1390 * are discarded if the value is non zero.
1391 */
1392 op |= draw_visible ? PREDICATION_DRAW_VISIBLE :
1393 PREDICATION_DRAW_NOT_VISIBLE;
1394 }
1395 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1396 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1397 radeon_emit(cmd_buffer->cs, op);
1398 radeon_emit(cmd_buffer->cs, va);
1399 radeon_emit(cmd_buffer->cs, va >> 32);
1400 } else {
1401 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1402 radeon_emit(cmd_buffer->cs, va);
1403 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1404 }
1405 }
1406
1407 /* Set this if you want the 3D engine to wait until CP DMA is done.
1408 * It should be set on the last CP DMA packet. */
1409 #define CP_DMA_SYNC (1 << 0)
1410
1411 /* Set this if the source data was used as a destination in a previous CP DMA
1412 * packet. It's for preventing a read-after-write (RAW) hazard between two
1413 * CP DMA packets. */
1414 #define CP_DMA_RAW_WAIT (1 << 1)
1415 #define CP_DMA_USE_L2 (1 << 2)
1416 #define CP_DMA_CLEAR (1 << 3)
1417
1418 /* Alignment for optimal performance. */
1419 #define SI_CPDMA_ALIGNMENT 32
1420
1421 /* The max number of bytes that can be copied per packet. */
1422 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1423 {
1424 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1425 S_414_BYTE_COUNT_GFX9(~0u) :
1426 S_414_BYTE_COUNT_GFX6(~0u);
1427
1428 /* make it aligned for optimal performance */
1429 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1430 }
1431
1432 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1433 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1434 * clear value.
1435 */
1436 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1437 uint64_t dst_va, uint64_t src_va,
1438 unsigned size, unsigned flags)
1439 {
1440 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1441 uint32_t header = 0, command = 0;
1442
1443 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1444
1445 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1446 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1447 command |= S_414_BYTE_COUNT_GFX9(size);
1448 else
1449 command |= S_414_BYTE_COUNT_GFX6(size);
1450
1451 /* Sync flags. */
1452 if (flags & CP_DMA_SYNC)
1453 header |= S_411_CP_SYNC(1);
1454 else {
1455 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1456 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1457 else
1458 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1459 }
1460
1461 if (flags & CP_DMA_RAW_WAIT)
1462 command |= S_414_RAW_WAIT(1);
1463
1464 /* Src and dst flags. */
1465 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1466 !(flags & CP_DMA_CLEAR) &&
1467 src_va == dst_va)
1468 header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
1469 else if (flags & CP_DMA_USE_L2)
1470 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
1471
1472 if (flags & CP_DMA_CLEAR)
1473 header |= S_411_SRC_SEL(V_411_DATA);
1474 else if (flags & CP_DMA_USE_L2)
1475 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1476
1477 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1478 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1479 radeon_emit(cs, header);
1480 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1481 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1482 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1483 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1484 radeon_emit(cs, command);
1485 } else {
1486 assert(!(flags & CP_DMA_USE_L2));
1487 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1488 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1489 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1490 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1491 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1492 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1493 radeon_emit(cs, command);
1494 }
1495
1496 /* CP DMA is executed in ME, but index buffers are read by PFP.
1497 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1498 * indices. If we wanted to execute CP DMA in PFP, this packet
1499 * should precede it.
1500 */
1501 if (flags & CP_DMA_SYNC) {
1502 if (cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1503 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1504 radeon_emit(cs, 0);
1505 }
1506
1507 /* CP will see the sync flag and wait for all DMAs to complete. */
1508 cmd_buffer->state.dma_is_busy = false;
1509 }
1510
1511 if (unlikely(cmd_buffer->device->trace_bo))
1512 radv_cmd_buffer_trace_emit(cmd_buffer);
1513 }
1514
1515 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1516 unsigned size)
1517 {
1518 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1519 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1520
1521 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1522 aligned_size, CP_DMA_USE_L2);
1523 }
1524
1525 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1526 uint64_t remaining_size, unsigned *flags)
1527 {
1528
1529 /* Flush the caches for the first copy only.
1530 * Also wait for the previous CP DMA operations.
1531 */
1532 if (cmd_buffer->state.flush_bits) {
1533 si_emit_cache_flush(cmd_buffer);
1534 *flags |= CP_DMA_RAW_WAIT;
1535 }
1536
1537 /* Do the synchronization after the last dma, so that all data
1538 * is written to memory.
1539 */
1540 if (byte_count == remaining_size)
1541 *flags |= CP_DMA_SYNC;
1542 }
1543
1544 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1545 {
1546 uint64_t va;
1547 uint32_t offset;
1548 unsigned dma_flags = 0;
1549 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1550 void *ptr;
1551
1552 assert(size < SI_CPDMA_ALIGNMENT);
1553
1554 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1555
1556 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1557 va += offset;
1558
1559 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1560
1561 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1562 dma_flags);
1563 }
1564
1565 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1566 uint64_t src_va, uint64_t dest_va,
1567 uint64_t size)
1568 {
1569 uint64_t main_src_va, main_dest_va;
1570 uint64_t skipped_size = 0, realign_size = 0;
1571
1572 /* Assume that we are not going to sync after the last DMA operation. */
1573 cmd_buffer->state.dma_is_busy = true;
1574
1575 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1576 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1577 /* If the size is not aligned, we must add a dummy copy at the end
1578 * just to align the internal counter. Otherwise, the DMA engine
1579 * would slow down by an order of magnitude for following copies.
1580 */
1581 if (size % SI_CPDMA_ALIGNMENT)
1582 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1583
1584 /* If the copy begins unaligned, we must start copying from the next
1585 * aligned block and the skipped part should be copied after everything
1586 * else has been copied. Only the src alignment matters, not dst.
1587 */
1588 if (src_va % SI_CPDMA_ALIGNMENT) {
1589 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1590 /* The main part will be skipped if the size is too small. */
1591 skipped_size = MIN2(skipped_size, size);
1592 size -= skipped_size;
1593 }
1594 }
1595 main_src_va = src_va + skipped_size;
1596 main_dest_va = dest_va + skipped_size;
1597
1598 while (size) {
1599 unsigned dma_flags = 0;
1600 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1601
1602 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1603 /* DMA operations via L2 are coherent and faster.
1604 * TODO: GFX7-GFX9 should also support this but it
1605 * requires tests/benchmarks.
1606 */
1607 dma_flags |= CP_DMA_USE_L2;
1608 }
1609
1610 si_cp_dma_prepare(cmd_buffer, byte_count,
1611 size + skipped_size + realign_size,
1612 &dma_flags);
1613
1614 dma_flags &= ~CP_DMA_SYNC;
1615
1616 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1617 byte_count, dma_flags);
1618
1619 size -= byte_count;
1620 main_src_va += byte_count;
1621 main_dest_va += byte_count;
1622 }
1623
1624 if (skipped_size) {
1625 unsigned dma_flags = 0;
1626
1627 si_cp_dma_prepare(cmd_buffer, skipped_size,
1628 size + skipped_size + realign_size,
1629 &dma_flags);
1630
1631 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1632 skipped_size, dma_flags);
1633 }
1634 if (realign_size)
1635 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1636 }
1637
1638 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1639 uint64_t size, unsigned value)
1640 {
1641
1642 if (!size)
1643 return;
1644
1645 assert(va % 4 == 0 && size % 4 == 0);
1646
1647 /* Assume that we are not going to sync after the last DMA operation. */
1648 cmd_buffer->state.dma_is_busy = true;
1649
1650 while (size) {
1651 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1652 unsigned dma_flags = CP_DMA_CLEAR;
1653
1654 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1655 /* DMA operations via L2 are coherent and faster.
1656 * TODO: GFX7-GFX9 should also support this but it
1657 * requires tests/benchmarks.
1658 */
1659 dma_flags |= CP_DMA_USE_L2;
1660 }
1661
1662 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1663
1664 /* Emit the clear packet. */
1665 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1666 dma_flags);
1667
1668 size -= byte_count;
1669 va += byte_count;
1670 }
1671 }
1672
1673 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
1674 {
1675 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX7)
1676 return;
1677
1678 if (!cmd_buffer->state.dma_is_busy)
1679 return;
1680
1681 /* Issue a dummy DMA that copies zero bytes.
1682 *
1683 * The DMA engine will see that there's no work to do and skip this
1684 * DMA request, however, the CP will see the sync flag and still wait
1685 * for all DMAs to complete.
1686 */
1687 si_emit_cp_dma(cmd_buffer, 0, 0, 0, CP_DMA_SYNC);
1688
1689 cmd_buffer->state.dma_is_busy = false;
1690 }
1691
1692 /* For MSAA sample positions. */
1693 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1694 ((((unsigned)(s0x) & 0xf) << 0) | (((unsigned)(s0y) & 0xf) << 4) | \
1695 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1696 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1697 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1698
1699 /* For obtaining location coordinates from registers */
1700 #define SEXT4(x) ((int)((x) | ((x) & 0x8 ? 0xfffffff0 : 0)))
1701 #define GET_SFIELD(reg, index) SEXT4(((reg) >> ((index) * 4)) & 0xf)
1702 #define GET_SX(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2)
1703 #define GET_SY(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2 + 1)
1704
1705 /* 1x MSAA */
1706 static const uint32_t sample_locs_1x =
1707 FILL_SREG(0, 0, 0, 0, 0, 0, 0, 0);
1708 static const unsigned max_dist_1x = 0;
1709 static const uint64_t centroid_priority_1x = 0x0000000000000000ull;
1710
1711 /* 2xMSAA */
1712 static const uint32_t sample_locs_2x =
1713 FILL_SREG(4,4, -4, -4, 0, 0, 0, 0);
1714 static const unsigned max_dist_2x = 4;
1715 static const uint64_t centroid_priority_2x = 0x1010101010101010ull;
1716
1717 /* 4xMSAA */
1718 static const uint32_t sample_locs_4x =
1719 FILL_SREG(-2,-6, 6, -2, -6, 2, 2, 6);
1720 static const unsigned max_dist_4x = 6;
1721 static const uint64_t centroid_priority_4x = 0x3210321032103210ull;
1722
1723 /* 8xMSAA */
1724 static const uint32_t sample_locs_8x[] = {
1725 FILL_SREG( 1,-3, -1, 3, 5, 1, -3,-5),
1726 FILL_SREG(-5, 5, -7,-1, 3, 7, 7,-7),
1727 /* The following are unused by hardware, but we emit them to IBs
1728 * instead of multiple SET_CONTEXT_REG packets. */
1729 0,
1730 0,
1731 };
1732 static const unsigned max_dist_8x = 7;
1733 static const uint64_t centroid_priority_8x = 0x7654321076543210ull;
1734
1735 unsigned radv_get_default_max_sample_dist(int log_samples)
1736 {
1737 unsigned max_dist[] = {
1738 max_dist_1x,
1739 max_dist_2x,
1740 max_dist_4x,
1741 max_dist_8x,
1742 };
1743 return max_dist[log_samples];
1744 }
1745
1746 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples)
1747 {
1748 switch (nr_samples) {
1749 default:
1750 case 1:
1751 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1752 radeon_emit(cs, (uint32_t)centroid_priority_1x);
1753 radeon_emit(cs, centroid_priority_1x >> 32);
1754 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_1x);
1755 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_1x);
1756 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_1x);
1757 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_1x);
1758 break;
1759 case 2:
1760 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1761 radeon_emit(cs, (uint32_t)centroid_priority_2x);
1762 radeon_emit(cs, centroid_priority_2x >> 32);
1763 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x);
1764 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x);
1765 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x);
1766 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x);
1767 break;
1768 case 4:
1769 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1770 radeon_emit(cs, (uint32_t)centroid_priority_4x);
1771 radeon_emit(cs, centroid_priority_4x >> 32);
1772 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x);
1773 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x);
1774 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x);
1775 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x);
1776 break;
1777 case 8:
1778 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1779 radeon_emit(cs, (uint32_t)centroid_priority_8x);
1780 radeon_emit(cs, centroid_priority_8x >> 32);
1781 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1782 radeon_emit_array(cs, sample_locs_8x, 4);
1783 radeon_emit_array(cs, sample_locs_8x, 4);
1784 radeon_emit_array(cs, sample_locs_8x, 4);
1785 radeon_emit_array(cs, sample_locs_8x, 2);
1786 break;
1787 }
1788 }
1789
1790 static void radv_get_sample_position(struct radv_device *device,
1791 unsigned sample_count,
1792 unsigned sample_index, float *out_value)
1793 {
1794 const uint32_t *sample_locs;
1795
1796 switch (sample_count) {
1797 case 1:
1798 default:
1799 sample_locs = &sample_locs_1x;
1800 break;
1801 case 2:
1802 sample_locs = &sample_locs_2x;
1803 break;
1804 case 4:
1805 sample_locs = &sample_locs_4x;
1806 break;
1807 case 8:
1808 sample_locs = sample_locs_8x;
1809 break;
1810 }
1811
1812 out_value[0] = (GET_SX(sample_locs, sample_index) + 8) / 16.0f;
1813 out_value[1] = (GET_SY(sample_locs, sample_index) + 8) / 16.0f;
1814 }
1815
1816 void radv_device_init_msaa(struct radv_device *device)
1817 {
1818 int i;
1819
1820 radv_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1821
1822 for (i = 0; i < 2; i++)
1823 radv_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1824 for (i = 0; i < 4; i++)
1825 radv_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1826 for (i = 0; i < 8; i++)
1827 radv_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1828 }