projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: get rid of buffer object priorities
[mesa.git] / src / amd / vulkan / winsys / amdgpu / radv_amdgpu_cs.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <stdlib.h>
26 #include <amdgpu.h>
27 #include <amdgpu_drm.h>
28 #include <assert.h>
29 #include <pthread.h>
30 #include <errno.h>
31
32 #include "ac_debug.h"
33 #include "radv_radeon_winsys.h"
34 #include "radv_amdgpu_cs.h"
35 #include "radv_amdgpu_bo.h"
36 #include "sid.h"
37
38
39 enum {
40 VIRTUAL_BUFFER_HASH_TABLE_SIZE = 1024
41 };
42
43 struct radv_amdgpu_cs {
44 struct radeon_cmdbuf base;
45 struct radv_amdgpu_winsys *ws;
46
47 struct amdgpu_cs_ib_info ib;
48
49 struct radeon_winsys_bo *ib_buffer;
50 uint8_t *ib_mapped;
51 unsigned max_num_buffers;
52 unsigned num_buffers;
53 amdgpu_bo_handle *handles;
54
55 struct radeon_winsys_bo **old_ib_buffers;
56 unsigned num_old_ib_buffers;
57 unsigned max_num_old_ib_buffers;
58 unsigned *ib_size_ptr;
59 bool failed;
60 bool is_chained;
61
62 int buffer_hash_table[1024];
63 unsigned hw_ip;
64
65 unsigned num_virtual_buffers;
66 unsigned max_num_virtual_buffers;
67 struct radeon_winsys_bo **virtual_buffers;
68 int *virtual_buffer_hash_table;
69
70 /* For chips that don't support chaining. */
71 struct radeon_cmdbuf *old_cs_buffers;
72 unsigned num_old_cs_buffers;
73 };
74
75 static inline struct radv_amdgpu_cs *
76 radv_amdgpu_cs(struct radeon_cmdbuf *base)
77 {
78 return (struct radv_amdgpu_cs*)base;
79 }
80
81 static int ring_to_hw_ip(enum ring_type ring)
82 {
83 switch (ring) {
84 case RING_GFX:
85 return AMDGPU_HW_IP_GFX;
86 case RING_DMA:
87 return AMDGPU_HW_IP_DMA;
88 case RING_COMPUTE:
89 return AMDGPU_HW_IP_COMPUTE;
90 default:
91 unreachable("unsupported ring");
92 }
93 }
94
95 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx *ctx,
96 uint32_t ip_type,
97 uint32_t ring,
98 struct radv_winsys_sem_info *sem_info);
99 static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx,
100 struct amdgpu_cs_request *request,
101 struct radv_winsys_sem_info *sem_info);
102
103 static void radv_amdgpu_request_to_fence(struct radv_amdgpu_ctx *ctx,
104 struct radv_amdgpu_fence *fence,
105 struct amdgpu_cs_request *req)
106 {
107 fence->fence.context = ctx->ctx;
108 fence->fence.ip_type = req->ip_type;
109 fence->fence.ip_instance = req->ip_instance;
110 fence->fence.ring = req->ring;
111 fence->fence.fence = req->seq_no;
112 fence->user_ptr = (volatile uint64_t*)(ctx->fence_map + (req->ip_type * MAX_RINGS_PER_TYPE + req->ring) * sizeof(uint64_t));
113 }
114
115 static struct radeon_winsys_fence *radv_amdgpu_create_fence()
116 {
117 struct radv_amdgpu_fence *fence = calloc(1, sizeof(struct radv_amdgpu_fence));
118 return (struct radeon_winsys_fence*)fence;
119 }
120
121 static void radv_amdgpu_destroy_fence(struct radeon_winsys_fence *_fence)
122 {
123 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
124 free(fence);
125 }
126
127 static bool radv_amdgpu_fence_wait(struct radeon_winsys *_ws,
128 struct radeon_winsys_fence *_fence,
129 bool absolute,
130 uint64_t timeout)
131 {
132 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
133 unsigned flags = absolute ? AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE : 0;
134 int r;
135 uint32_t expired = 0;
136
137 if (fence->user_ptr) {
138 if (*fence->user_ptr >= fence->fence.fence)
139 return true;
140 if (!absolute && !timeout)
141 return false;
142 }
143
144 /* Now use the libdrm query. */
145 r = amdgpu_cs_query_fence_status(&fence->fence,
146 timeout,
147 flags,
148 &expired);
149
150 if (r) {
151 fprintf(stderr, "amdgpu: radv_amdgpu_cs_query_fence_status failed.\n");
152 return false;
153 }
154
155 if (expired)
156 return true;
157
158 return false;
159 }
160
161
162 static bool radv_amdgpu_fences_wait(struct radeon_winsys *_ws,
163 struct radeon_winsys_fence *const *_fences,
164 uint32_t fence_count,
165 bool wait_all,
166 uint64_t timeout)
167 {
168 struct amdgpu_cs_fence *fences = malloc(sizeof(struct amdgpu_cs_fence) * fence_count);
169 int r;
170 uint32_t expired = 0, first = 0;
171
172 if (!fences)
173 return false;
174
175 for (uint32_t i = 0; i < fence_count; ++i)
176 fences[i] = ((struct radv_amdgpu_fence *)_fences[i])->fence;
177
178 /* Now use the libdrm query. */
179 r = amdgpu_cs_wait_fences(fences, fence_count, wait_all,
180 timeout, &expired, &first);
181
182 free(fences);
183 if (r) {
184 fprintf(stderr, "amdgpu: amdgpu_cs_wait_fences failed.\n");
185 return false;
186 }
187
188 if (expired)
189 return true;
190
191 return false;
192 }
193
194 static void radv_amdgpu_cs_destroy(struct radeon_cmdbuf *rcs)
195 {
196 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(rcs);
197
198 if (cs->ib_buffer)
199 cs->ws->base.buffer_destroy(cs->ib_buffer);
200 else
201 free(cs->base.buf);
202
203 for (unsigned i = 0; i < cs->num_old_ib_buffers; ++i)
204 cs->ws->base.buffer_destroy(cs->old_ib_buffers[i]);
205
206 for (unsigned i = 0; i < cs->num_old_cs_buffers; ++i) {
207 struct radeon_cmdbuf *rcs = &cs->old_cs_buffers[i];
208 free(rcs->buf);
209 }
210
211 free(cs->old_cs_buffers);
212 free(cs->old_ib_buffers);
213 free(cs->virtual_buffers);
214 free(cs->virtual_buffer_hash_table);
215 free(cs->handles);
216 free(cs);
217 }
218
219 static void radv_amdgpu_init_cs(struct radv_amdgpu_cs *cs,
220 enum ring_type ring_type)
221 {
222 for (int i = 0; i < ARRAY_SIZE(cs->buffer_hash_table); ++i)
223 cs->buffer_hash_table[i] = -1;
224
225 cs->hw_ip = ring_to_hw_ip(ring_type);
226 }
227
228 static struct radeon_cmdbuf *
229 radv_amdgpu_cs_create(struct radeon_winsys *ws,
230 enum ring_type ring_type)
231 {
232 struct radv_amdgpu_cs *cs;
233 uint32_t ib_size = 20 * 1024 * 4;
234 cs = calloc(1, sizeof(struct radv_amdgpu_cs));
235 if (!cs)
236 return NULL;
237
238 cs->ws = radv_amdgpu_winsys(ws);
239 radv_amdgpu_init_cs(cs, ring_type);
240
241 if (cs->ws->use_ib_bos) {
242 cs->ib_buffer = ws->buffer_create(ws, ib_size, 0,
243 RADEON_DOMAIN_GTT,
244 RADEON_FLAG_CPU_ACCESS |
245 RADEON_FLAG_NO_INTERPROCESS_SHARING |
246 RADEON_FLAG_READ_ONLY);
247 if (!cs->ib_buffer) {
248 free(cs);
249 return NULL;
250 }
251
252 cs->ib_mapped = ws->buffer_map(cs->ib_buffer);
253 if (!cs->ib_mapped) {
254 ws->buffer_destroy(cs->ib_buffer);
255 free(cs);
256 return NULL;
257 }
258
259 cs->ib.ib_mc_address = radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va;
260 cs->base.buf = (uint32_t *)cs->ib_mapped;
261 cs->base.max_dw = ib_size / 4 - 4;
262 cs->ib_size_ptr = &cs->ib.size;
263 cs->ib.size = 0;
264
265 ws->cs_add_buffer(&cs->base, cs->ib_buffer);
266 } else {
267 cs->base.buf = malloc(16384);
268 cs->base.max_dw = 4096;
269 if (!cs->base.buf) {
270 free(cs);
271 return NULL;
272 }
273 }
274
275 return &cs->base;
276 }
277
278 static void radv_amdgpu_cs_grow(struct radeon_cmdbuf *_cs, size_t min_size)
279 {
280 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
281
282 if (cs->failed) {
283 cs->base.cdw = 0;
284 return;
285 }
286
287 if (!cs->ws->use_ib_bos) {
288 const uint64_t limit_dws = 0xffff8;
289 uint64_t ib_dws = MAX2(cs->base.cdw + min_size,
290 MIN2(cs->base.max_dw * 2, limit_dws));
291
292 /* The total ib size cannot exceed limit_dws dwords. */
293 if (ib_dws > limit_dws)
294 {
295 /* The maximum size in dwords has been reached,
296 * try to allocate a new one.
297 */
298 if (cs->num_old_cs_buffers + 1 >= AMDGPU_CS_MAX_IBS_PER_SUBMIT) {
299 /* TODO: Allow to submit more than 4 IBs. */
300 fprintf(stderr, "amdgpu: Maximum number of IBs "
301 "per submit reached.\n");
302 cs->failed = true;
303 cs->base.cdw = 0;
304 return;
305 }
306
307 cs->old_cs_buffers =
308 realloc(cs->old_cs_buffers,
309 (cs->num_old_cs_buffers + 1) * sizeof(*cs->old_cs_buffers));
310 if (!cs->old_cs_buffers) {
311 cs->failed = true;
312 cs->base.cdw = 0;
313 return;
314 }
315
316 /* Store the current one for submitting it later. */
317 cs->old_cs_buffers[cs->num_old_cs_buffers].cdw = cs->base.cdw;
318 cs->old_cs_buffers[cs->num_old_cs_buffers].max_dw = cs->base.max_dw;
319 cs->old_cs_buffers[cs->num_old_cs_buffers].buf = cs->base.buf;
320 cs->num_old_cs_buffers++;
321
322 /* Reset the cs, it will be re-allocated below. */
323 cs->base.cdw = 0;
324 cs->base.buf = NULL;
325
326 /* Re-compute the number of dwords to allocate. */
327 ib_dws = MAX2(cs->base.cdw + min_size,
328 MIN2(cs->base.max_dw * 2, limit_dws));
329 if (ib_dws > limit_dws) {
330 fprintf(stderr, "amdgpu: Too high number of "
331 "dwords to allocate\n");
332 cs->failed = true;
333 return;
334 }
335 }
336
337 uint32_t *new_buf = realloc(cs->base.buf, ib_dws * 4);
338 if (new_buf) {
339 cs->base.buf = new_buf;
340 cs->base.max_dw = ib_dws;
341 } else {
342 cs->failed = true;
343 cs->base.cdw = 0;
344 }
345 return;
346 }
347
348 uint64_t ib_size = MAX2(min_size * 4 + 16, cs->base.max_dw * 4 * 2);
349
350 /* max that fits in the chain size field. */
351 ib_size = MIN2(ib_size, 0xfffff);
352
353 while (!cs->base.cdw || (cs->base.cdw & 7) != 4)
354 radeon_emit(&cs->base, 0xffff1000);
355
356 *cs->ib_size_ptr |= cs->base.cdw + 4;
357
358 if (cs->num_old_ib_buffers == cs->max_num_old_ib_buffers) {
359 cs->max_num_old_ib_buffers = MAX2(1, cs->max_num_old_ib_buffers * 2);
360 cs->old_ib_buffers = realloc(cs->old_ib_buffers,
361 cs->max_num_old_ib_buffers * sizeof(void*));
362 }
363
364 cs->old_ib_buffers[cs->num_old_ib_buffers++] = cs->ib_buffer;
365
366 cs->ib_buffer = cs->ws->base.buffer_create(&cs->ws->base, ib_size, 0,
367 RADEON_DOMAIN_GTT,
368 RADEON_FLAG_CPU_ACCESS |
369 RADEON_FLAG_NO_INTERPROCESS_SHARING |
370 RADEON_FLAG_READ_ONLY);
371
372 if (!cs->ib_buffer) {
373 cs->base.cdw = 0;
374 cs->failed = true;
375 cs->ib_buffer = cs->old_ib_buffers[--cs->num_old_ib_buffers];
376 }
377
378 cs->ib_mapped = cs->ws->base.buffer_map(cs->ib_buffer);
379 if (!cs->ib_mapped) {
380 cs->ws->base.buffer_destroy(cs->ib_buffer);
381 cs->base.cdw = 0;
382 cs->failed = true;
383 cs->ib_buffer = cs->old_ib_buffers[--cs->num_old_ib_buffers];
384 }
385
386 cs->ws->base.cs_add_buffer(&cs->base, cs->ib_buffer);
387
388 radeon_emit(&cs->base, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
389 radeon_emit(&cs->base, radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va);
390 radeon_emit(&cs->base, radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va >> 32);
391 radeon_emit(&cs->base, S_3F2_CHAIN(1) | S_3F2_VALID(1));
392
393 cs->ib_size_ptr = cs->base.buf + cs->base.cdw - 1;
394
395 cs->base.buf = (uint32_t *)cs->ib_mapped;
396 cs->base.cdw = 0;
397 cs->base.max_dw = ib_size / 4 - 4;
398
399 }
400
401 static bool radv_amdgpu_cs_finalize(struct radeon_cmdbuf *_cs)
402 {
403 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
404
405 if (cs->ws->use_ib_bos) {
406 while (!cs->base.cdw || (cs->base.cdw & 7) != 0)
407 radeon_emit(&cs->base, 0xffff1000);
408
409 *cs->ib_size_ptr |= cs->base.cdw;
410
411 cs->is_chained = false;
412 }
413
414 return !cs->failed;
415 }
416
417 static void radv_amdgpu_cs_reset(struct radeon_cmdbuf *_cs)
418 {
419 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
420 cs->base.cdw = 0;
421 cs->failed = false;
422
423 for (unsigned i = 0; i < cs->num_buffers; ++i) {
424 unsigned hash = ((uintptr_t)cs->handles[i] >> 6) &
425 (ARRAY_SIZE(cs->buffer_hash_table) - 1);
426 cs->buffer_hash_table[hash] = -1;
427 }
428
429 for (unsigned i = 0; i < cs->num_virtual_buffers; ++i) {
430 unsigned hash = ((uintptr_t)cs->virtual_buffers[i] >> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE - 1);
431 cs->virtual_buffer_hash_table[hash] = -1;
432 }
433
434 cs->num_buffers = 0;
435 cs->num_virtual_buffers = 0;
436
437 if (cs->ws->use_ib_bos) {
438 cs->ws->base.cs_add_buffer(&cs->base, cs->ib_buffer);
439
440 for (unsigned i = 0; i < cs->num_old_ib_buffers; ++i)
441 cs->ws->base.buffer_destroy(cs->old_ib_buffers[i]);
442
443 cs->num_old_ib_buffers = 0;
444 cs->ib.ib_mc_address = radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va;
445 cs->ib_size_ptr = &cs->ib.size;
446 cs->ib.size = 0;
447 } else {
448 for (unsigned i = 0; i < cs->num_old_cs_buffers; ++i) {
449 struct radeon_cmdbuf *rcs = &cs->old_cs_buffers[i];
450 free(rcs->buf);
451 }
452
453 free(cs->old_cs_buffers);
454 cs->old_cs_buffers = NULL;
455 cs->num_old_cs_buffers = 0;
456 }
457 }
458
459 static int radv_amdgpu_cs_find_buffer(struct radv_amdgpu_cs *cs,
460 amdgpu_bo_handle bo)
461 {
462 unsigned hash = ((uintptr_t)bo >> 6) & (ARRAY_SIZE(cs->buffer_hash_table) - 1);
463 int index = cs->buffer_hash_table[hash];
464
465 if (index == -1)
466 return -1;
467
468 if (cs->handles[index] == bo)
469 return index;
470
471 for (unsigned i = 0; i < cs->num_buffers; ++i) {
472 if (cs->handles[i] == bo) {
473 cs->buffer_hash_table[hash] = i;
474 return i;
475 }
476 }
477
478 return -1;
479 }
480
481 static void radv_amdgpu_cs_add_buffer_internal(struct radv_amdgpu_cs *cs,
482 amdgpu_bo_handle bo)
483 {
484 unsigned hash;
485 int index = radv_amdgpu_cs_find_buffer(cs, bo);
486
487 if (index != -1)
488 return;
489
490 if (cs->num_buffers == cs->max_num_buffers) {
491 unsigned new_count = MAX2(1, cs->max_num_buffers * 2);
492 cs->handles = realloc(cs->handles, new_count * sizeof(amdgpu_bo_handle));
493 cs->max_num_buffers = new_count;
494 }
495
496 cs->handles[cs->num_buffers] = bo;
497
498 hash = ((uintptr_t)bo >> 6) & (ARRAY_SIZE(cs->buffer_hash_table) - 1);
499 cs->buffer_hash_table[hash] = cs->num_buffers;
500
501 ++cs->num_buffers;
502 }
503
504 static void radv_amdgpu_cs_add_virtual_buffer(struct radeon_cmdbuf *_cs,
505 struct radeon_winsys_bo *bo)
506 {
507 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
508 unsigned hash = ((uintptr_t)bo >> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE - 1);
509
510
511 if (!cs->virtual_buffer_hash_table) {
512 cs->virtual_buffer_hash_table = malloc(VIRTUAL_BUFFER_HASH_TABLE_SIZE * sizeof(int));
513 for (int i = 0; i < VIRTUAL_BUFFER_HASH_TABLE_SIZE; ++i)
514 cs->virtual_buffer_hash_table[i] = -1;
515 }
516
517 if (cs->virtual_buffer_hash_table[hash] >= 0) {
518 int idx = cs->virtual_buffer_hash_table[hash];
519 if (cs->virtual_buffers[idx] == bo) {
520 return;
521 }
522 for (unsigned i = 0; i < cs->num_virtual_buffers; ++i) {
523 if (cs->virtual_buffers[i] == bo) {
524 cs->virtual_buffer_hash_table[hash] = i;
525 return;
526 }
527 }
528 }
529
530 if(cs->max_num_virtual_buffers <= cs->num_virtual_buffers) {
531 cs->max_num_virtual_buffers = MAX2(2, cs->max_num_virtual_buffers * 2);
532 cs->virtual_buffers = realloc(cs->virtual_buffers, sizeof(struct radv_amdgpu_virtual_virtual_buffer*) * cs->max_num_virtual_buffers);
533 }
534
535 cs->virtual_buffers[cs->num_virtual_buffers] = bo;
536
537 cs->virtual_buffer_hash_table[hash] = cs->num_virtual_buffers;
538 ++cs->num_virtual_buffers;
539
540 }
541
542 static void radv_amdgpu_cs_add_buffer(struct radeon_cmdbuf *_cs,
543 struct radeon_winsys_bo *_bo)
544 {
545 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
546 struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(_bo);
547
548 if (bo->is_virtual) {
549 radv_amdgpu_cs_add_virtual_buffer(_cs, _bo);
550 return;
551 }
552
553 if (bo->base.is_local)
554 return;
555
556 radv_amdgpu_cs_add_buffer_internal(cs, bo->bo);
557 }
558
559 static void radv_amdgpu_cs_execute_secondary(struct radeon_cmdbuf *_parent,
560 struct radeon_cmdbuf *_child)
561 {
562 struct radv_amdgpu_cs *parent = radv_amdgpu_cs(_parent);
563 struct radv_amdgpu_cs *child = radv_amdgpu_cs(_child);
564
565 for (unsigned i = 0; i < child->num_buffers; ++i) {
566 radv_amdgpu_cs_add_buffer_internal(parent, child->handles[i]);
567 }
568
569 for (unsigned i = 0; i < child->num_virtual_buffers; ++i) {
570 radv_amdgpu_cs_add_buffer(&parent->base, child->virtual_buffers[i]);
571 }
572
573 if (parent->ws->use_ib_bos) {
574 if (parent->base.cdw + 4 > parent->base.max_dw)
575 radv_amdgpu_cs_grow(&parent->base, 4);
576
577 radeon_emit(&parent->base, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
578 radeon_emit(&parent->base, child->ib.ib_mc_address);
579 radeon_emit(&parent->base, child->ib.ib_mc_address >> 32);
580 radeon_emit(&parent->base, child->ib.size);
581 } else {
582 if (parent->base.cdw + child->base.cdw > parent->base.max_dw)
583 radv_amdgpu_cs_grow(&parent->base, child->base.cdw);
584
585 memcpy(parent->base.buf + parent->base.cdw, child->base.buf, 4 * child->base.cdw);
586 parent->base.cdw += child->base.cdw;
587 }
588 }
589
590 static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws,
591 struct radeon_cmdbuf **cs_array,
592 unsigned count,
593 struct radv_amdgpu_winsys_bo **extra_bo_array,
594 unsigned num_extra_bo,
595 struct radeon_cmdbuf *extra_cs,
596 const struct radv_winsys_bo_list *radv_bo_list,
597 amdgpu_bo_list_handle *bo_list)
598 {
599 int r = 0;
600
601 if (ws->debug_all_bos) {
602 struct radv_amdgpu_winsys_bo *bo;
603 amdgpu_bo_handle *handles;
604 unsigned num = 0;
605
606 pthread_mutex_lock(&ws->global_bo_list_lock);
607
608 handles = malloc(sizeof(handles[0]) * ws->num_buffers);
609 if (!handles) {
610 pthread_mutex_unlock(&ws->global_bo_list_lock);
611 return -ENOMEM;
612 }
613
614 LIST_FOR_EACH_ENTRY(bo, &ws->global_bo_list, global_list_item) {
615 assert(num < ws->num_buffers);
616 handles[num++] = bo->bo;
617 }
618
619 r = amdgpu_bo_list_create(ws->dev, ws->num_buffers,
620 handles, NULL,
621 bo_list);
622 free(handles);
623 pthread_mutex_unlock(&ws->global_bo_list_lock);
624 } else if (count == 1 && !num_extra_bo && !extra_cs && !radv_bo_list &&
625 !radv_amdgpu_cs(cs_array[0])->num_virtual_buffers) {
626 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs*)cs_array[0];
627 if (cs->num_buffers == 0) {
628 *bo_list = 0;
629 return 0;
630 }
631 r = amdgpu_bo_list_create(ws->dev, cs->num_buffers, cs->handles,
632 NULL, bo_list);
633 } else {
634 unsigned total_buffer_count = num_extra_bo;
635 unsigned unique_bo_count = num_extra_bo;
636 for (unsigned i = 0; i < count; ++i) {
637 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs*)cs_array[i];
638 total_buffer_count += cs->num_buffers;
639 for (unsigned j = 0; j < cs->num_virtual_buffers; ++j)
640 total_buffer_count += radv_amdgpu_winsys_bo(cs->virtual_buffers[j])->bo_count;
641 }
642
643 if (extra_cs) {
644 total_buffer_count += ((struct radv_amdgpu_cs*)extra_cs)->num_buffers;
645 }
646
647 if (radv_bo_list) {
648 total_buffer_count += radv_bo_list->count;
649 }
650
651 if (total_buffer_count == 0) {
652 *bo_list = 0;
653 return 0;
654 }
655 amdgpu_bo_handle *handles = malloc(sizeof(amdgpu_bo_handle) * total_buffer_count);
656 if (!handles) {
657 free(handles);
658 return -ENOMEM;
659 }
660
661 for (unsigned i = 0; i < num_extra_bo; i++) {
662 handles[i] = extra_bo_array[i]->bo;
663 }
664
665 for (unsigned i = 0; i < count + !!extra_cs; ++i) {
666 struct radv_amdgpu_cs *cs;
667
668 if (i == count)
669 cs = (struct radv_amdgpu_cs*)extra_cs;
670 else
671 cs = (struct radv_amdgpu_cs*)cs_array[i];
672
673 if (!cs->num_buffers)
674 continue;
675
676 if (unique_bo_count == 0) {
677 memcpy(handles, cs->handles, cs->num_buffers * sizeof(amdgpu_bo_handle));
678 unique_bo_count = cs->num_buffers;
679 continue;
680 }
681 int unique_bo_so_far = unique_bo_count;
682 for (unsigned j = 0; j < cs->num_buffers; ++j) {
683 bool found = false;
684 for (unsigned k = 0; k < unique_bo_so_far; ++k) {
685 if (handles[k] == cs->handles[j]) {
686 found = true;
687 break;
688 }
689 }
690 if (!found) {
691 handles[unique_bo_count] = cs->handles[j];
692 ++unique_bo_count;
693 }
694 }
695 for (unsigned j = 0; j < cs->num_virtual_buffers; ++j) {
696 struct radv_amdgpu_winsys_bo *virtual_bo = radv_amdgpu_winsys_bo(cs->virtual_buffers[j]);
697 for(unsigned k = 0; k < virtual_bo->bo_count; ++k) {
698 struct radv_amdgpu_winsys_bo *bo = virtual_bo->bos[k];
699 bool found = false;
700 for (unsigned m = 0; m < unique_bo_count; ++m) {
701 if (handles[m] == bo->bo) {
702 found = true;
703 break;
704 }
705 }
706 if (!found) {
707 handles[unique_bo_count] = bo->bo;
708 ++unique_bo_count;
709 }
710 }
711 }
712 }
713
714 if (radv_bo_list) {
715 unsigned unique_bo_so_far = unique_bo_count;
716 for (unsigned i = 0; i < radv_bo_list->count; ++i) {
717 struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(radv_bo_list->bos[i]);
718 bool found = false;
719 for (unsigned j = 0; j < unique_bo_so_far; ++j) {
720 if (bo->bo == handles[j]) {
721 found = true;
722 break;
723 }
724 }
725 if (!found) {
726 handles[unique_bo_count] = bo->bo;
727 ++unique_bo_count;
728 }
729 }
730 }
731
732 if (unique_bo_count > 0) {
733 r = amdgpu_bo_list_create(ws->dev, unique_bo_count, handles,
734 NULL, bo_list);
735 } else {
736 *bo_list = 0;
737 }
738
739 free(handles);
740 }
741
742 return r;
743 }
744
745 static struct amdgpu_cs_fence_info radv_set_cs_fence(struct radv_amdgpu_ctx *ctx, int ip_type, int ring)
746 {
747 struct amdgpu_cs_fence_info ret = {0};
748 if (ctx->fence_map) {
749 ret.handle = radv_amdgpu_winsys_bo(ctx->fence_bo)->bo;
750 ret.offset = (ip_type * MAX_RINGS_PER_TYPE + ring) * sizeof(uint64_t);
751 }
752 return ret;
753 }
754
755 static void radv_assign_last_submit(struct radv_amdgpu_ctx *ctx,
756 struct amdgpu_cs_request *request)
757 {
758 radv_amdgpu_request_to_fence(ctx,
759 &ctx->last_submission[request->ip_type][request->ring],
760 request);
761 }
762
763 static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx *_ctx,
764 int queue_idx,
765 struct radv_winsys_sem_info *sem_info,
766 const struct radv_winsys_bo_list *radv_bo_list,
767 struct radeon_cmdbuf **cs_array,
768 unsigned cs_count,
769 struct radeon_cmdbuf *initial_preamble_cs,
770 struct radeon_cmdbuf *continue_preamble_cs,
771 struct radeon_winsys_fence *_fence)
772 {
773 int r;
774 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
775 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
776 struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[0]);
777 amdgpu_bo_list_handle bo_list;
778 struct amdgpu_cs_request request = {0};
779 struct amdgpu_cs_ib_info ibs[2];
780
781 for (unsigned i = cs_count; i--;) {
782 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
783
784 if (cs->is_chained) {
785 *cs->ib_size_ptr -= 4;
786 cs->is_chained = false;
787 }
788
789 if (i + 1 < cs_count) {
790 struct radv_amdgpu_cs *next = radv_amdgpu_cs(cs_array[i + 1]);
791 assert(cs->base.cdw + 4 <= cs->base.max_dw);
792
793 cs->is_chained = true;
794 *cs->ib_size_ptr += 4;
795
796 cs->base.buf[cs->base.cdw + 0] = PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0);
797 cs->base.buf[cs->base.cdw + 1] = next->ib.ib_mc_address;
798 cs->base.buf[cs->base.cdw + 2] = next->ib.ib_mc_address >> 32;
799 cs->base.buf[cs->base.cdw + 3] = S_3F2_CHAIN(1) | S_3F2_VALID(1) | next->ib.size;
800 }
801 }
802
803 r = radv_amdgpu_create_bo_list(cs0->ws, cs_array, cs_count, NULL, 0, initial_preamble_cs,
804 radv_bo_list, &bo_list);
805 if (r) {
806 fprintf(stderr, "amdgpu: buffer list creation failed for the "
807 "chained submission(%d)\n", r);
808 return r;
809 }
810
811 request.ip_type = cs0->hw_ip;
812 request.ring = queue_idx;
813 request.number_of_ibs = 1;
814 request.ibs = &cs0->ib;
815 request.resources = bo_list;
816 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
817
818 if (initial_preamble_cs) {
819 request.ibs = ibs;
820 request.number_of_ibs = 2;
821 ibs[1] = cs0->ib;
822 ibs[0] = ((struct radv_amdgpu_cs*)initial_preamble_cs)->ib;
823 }
824
825 r = radv_amdgpu_cs_submit(ctx, &request, sem_info);
826 if (r) {
827 if (r == -ENOMEM)
828 fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
829 else
830 fprintf(stderr, "amdgpu: The CS has been rejected, "
831 "see dmesg for more information.\n");
832 }
833
834 if (bo_list)
835 amdgpu_bo_list_destroy(bo_list);
836
837 if (fence)
838 radv_amdgpu_request_to_fence(ctx, fence, &request);
839
840 radv_assign_last_submit(ctx, &request);
841
842 return r;
843 }
844
845 static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx *_ctx,
846 int queue_idx,
847 struct radv_winsys_sem_info *sem_info,
848 const struct radv_winsys_bo_list *radv_bo_list,
849 struct radeon_cmdbuf **cs_array,
850 unsigned cs_count,
851 struct radeon_cmdbuf *initial_preamble_cs,
852 struct radeon_cmdbuf *continue_preamble_cs,
853 struct radeon_winsys_fence *_fence)
854 {
855 int r;
856 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
857 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
858 amdgpu_bo_list_handle bo_list;
859 struct amdgpu_cs_request request;
860 bool emit_signal_sem = sem_info->cs_emit_signal;
861 assert(cs_count);
862
863 for (unsigned i = 0; i < cs_count;) {
864 struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[i]);
865 struct amdgpu_cs_ib_info ibs[AMDGPU_CS_MAX_IBS_PER_SUBMIT];
866 struct radeon_cmdbuf *preamble_cs = i ? continue_preamble_cs : initial_preamble_cs;
867 unsigned cnt = MIN2(AMDGPU_CS_MAX_IBS_PER_SUBMIT - !!preamble_cs,
868 cs_count - i);
869
870 memset(&request, 0, sizeof(request));
871
872 r = radv_amdgpu_create_bo_list(cs0->ws, &cs_array[i], cnt, NULL, 0,
873 preamble_cs, radv_bo_list, &bo_list);
874 if (r) {
875 fprintf(stderr, "amdgpu: buffer list creation failed "
876 "for the fallback submission (%d)\n", r);
877 return r;
878 }
879
880 request.ip_type = cs0->hw_ip;
881 request.ring = queue_idx;
882 request.resources = bo_list;
883 request.number_of_ibs = cnt + !!preamble_cs;
884 request.ibs = ibs;
885 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
886
887 if (preamble_cs) {
888 ibs[0] = radv_amdgpu_cs(preamble_cs)->ib;
889 }
890
891 for (unsigned j = 0; j < cnt; ++j) {
892 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i + j]);
893 ibs[j + !!preamble_cs] = cs->ib;
894
895 if (cs->is_chained) {
896 *cs->ib_size_ptr -= 4;
897 cs->is_chained = false;
898 }
899 }
900
901 sem_info->cs_emit_signal = (i == cs_count - cnt) ? emit_signal_sem : false;
902 r = radv_amdgpu_cs_submit(ctx, &request, sem_info);
903 if (r) {
904 if (r == -ENOMEM)
905 fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
906 else
907 fprintf(stderr, "amdgpu: The CS has been rejected, "
908 "see dmesg for more information.\n");
909 }
910
911 if (bo_list)
912 amdgpu_bo_list_destroy(bo_list);
913
914 if (r)
915 return r;
916
917 i += cnt;
918 }
919 if (fence)
920 radv_amdgpu_request_to_fence(ctx, fence, &request);
921
922 radv_assign_last_submit(ctx, &request);
923
924 return 0;
925 }
926
927 static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
928 int queue_idx,
929 struct radv_winsys_sem_info *sem_info,
930 const struct radv_winsys_bo_list *radv_bo_list,
931 struct radeon_cmdbuf **cs_array,
932 unsigned cs_count,
933 struct radeon_cmdbuf *initial_preamble_cs,
934 struct radeon_cmdbuf *continue_preamble_cs,
935 struct radeon_winsys_fence *_fence)
936 {
937 int r;
938 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
939 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
940 struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[0]);
941 struct radeon_winsys *ws = (struct radeon_winsys*)cs0->ws;
942 amdgpu_bo_list_handle bo_list;
943 struct amdgpu_cs_request request;
944 uint32_t pad_word = 0xffff1000U;
945 bool emit_signal_sem = sem_info->cs_emit_signal;
946
947 if (radv_amdgpu_winsys(ws)->info.chip_class == SI)
948 pad_word = 0x80000000;
949
950 assert(cs_count);
951
952 for (unsigned i = 0; i < cs_count;) {
953 struct amdgpu_cs_ib_info ibs[AMDGPU_CS_MAX_IBS_PER_SUBMIT] = {0};
954 unsigned number_of_ibs = 1;
955 struct radeon_winsys_bo *bos[AMDGPU_CS_MAX_IBS_PER_SUBMIT] = {0};
956 struct radeon_cmdbuf *preamble_cs = i ? continue_preamble_cs : initial_preamble_cs;
957 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
958 uint32_t *ptr;
959 unsigned cnt = 0;
960 unsigned size = 0;
961 unsigned pad_words = 0;
962
963 if (cs->num_old_cs_buffers > 0) {
964 /* Special path when the maximum size in dwords has
965 * been reached because we need to handle more than one
966 * IB per submit.
967 */
968 unsigned new_cs_count = cs->num_old_cs_buffers + 1;
969 struct radeon_cmdbuf *new_cs_array[AMDGPU_CS_MAX_IBS_PER_SUBMIT];
970 unsigned idx = 0;
971
972 for (unsigned j = 0; j < cs->num_old_cs_buffers; j++)
973 new_cs_array[idx++] = &cs->old_cs_buffers[j];
974 new_cs_array[idx++] = cs_array[i];
975
976 for (unsigned j = 0; j < new_cs_count; j++) {
977 struct radeon_cmdbuf *rcs = new_cs_array[j];
978 bool needs_preamble = preamble_cs && j == 0;
979 unsigned size = 0;
980
981 if (needs_preamble)
982 size += preamble_cs->cdw;
983 size += rcs->cdw;
984
985 assert(size < 0xffff8);
986
987 while (!size || (size & 7)) {
988 size++;
989 pad_words++;
990 }
991
992 bos[j] = ws->buffer_create(ws, 4 * size, 4096,
993 RADEON_DOMAIN_GTT,
994 RADEON_FLAG_CPU_ACCESS |
995 RADEON_FLAG_NO_INTERPROCESS_SHARING |
996 RADEON_FLAG_READ_ONLY);
997 ptr = ws->buffer_map(bos[j]);
998
999 if (needs_preamble) {
1000 memcpy(ptr, preamble_cs->buf, preamble_cs->cdw * 4);
1001 ptr += preamble_cs->cdw;
1002 }
1003
1004 memcpy(ptr, rcs->buf, 4 * rcs->cdw);
1005 ptr += rcs->cdw;
1006
1007 for (unsigned k = 0; k < pad_words; ++k)
1008 *ptr++ = pad_word;
1009
1010 ibs[j].size = size;
1011 ibs[j].ib_mc_address = radv_buffer_get_va(bos[j]);
1012 }
1013
1014 number_of_ibs = new_cs_count;
1015 cnt++;
1016 } else {
1017 if (preamble_cs)
1018 size += preamble_cs->cdw;
1019
1020 while (i + cnt < cs_count && 0xffff8 - size >= radv_amdgpu_cs(cs_array[i + cnt])->base.cdw) {
1021 size += radv_amdgpu_cs(cs_array[i + cnt])->base.cdw;
1022 ++cnt;
1023 }
1024
1025 while (!size || (size & 7)) {
1026 size++;
1027 pad_words++;
1028 }
1029 assert(cnt);
1030
1031 bos[0] = ws->buffer_create(ws, 4 * size, 4096,
1032 RADEON_DOMAIN_GTT,
1033 RADEON_FLAG_CPU_ACCESS |
1034 RADEON_FLAG_NO_INTERPROCESS_SHARING |
1035 RADEON_FLAG_READ_ONLY);
1036 ptr = ws->buffer_map(bos[0]);
1037
1038 if (preamble_cs) {
1039 memcpy(ptr, preamble_cs->buf, preamble_cs->cdw * 4);
1040 ptr += preamble_cs->cdw;
1041 }
1042
1043 for (unsigned j = 0; j < cnt; ++j) {
1044 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i + j]);
1045 memcpy(ptr, cs->base.buf, 4 * cs->base.cdw);
1046 ptr += cs->base.cdw;
1047
1048 }
1049
1050 for (unsigned j = 0; j < pad_words; ++j)
1051 *ptr++ = pad_word;
1052
1053 ibs[0].size = size;
1054 ibs[0].ib_mc_address = radv_buffer_get_va(bos[0]);
1055 }
1056
1057 r = radv_amdgpu_create_bo_list(cs0->ws, &cs_array[i], cnt,
1058 (struct radv_amdgpu_winsys_bo **)bos,
1059 number_of_ibs, preamble_cs,
1060 radv_bo_list, &bo_list);
1061 if (r) {
1062 fprintf(stderr, "amdgpu: buffer list creation failed "
1063 "for the sysmem submission (%d)\n", r);
1064 return r;
1065 }
1066
1067 memset(&request, 0, sizeof(request));
1068
1069 request.ip_type = cs0->hw_ip;
1070 request.ring = queue_idx;
1071 request.resources = bo_list;
1072 request.number_of_ibs = number_of_ibs;
1073 request.ibs = ibs;
1074 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
1075
1076 sem_info->cs_emit_signal = (i == cs_count - cnt) ? emit_signal_sem : false;
1077 r = radv_amdgpu_cs_submit(ctx, &request, sem_info);
1078 if (r) {
1079 if (r == -ENOMEM)
1080 fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
1081 else
1082 fprintf(stderr, "amdgpu: The CS has been rejected, "
1083 "see dmesg for more information.\n");
1084 }
1085
1086 if (bo_list)
1087 amdgpu_bo_list_destroy(bo_list);
1088
1089 for (unsigned j = 0; j < number_of_ibs; j++) {
1090 ws->buffer_destroy(bos[j]);
1091 if (r)
1092 return r;
1093 }
1094
1095 i += cnt;
1096 }
1097 if (fence)
1098 radv_amdgpu_request_to_fence(ctx, fence, &request);
1099
1100 radv_assign_last_submit(ctx, &request);
1101
1102 return 0;
1103 }
1104
1105 static int radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx,
1106 int queue_idx,
1107 struct radeon_cmdbuf **cs_array,
1108 unsigned cs_count,
1109 struct radeon_cmdbuf *initial_preamble_cs,
1110 struct radeon_cmdbuf *continue_preamble_cs,
1111 struct radv_winsys_sem_info *sem_info,
1112 const struct radv_winsys_bo_list *bo_list,
1113 bool can_patch,
1114 struct radeon_winsys_fence *_fence)
1115 {
1116 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[0]);
1117 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
1118 int ret;
1119
1120 assert(sem_info);
1121 if (!cs->ws->use_ib_bos) {
1122 ret = radv_amdgpu_winsys_cs_submit_sysmem(_ctx, queue_idx, sem_info, bo_list, cs_array,
1123 cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
1124 } else if (can_patch && cs_count > AMDGPU_CS_MAX_IBS_PER_SUBMIT && cs->ws->batchchain) {
1125 ret = radv_amdgpu_winsys_cs_submit_chained(_ctx, queue_idx, sem_info, bo_list, cs_array,
1126 cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
1127 } else {
1128 ret = radv_amdgpu_winsys_cs_submit_fallback(_ctx, queue_idx, sem_info, bo_list, cs_array,
1129 cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
1130 }
1131
1132 radv_amdgpu_signal_sems(ctx, cs->hw_ip, queue_idx, sem_info);
1133 return ret;
1134 }
1135
1136 static void *radv_amdgpu_winsys_get_cpu_addr(void *_cs, uint64_t addr)
1137 {
1138 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)_cs;
1139 void *ret = NULL;
1140
1141 if (!cs->ib_buffer)
1142 return NULL;
1143 for (unsigned i = 0; i <= cs->num_old_ib_buffers; ++i) {
1144 struct radv_amdgpu_winsys_bo *bo;
1145
1146 bo = (struct radv_amdgpu_winsys_bo*)
1147 (i == cs->num_old_ib_buffers ? cs->ib_buffer : cs->old_ib_buffers[i]);
1148 if (addr >= bo->base.va && addr - bo->base.va < bo->size) {
1149 if (amdgpu_bo_cpu_map(bo->bo, &ret) == 0)
1150 return (char *)ret + (addr - bo->base.va);
1151 }
1152 }
1153 if(cs->ws->debug_all_bos) {
1154 pthread_mutex_lock(&cs->ws->global_bo_list_lock);
1155 list_for_each_entry(struct radv_amdgpu_winsys_bo, bo,
1156 &cs->ws->global_bo_list, global_list_item) {
1157 if (addr >= bo->base.va && addr - bo->base.va < bo->size) {
1158 if (amdgpu_bo_cpu_map(bo->bo, &ret) == 0) {
1159 pthread_mutex_unlock(&cs->ws->global_bo_list_lock);
1160 return (char *)ret + (addr - bo->base.va);
1161 }
1162 }
1163 }
1164 pthread_mutex_unlock(&cs->ws->global_bo_list_lock);
1165 }
1166 return ret;
1167 }
1168
1169 static void radv_amdgpu_winsys_cs_dump(struct radeon_cmdbuf *_cs,
1170 FILE* file,
1171 const int *trace_ids, int trace_id_count)
1172 {
1173 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)_cs;
1174 void *ib = cs->base.buf;
1175 int num_dw = cs->base.cdw;
1176
1177 if (cs->ws->use_ib_bos) {
1178 ib = radv_amdgpu_winsys_get_cpu_addr(cs, cs->ib.ib_mc_address);
1179 num_dw = cs->ib.size;
1180 }
1181 assert(ib);
1182 ac_parse_ib(file, ib, num_dw, trace_ids, trace_id_count, "main IB",
1183 cs->ws->info.chip_class, radv_amdgpu_winsys_get_cpu_addr, cs);
1184 }
1185
1186 static uint32_t radv_to_amdgpu_priority(enum radeon_ctx_priority radv_priority)
1187 {
1188 switch (radv_priority) {
1189 case RADEON_CTX_PRIORITY_REALTIME:
1190 return AMDGPU_CTX_PRIORITY_VERY_HIGH;
1191 case RADEON_CTX_PRIORITY_HIGH:
1192 return AMDGPU_CTX_PRIORITY_HIGH;
1193 case RADEON_CTX_PRIORITY_MEDIUM:
1194 return AMDGPU_CTX_PRIORITY_NORMAL;
1195 case RADEON_CTX_PRIORITY_LOW:
1196 return AMDGPU_CTX_PRIORITY_LOW;
1197 default:
1198 unreachable("Invalid context priority");
1199 }
1200 }
1201
1202 static struct radeon_winsys_ctx *radv_amdgpu_ctx_create(struct radeon_winsys *_ws,
1203 enum radeon_ctx_priority priority)
1204 {
1205 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1206 struct radv_amdgpu_ctx *ctx = CALLOC_STRUCT(radv_amdgpu_ctx);
1207 uint32_t amdgpu_priority = radv_to_amdgpu_priority(priority);
1208 int r;
1209
1210 if (!ctx)
1211 return NULL;
1212
1213 r = amdgpu_cs_ctx_create2(ws->dev, amdgpu_priority, &ctx->ctx);
1214 if (r) {
1215 fprintf(stderr, "amdgpu: radv_amdgpu_cs_ctx_create2 failed. (%i)\n", r);
1216 goto error_create;
1217 }
1218 ctx->ws = ws;
1219
1220 assert(AMDGPU_HW_IP_NUM * MAX_RINGS_PER_TYPE * sizeof(uint64_t) <= 4096);
1221 ctx->fence_bo = ws->base.buffer_create(&ws->base, 4096, 8,
1222 RADEON_DOMAIN_GTT,
1223 RADEON_FLAG_CPU_ACCESS|
1224 RADEON_FLAG_NO_INTERPROCESS_SHARING);
1225 if (ctx->fence_bo)
1226 ctx->fence_map = (uint64_t*)ws->base.buffer_map(ctx->fence_bo);
1227 if (ctx->fence_map)
1228 memset(ctx->fence_map, 0, 4096);
1229 return (struct radeon_winsys_ctx *)ctx;
1230 error_create:
1231 FREE(ctx);
1232 return NULL;
1233 }
1234
1235 static void radv_amdgpu_ctx_destroy(struct radeon_winsys_ctx *rwctx)
1236 {
1237 struct radv_amdgpu_ctx *ctx = (struct radv_amdgpu_ctx *)rwctx;
1238 ctx->ws->base.buffer_destroy(ctx->fence_bo);
1239 amdgpu_cs_ctx_free(ctx->ctx);
1240 FREE(ctx);
1241 }
1242
1243 static bool radv_amdgpu_ctx_wait_idle(struct radeon_winsys_ctx *rwctx,
1244 enum ring_type ring_type, int ring_index)
1245 {
1246 struct radv_amdgpu_ctx *ctx = (struct radv_amdgpu_ctx *)rwctx;
1247 int ip_type = ring_to_hw_ip(ring_type);
1248
1249 if (ctx->last_submission[ip_type][ring_index].fence.fence) {
1250 uint32_t expired;
1251 int ret = amdgpu_cs_query_fence_status(&ctx->last_submission[ip_type][ring_index].fence,
1252 1000000000ull, 0, &expired);
1253
1254 if (ret || !expired)
1255 return false;
1256 }
1257
1258 return true;
1259 }
1260
1261 static struct radeon_winsys_sem *radv_amdgpu_create_sem(struct radeon_winsys *_ws)
1262 {
1263 struct amdgpu_cs_fence *sem = CALLOC_STRUCT(amdgpu_cs_fence);
1264 if (!sem)
1265 return NULL;
1266
1267 return (struct radeon_winsys_sem *)sem;
1268 }
1269
1270 static void radv_amdgpu_destroy_sem(struct radeon_winsys_sem *_sem)
1271 {
1272 struct amdgpu_cs_fence *sem = (struct amdgpu_cs_fence *)_sem;
1273 FREE(sem);
1274 }
1275
1276 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx *ctx,
1277 uint32_t ip_type,
1278 uint32_t ring,
1279 struct radv_winsys_sem_info *sem_info)
1280 {
1281 for (unsigned i = 0; i < sem_info->signal.sem_count; i++) {
1282 struct amdgpu_cs_fence *sem = (struct amdgpu_cs_fence *)(sem_info->signal.sem)[i];
1283
1284 if (sem->context)
1285 return -EINVAL;
1286
1287 *sem = ctx->last_submission[ip_type][ring].fence;
1288 }
1289 return 0;
1290 }
1291
1292 static struct drm_amdgpu_cs_chunk_sem *radv_amdgpu_cs_alloc_syncobj_chunk(struct radv_winsys_sem_counts *counts,
1293 struct drm_amdgpu_cs_chunk *chunk, int chunk_id)
1294 {
1295 struct drm_amdgpu_cs_chunk_sem *syncobj = malloc(sizeof(struct drm_amdgpu_cs_chunk_sem) * counts->syncobj_count);
1296 if (!syncobj)
1297 return NULL;
1298
1299 for (unsigned i = 0; i < counts->syncobj_count; i++) {
1300 struct drm_amdgpu_cs_chunk_sem *sem = &syncobj[i];
1301 sem->handle = counts->syncobj[i];
1302 }
1303
1304 chunk->chunk_id = chunk_id;
1305 chunk->length_dw = sizeof(struct drm_amdgpu_cs_chunk_sem) / 4 * counts->syncobj_count;
1306 chunk->chunk_data = (uint64_t)(uintptr_t)syncobj;
1307 return syncobj;
1308 }
1309
1310 static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx,
1311 struct amdgpu_cs_request *request,
1312 struct radv_winsys_sem_info *sem_info)
1313 {
1314 int r;
1315 int num_chunks;
1316 int size;
1317 bool user_fence;
1318 struct drm_amdgpu_cs_chunk *chunks;
1319 struct drm_amdgpu_cs_chunk_data *chunk_data;
1320 struct drm_amdgpu_cs_chunk_dep *sem_dependencies = NULL;
1321 struct drm_amdgpu_cs_chunk_sem *wait_syncobj = NULL, *signal_syncobj = NULL;
1322 int i;
1323 struct amdgpu_cs_fence *sem;
1324
1325 user_fence = (request->fence_info.handle != NULL);
1326 size = request->number_of_ibs + (user_fence ? 2 : 1) + 3;
1327
1328 chunks = alloca(sizeof(struct drm_amdgpu_cs_chunk) * size);
1329
1330 size = request->number_of_ibs + (user_fence ? 1 : 0);
1331
1332 chunk_data = alloca(sizeof(struct drm_amdgpu_cs_chunk_data) * size);
1333
1334 num_chunks = request->number_of_ibs;
1335 for (i = 0; i < request->number_of_ibs; i++) {
1336 struct amdgpu_cs_ib_info *ib;
1337 chunks[i].chunk_id = AMDGPU_CHUNK_ID_IB;
1338 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
1339 chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
1340
1341 ib = &request->ibs[i];
1342
1343 chunk_data[i].ib_data._pad = 0;
1344 chunk_data[i].ib_data.va_start = ib->ib_mc_address;
1345 chunk_data[i].ib_data.ib_bytes = ib->size * 4;
1346 chunk_data[i].ib_data.ip_type = request->ip_type;
1347 chunk_data[i].ib_data.ip_instance = request->ip_instance;
1348 chunk_data[i].ib_data.ring = request->ring;
1349 chunk_data[i].ib_data.flags = ib->flags;
1350 }
1351
1352 if (user_fence) {
1353 i = num_chunks++;
1354
1355 chunks[i].chunk_id = AMDGPU_CHUNK_ID_FENCE;
1356 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_fence) / 4;
1357 chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
1358
1359 amdgpu_cs_chunk_fence_info_to_data(&request->fence_info,
1360 &chunk_data[i]);
1361 }
1362
1363 if (sem_info->wait.syncobj_count && sem_info->cs_emit_wait) {
1364 wait_syncobj = radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info->wait,
1365 &chunks[num_chunks],
1366 AMDGPU_CHUNK_ID_SYNCOBJ_IN);
1367 if (!wait_syncobj) {
1368 r = -ENOMEM;
1369 goto error_out;
1370 }
1371 num_chunks++;
1372
1373 if (sem_info->wait.sem_count == 0)
1374 sem_info->cs_emit_wait = false;
1375
1376 }
1377
1378 if (sem_info->wait.sem_count && sem_info->cs_emit_wait) {
1379 sem_dependencies = malloc(sizeof(struct drm_amdgpu_cs_chunk_dep) * sem_info->wait.sem_count);
1380 if (!sem_dependencies) {
1381 r = -ENOMEM;
1382 goto error_out;
1383 }
1384 int sem_count = 0;
1385 for (unsigned j = 0; j < sem_info->wait.sem_count; j++) {
1386 sem = (struct amdgpu_cs_fence *)sem_info->wait.sem[j];
1387 if (!sem->context)
1388 continue;
1389 struct drm_amdgpu_cs_chunk_dep *dep = &sem_dependencies[sem_count++];
1390
1391 amdgpu_cs_chunk_fence_to_dep(sem, dep);
1392
1393 sem->context = NULL;
1394 }
1395 i = num_chunks++;
1396
1397 /* dependencies chunk */
1398 chunks[i].chunk_id = AMDGPU_CHUNK_ID_DEPENDENCIES;
1399 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_dep) / 4 * sem_count;
1400 chunks[i].chunk_data = (uint64_t)(uintptr_t)sem_dependencies;
1401
1402 sem_info->cs_emit_wait = false;
1403 }
1404
1405 if (sem_info->signal.syncobj_count && sem_info->cs_emit_signal) {
1406 signal_syncobj = radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info->signal,
1407 &chunks[num_chunks],
1408 AMDGPU_CHUNK_ID_SYNCOBJ_OUT);
1409 if (!signal_syncobj) {
1410 r = -ENOMEM;
1411 goto error_out;
1412 }
1413 num_chunks++;
1414 }
1415
1416 r = amdgpu_cs_submit_raw(ctx->ws->dev,
1417 ctx->ctx,
1418 request->resources,
1419 num_chunks,
1420 chunks,
1421 &request->seq_no);
1422 error_out:
1423 free(sem_dependencies);
1424 free(wait_syncobj);
1425 free(signal_syncobj);
1426 return r;
1427 }
1428
1429 static int radv_amdgpu_create_syncobj(struct radeon_winsys *_ws,
1430 uint32_t *handle)
1431 {
1432 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1433 return amdgpu_cs_create_syncobj(ws->dev, handle);
1434 }
1435
1436 static void radv_amdgpu_destroy_syncobj(struct radeon_winsys *_ws,
1437 uint32_t handle)
1438 {
1439 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1440 amdgpu_cs_destroy_syncobj(ws->dev, handle);
1441 }
1442
1443 static void radv_amdgpu_reset_syncobj(struct radeon_winsys *_ws,
1444 uint32_t handle)
1445 {
1446 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1447 amdgpu_cs_syncobj_reset(ws->dev, &handle, 1);
1448 }
1449
1450 static void radv_amdgpu_signal_syncobj(struct radeon_winsys *_ws,
1451 uint32_t handle)
1452 {
1453 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1454 amdgpu_cs_syncobj_signal(ws->dev, &handle, 1);
1455 }
1456
1457 static bool radv_amdgpu_wait_syncobj(struct radeon_winsys *_ws, const uint32_t *handles,
1458 uint32_t handle_count, bool wait_all, uint64_t timeout)
1459 {
1460 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1461 uint32_t tmp;
1462
1463 /* The timeouts are signed, while vulkan timeouts are unsigned. */
1464 timeout = MIN2(timeout, INT64_MAX);
1465
1466 int ret = amdgpu_cs_syncobj_wait(ws->dev, (uint32_t*)handles, handle_count, timeout,
1467 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT |
1468 (wait_all ? DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL : 0),
1469 &tmp);
1470 if (ret == 0) {
1471 return true;
1472 } else if (ret == -1 && errno == ETIME) {
1473 return false;
1474 } else {
1475 fprintf(stderr, "amdgpu: radv_amdgpu_wait_syncobj failed!\nerrno: %d\n", errno);
1476 return false;
1477 }
1478 }
1479
1480 static int radv_amdgpu_export_syncobj(struct radeon_winsys *_ws,
1481 uint32_t syncobj,
1482 int *fd)
1483 {
1484 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1485
1486 return amdgpu_cs_export_syncobj(ws->dev, syncobj, fd);
1487 }
1488
1489 static int radv_amdgpu_import_syncobj(struct radeon_winsys *_ws,
1490 int fd,
1491 uint32_t *syncobj)
1492 {
1493 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1494
1495 return amdgpu_cs_import_syncobj(ws->dev, fd, syncobj);
1496 }
1497
1498
1499 static int radv_amdgpu_export_syncobj_to_sync_file(struct radeon_winsys *_ws,
1500 uint32_t syncobj,
1501 int *fd)
1502 {
1503 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1504
1505 return amdgpu_cs_syncobj_export_sync_file(ws->dev, syncobj, fd);
1506 }
1507
1508 static int radv_amdgpu_import_syncobj_from_sync_file(struct radeon_winsys *_ws,
1509 uint32_t syncobj,
1510 int fd)
1511 {
1512 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1513
1514 return amdgpu_cs_syncobj_import_sync_file(ws->dev, syncobj, fd);
1515 }
1516
1517 void radv_amdgpu_cs_init_functions(struct radv_amdgpu_winsys *ws)
1518 {
1519 ws->base.ctx_create = radv_amdgpu_ctx_create;
1520 ws->base.ctx_destroy = radv_amdgpu_ctx_destroy;
1521 ws->base.ctx_wait_idle = radv_amdgpu_ctx_wait_idle;
1522 ws->base.cs_create = radv_amdgpu_cs_create;
1523 ws->base.cs_destroy = radv_amdgpu_cs_destroy;
1524 ws->base.cs_grow = radv_amdgpu_cs_grow;
1525 ws->base.cs_finalize = radv_amdgpu_cs_finalize;
1526 ws->base.cs_reset = radv_amdgpu_cs_reset;
1527 ws->base.cs_add_buffer = radv_amdgpu_cs_add_buffer;
1528 ws->base.cs_execute_secondary = radv_amdgpu_cs_execute_secondary;
1529 ws->base.cs_submit = radv_amdgpu_winsys_cs_submit;
1530 ws->base.cs_dump = radv_amdgpu_winsys_cs_dump;
1531 ws->base.create_fence = radv_amdgpu_create_fence;
1532 ws->base.destroy_fence = radv_amdgpu_destroy_fence;
1533 ws->base.create_sem = radv_amdgpu_create_sem;
1534 ws->base.destroy_sem = radv_amdgpu_destroy_sem;
1535 ws->base.create_syncobj = radv_amdgpu_create_syncobj;
1536 ws->base.destroy_syncobj = radv_amdgpu_destroy_syncobj;
1537 ws->base.reset_syncobj = radv_amdgpu_reset_syncobj;
1538 ws->base.signal_syncobj = radv_amdgpu_signal_syncobj;
1539 ws->base.wait_syncobj = radv_amdgpu_wait_syncobj;
1540 ws->base.export_syncobj = radv_amdgpu_export_syncobj;
1541 ws->base.import_syncobj = radv_amdgpu_import_syncobj;
1542 ws->base.export_syncobj_to_sync_file = radv_amdgpu_export_syncobj_to_sync_file;
1543 ws->base.import_syncobj_from_sync_file = radv_amdgpu_import_syncobj_from_sync_file;
1544 ws->base.fence_wait = radv_amdgpu_fence_wait;
1545 ws->base.fences_wait = radv_amdgpu_fences_wait;
1546 }