2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include <amdgpu_drm.h>
31 #include "amdgpu_id.h"
32 #include "radv_radeon_winsys.h"
33 #include "radv_amdgpu_cs.h"
34 #include "radv_amdgpu_bo.h"
39 VIRTUAL_BUFFER_HASH_TABLE_SIZE
= 1024
42 struct radv_amdgpu_cs
{
43 struct radeon_winsys_cs base
;
44 struct radv_amdgpu_winsys
*ws
;
46 struct amdgpu_cs_ib_info ib
;
48 struct radeon_winsys_bo
*ib_buffer
;
50 unsigned max_num_buffers
;
52 amdgpu_bo_handle
*handles
;
55 struct radeon_winsys_bo
**old_ib_buffers
;
56 unsigned num_old_ib_buffers
;
57 unsigned max_num_old_ib_buffers
;
58 unsigned *ib_size_ptr
;
62 int buffer_hash_table
[1024];
65 unsigned num_virtual_buffers
;
66 unsigned max_num_virtual_buffers
;
67 struct radeon_winsys_bo
**virtual_buffers
;
68 uint8_t *virtual_buffer_priorities
;
69 int *virtual_buffer_hash_table
;
72 static inline struct radv_amdgpu_cs
*
73 radv_amdgpu_cs(struct radeon_winsys_cs
*base
)
75 return (struct radv_amdgpu_cs
*)base
;
78 static int ring_to_hw_ip(enum ring_type ring
)
82 return AMDGPU_HW_IP_GFX
;
84 return AMDGPU_HW_IP_DMA
;
86 return AMDGPU_HW_IP_COMPUTE
;
88 unreachable("unsupported ring");
92 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx
*ctx
,
95 struct radv_winsys_sem_info
*sem_info
);
96 static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx
*ctx
,
97 struct amdgpu_cs_request
*request
,
98 struct radv_winsys_sem_info
*sem_info
);
100 static void radv_amdgpu_request_to_fence(struct radv_amdgpu_ctx
*ctx
,
101 struct radv_amdgpu_fence
*fence
,
102 struct amdgpu_cs_request
*req
)
104 fence
->fence
.context
= ctx
->ctx
;
105 fence
->fence
.ip_type
= req
->ip_type
;
106 fence
->fence
.ip_instance
= req
->ip_instance
;
107 fence
->fence
.ring
= req
->ring
;
108 fence
->fence
.fence
= req
->seq_no
;
109 fence
->user_ptr
= (volatile uint64_t*)(ctx
->fence_map
+ (req
->ip_type
* MAX_RINGS_PER_TYPE
+ req
->ring
) * sizeof(uint64_t));
112 static struct radeon_winsys_fence
*radv_amdgpu_create_fence()
114 struct radv_amdgpu_fence
*fence
= calloc(1, sizeof(struct radv_amdgpu_fence
));
115 return (struct radeon_winsys_fence
*)fence
;
118 static void radv_amdgpu_destroy_fence(struct radeon_winsys_fence
*_fence
)
120 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
124 static bool radv_amdgpu_fence_wait(struct radeon_winsys
*_ws
,
125 struct radeon_winsys_fence
*_fence
,
129 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
130 unsigned flags
= absolute
? AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE
: 0;
132 uint32_t expired
= 0;
134 if (fence
->user_ptr
) {
135 if (*fence
->user_ptr
>= fence
->fence
.fence
)
137 if (!absolute
&& !timeout
)
141 /* Now use the libdrm query. */
142 r
= amdgpu_cs_query_fence_status(&fence
->fence
,
148 fprintf(stderr
, "amdgpu: radv_amdgpu_cs_query_fence_status failed.\n");
158 static void radv_amdgpu_cs_destroy(struct radeon_winsys_cs
*rcs
)
160 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(rcs
);
163 cs
->ws
->base
.buffer_destroy(cs
->ib_buffer
);
167 for (unsigned i
= 0; i
< cs
->num_old_ib_buffers
; ++i
)
168 cs
->ws
->base
.buffer_destroy(cs
->old_ib_buffers
[i
]);
170 free(cs
->old_ib_buffers
);
171 free(cs
->virtual_buffers
);
172 free(cs
->virtual_buffer_priorities
);
173 free(cs
->virtual_buffer_hash_table
);
175 free(cs
->priorities
);
179 static boolean
radv_amdgpu_init_cs(struct radv_amdgpu_cs
*cs
,
180 enum ring_type ring_type
)
182 for (int i
= 0; i
< ARRAY_SIZE(cs
->buffer_hash_table
); ++i
)
183 cs
->buffer_hash_table
[i
] = -1;
185 cs
->hw_ip
= ring_to_hw_ip(ring_type
);
189 static struct radeon_winsys_cs
*
190 radv_amdgpu_cs_create(struct radeon_winsys
*ws
,
191 enum ring_type ring_type
)
193 struct radv_amdgpu_cs
*cs
;
194 uint32_t ib_size
= 20 * 1024 * 4;
195 cs
= calloc(1, sizeof(struct radv_amdgpu_cs
));
199 cs
->ws
= radv_amdgpu_winsys(ws
);
200 radv_amdgpu_init_cs(cs
, ring_type
);
202 if (cs
->ws
->use_ib_bos
) {
203 cs
->ib_buffer
= ws
->buffer_create(ws
, ib_size
, 0,
205 RADEON_FLAG_CPU_ACCESS
);
206 if (!cs
->ib_buffer
) {
211 cs
->ib_mapped
= ws
->buffer_map(cs
->ib_buffer
);
212 if (!cs
->ib_mapped
) {
213 ws
->buffer_destroy(cs
->ib_buffer
);
218 cs
->ib
.ib_mc_address
= radv_amdgpu_winsys_bo(cs
->ib_buffer
)->va
;
219 cs
->base
.buf
= (uint32_t *)cs
->ib_mapped
;
220 cs
->base
.max_dw
= ib_size
/ 4 - 4;
221 cs
->ib_size_ptr
= &cs
->ib
.size
;
224 ws
->cs_add_buffer(&cs
->base
, cs
->ib_buffer
, 8);
226 cs
->base
.buf
= malloc(16384);
227 cs
->base
.max_dw
= 4096;
237 static void radv_amdgpu_cs_grow(struct radeon_winsys_cs
*_cs
, size_t min_size
)
239 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(_cs
);
246 if (!cs
->ws
->use_ib_bos
) {
247 const uint64_t limit_dws
= 0xffff8;
248 uint64_t ib_dws
= MAX2(cs
->base
.cdw
+ min_size
,
249 MIN2(cs
->base
.max_dw
* 2, limit_dws
));
251 /* The total ib size cannot exceed limit_dws dwords. */
252 if (ib_dws
> limit_dws
)
259 uint32_t *new_buf
= realloc(cs
->base
.buf
, ib_dws
* 4);
261 cs
->base
.buf
= new_buf
;
262 cs
->base
.max_dw
= ib_dws
;
270 uint64_t ib_size
= MAX2(min_size
* 4 + 16, cs
->base
.max_dw
* 4 * 2);
272 /* max that fits in the chain size field. */
273 ib_size
= MIN2(ib_size
, 0xfffff);
275 while (!cs
->base
.cdw
|| (cs
->base
.cdw
& 7) != 4)
276 cs
->base
.buf
[cs
->base
.cdw
++] = 0xffff1000;
278 *cs
->ib_size_ptr
|= cs
->base
.cdw
+ 4;
280 if (cs
->num_old_ib_buffers
== cs
->max_num_old_ib_buffers
) {
281 cs
->max_num_old_ib_buffers
= MAX2(1, cs
->max_num_old_ib_buffers
* 2);
282 cs
->old_ib_buffers
= realloc(cs
->old_ib_buffers
,
283 cs
->max_num_old_ib_buffers
* sizeof(void*));
286 cs
->old_ib_buffers
[cs
->num_old_ib_buffers
++] = cs
->ib_buffer
;
288 cs
->ib_buffer
= cs
->ws
->base
.buffer_create(&cs
->ws
->base
, ib_size
, 0,
290 RADEON_FLAG_CPU_ACCESS
);
292 if (!cs
->ib_buffer
) {
295 cs
->ib_buffer
= cs
->old_ib_buffers
[--cs
->num_old_ib_buffers
];
298 cs
->ib_mapped
= cs
->ws
->base
.buffer_map(cs
->ib_buffer
);
299 if (!cs
->ib_mapped
) {
300 cs
->ws
->base
.buffer_destroy(cs
->ib_buffer
);
303 cs
->ib_buffer
= cs
->old_ib_buffers
[--cs
->num_old_ib_buffers
];
306 cs
->ws
->base
.cs_add_buffer(&cs
->base
, cs
->ib_buffer
, 8);
308 cs
->base
.buf
[cs
->base
.cdw
++] = PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0);
309 cs
->base
.buf
[cs
->base
.cdw
++] = radv_amdgpu_winsys_bo(cs
->ib_buffer
)->va
;
310 cs
->base
.buf
[cs
->base
.cdw
++] = radv_amdgpu_winsys_bo(cs
->ib_buffer
)->va
>> 32;
311 cs
->ib_size_ptr
= cs
->base
.buf
+ cs
->base
.cdw
;
312 cs
->base
.buf
[cs
->base
.cdw
++] = S_3F2_CHAIN(1) | S_3F2_VALID(1);
314 cs
->base
.buf
= (uint32_t *)cs
->ib_mapped
;
316 cs
->base
.max_dw
= ib_size
/ 4 - 4;
320 static bool radv_amdgpu_cs_finalize(struct radeon_winsys_cs
*_cs
)
322 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(_cs
);
324 if (cs
->ws
->use_ib_bos
) {
325 while (!cs
->base
.cdw
|| (cs
->base
.cdw
& 7) != 0)
326 cs
->base
.buf
[cs
->base
.cdw
++] = 0xffff1000;
328 *cs
->ib_size_ptr
|= cs
->base
.cdw
;
330 cs
->is_chained
= false;
336 static void radv_amdgpu_cs_reset(struct radeon_winsys_cs
*_cs
)
338 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(_cs
);
342 for (unsigned i
= 0; i
< cs
->num_buffers
; ++i
) {
343 unsigned hash
= ((uintptr_t)cs
->handles
[i
] >> 6) &
344 (ARRAY_SIZE(cs
->buffer_hash_table
) - 1);
345 cs
->buffer_hash_table
[hash
] = -1;
348 for (unsigned i
= 0; i
< cs
->num_virtual_buffers
; ++i
) {
349 unsigned hash
= ((uintptr_t)cs
->virtual_buffers
[i
] >> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE
- 1);
350 cs
->virtual_buffer_hash_table
[hash
] = -1;
354 cs
->num_virtual_buffers
= 0;
356 if (cs
->ws
->use_ib_bos
) {
357 cs
->ws
->base
.cs_add_buffer(&cs
->base
, cs
->ib_buffer
, 8);
359 for (unsigned i
= 0; i
< cs
->num_old_ib_buffers
; ++i
)
360 cs
->ws
->base
.buffer_destroy(cs
->old_ib_buffers
[i
]);
362 cs
->num_old_ib_buffers
= 0;
363 cs
->ib
.ib_mc_address
= radv_amdgpu_winsys_bo(cs
->ib_buffer
)->va
;
364 cs
->ib_size_ptr
= &cs
->ib
.size
;
369 static int radv_amdgpu_cs_find_buffer(struct radv_amdgpu_cs
*cs
,
372 unsigned hash
= ((uintptr_t)bo
>> 6) & (ARRAY_SIZE(cs
->buffer_hash_table
) - 1);
373 int index
= cs
->buffer_hash_table
[hash
];
378 if (cs
->handles
[index
] == bo
)
381 for (unsigned i
= 0; i
< cs
->num_buffers
; ++i
) {
382 if (cs
->handles
[i
] == bo
) {
383 cs
->buffer_hash_table
[hash
] = i
;
391 static void radv_amdgpu_cs_add_buffer_internal(struct radv_amdgpu_cs
*cs
,
396 int index
= radv_amdgpu_cs_find_buffer(cs
, bo
);
399 cs
->priorities
[index
] = MAX2(cs
->priorities
[index
], priority
);
403 if (cs
->num_buffers
== cs
->max_num_buffers
) {
404 unsigned new_count
= MAX2(1, cs
->max_num_buffers
* 2);
405 cs
->handles
= realloc(cs
->handles
, new_count
* sizeof(amdgpu_bo_handle
));
406 cs
->priorities
= realloc(cs
->priorities
, new_count
* sizeof(uint8_t));
407 cs
->max_num_buffers
= new_count
;
410 cs
->handles
[cs
->num_buffers
] = bo
;
411 cs
->priorities
[cs
->num_buffers
] = priority
;
413 hash
= ((uintptr_t)bo
>> 6) & (ARRAY_SIZE(cs
->buffer_hash_table
) - 1);
414 cs
->buffer_hash_table
[hash
] = cs
->num_buffers
;
419 static void radv_amdgpu_cs_add_virtual_buffer(struct radeon_winsys_cs
*_cs
,
420 struct radeon_winsys_bo
*bo
,
423 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(_cs
);
424 unsigned hash
= ((uintptr_t)bo
>> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE
- 1);
427 if (!cs
->virtual_buffer_hash_table
) {
428 cs
->virtual_buffer_hash_table
= malloc(VIRTUAL_BUFFER_HASH_TABLE_SIZE
* sizeof(int));
429 for (int i
= 0; i
< VIRTUAL_BUFFER_HASH_TABLE_SIZE
; ++i
)
430 cs
->virtual_buffer_hash_table
[i
] = -1;
433 if (cs
->virtual_buffer_hash_table
[hash
] >= 0) {
434 int idx
= cs
->virtual_buffer_hash_table
[hash
];
435 if (cs
->virtual_buffers
[idx
] == bo
) {
436 cs
->virtual_buffer_priorities
[idx
] = MAX2(cs
->virtual_buffer_priorities
[idx
], priority
);
439 for (unsigned i
= 0; i
< cs
->num_virtual_buffers
; ++i
) {
440 if (cs
->virtual_buffers
[i
] == bo
) {
441 cs
->virtual_buffer_priorities
[i
] = MAX2(cs
->virtual_buffer_priorities
[i
], priority
);
442 cs
->virtual_buffer_hash_table
[hash
] = i
;
448 if(cs
->max_num_virtual_buffers
<= cs
->num_virtual_buffers
) {
449 cs
->max_num_virtual_buffers
= MAX2(2, cs
->max_num_virtual_buffers
* 2);
450 cs
->virtual_buffers
= realloc(cs
->virtual_buffers
, sizeof(struct radv_amdgpu_virtual_virtual_buffer
*) * cs
->max_num_virtual_buffers
);
451 cs
->virtual_buffer_priorities
= realloc(cs
->virtual_buffer_priorities
, sizeof(uint8_t) * cs
->max_num_virtual_buffers
);
454 cs
->virtual_buffers
[cs
->num_virtual_buffers
] = bo
;
455 cs
->virtual_buffer_priorities
[cs
->num_virtual_buffers
] = priority
;
457 cs
->virtual_buffer_hash_table
[hash
] = cs
->num_virtual_buffers
;
458 ++cs
->num_virtual_buffers
;
462 static void radv_amdgpu_cs_add_buffer(struct radeon_winsys_cs
*_cs
,
463 struct radeon_winsys_bo
*_bo
,
466 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(_cs
);
467 struct radv_amdgpu_winsys_bo
*bo
= radv_amdgpu_winsys_bo(_bo
);
469 if (bo
->is_virtual
) {
470 radv_amdgpu_cs_add_virtual_buffer(_cs
, _bo
, priority
);
474 radv_amdgpu_cs_add_buffer_internal(cs
, bo
->bo
, priority
);
477 static void radv_amdgpu_cs_execute_secondary(struct radeon_winsys_cs
*_parent
,
478 struct radeon_winsys_cs
*_child
)
480 struct radv_amdgpu_cs
*parent
= radv_amdgpu_cs(_parent
);
481 struct radv_amdgpu_cs
*child
= radv_amdgpu_cs(_child
);
483 for (unsigned i
= 0; i
< child
->num_buffers
; ++i
) {
484 radv_amdgpu_cs_add_buffer_internal(parent
, child
->handles
[i
],
485 child
->priorities
[i
]);
488 for (unsigned i
= 0; i
< child
->num_virtual_buffers
; ++i
) {
489 radv_amdgpu_cs_add_buffer(&parent
->base
, child
->virtual_buffers
[i
],
490 child
->virtual_buffer_priorities
[i
]);
493 if (parent
->ws
->use_ib_bos
) {
494 if (parent
->base
.cdw
+ 4 > parent
->base
.max_dw
)
495 radv_amdgpu_cs_grow(&parent
->base
, 4);
497 parent
->base
.buf
[parent
->base
.cdw
++] = PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0);
498 parent
->base
.buf
[parent
->base
.cdw
++] = child
->ib
.ib_mc_address
;
499 parent
->base
.buf
[parent
->base
.cdw
++] = child
->ib
.ib_mc_address
>> 32;
500 parent
->base
.buf
[parent
->base
.cdw
++] = child
->ib
.size
;
502 if (parent
->base
.cdw
+ child
->base
.cdw
> parent
->base
.max_dw
)
503 radv_amdgpu_cs_grow(&parent
->base
, child
->base
.cdw
);
505 memcpy(parent
->base
.buf
+ parent
->base
.cdw
, child
->base
.buf
, 4 * child
->base
.cdw
);
506 parent
->base
.cdw
+= child
->base
.cdw
;
510 static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys
*ws
,
511 struct radeon_winsys_cs
**cs_array
,
513 struct radv_amdgpu_winsys_bo
*extra_bo
,
514 struct radeon_winsys_cs
*extra_cs
,
515 amdgpu_bo_list_handle
*bo_list
)
518 if (ws
->debug_all_bos
) {
519 struct radv_amdgpu_winsys_bo
*bo
;
520 amdgpu_bo_handle
*handles
;
523 pthread_mutex_lock(&ws
->global_bo_list_lock
);
525 handles
= malloc(sizeof(handles
[0]) * ws
->num_buffers
);
527 pthread_mutex_unlock(&ws
->global_bo_list_lock
);
531 LIST_FOR_EACH_ENTRY(bo
, &ws
->global_bo_list
, global_list_item
) {
532 assert(num
< ws
->num_buffers
);
533 handles
[num
++] = bo
->bo
;
536 r
= amdgpu_bo_list_create(ws
->dev
, ws
->num_buffers
,
540 pthread_mutex_unlock(&ws
->global_bo_list_lock
);
541 } else if (count
== 1 && !extra_bo
&& !extra_cs
&&
542 !radv_amdgpu_cs(cs_array
[0])->num_virtual_buffers
) {
543 struct radv_amdgpu_cs
*cs
= (struct radv_amdgpu_cs
*)cs_array
[0];
544 r
= amdgpu_bo_list_create(ws
->dev
, cs
->num_buffers
, cs
->handles
,
545 cs
->priorities
, bo_list
);
547 unsigned total_buffer_count
= !!extra_bo
;
548 unsigned unique_bo_count
= !!extra_bo
;
549 for (unsigned i
= 0; i
< count
; ++i
) {
550 struct radv_amdgpu_cs
*cs
= (struct radv_amdgpu_cs
*)cs_array
[i
];
551 total_buffer_count
+= cs
->num_buffers
;
552 for (unsigned j
= 0; j
< cs
->num_virtual_buffers
; ++j
)
553 total_buffer_count
+= radv_amdgpu_winsys_bo(cs
->virtual_buffers
[j
])->bo_count
;
557 total_buffer_count
+= ((struct radv_amdgpu_cs
*)extra_cs
)->num_buffers
;
560 amdgpu_bo_handle
*handles
= malloc(sizeof(amdgpu_bo_handle
) * total_buffer_count
);
561 uint8_t *priorities
= malloc(sizeof(uint8_t) * total_buffer_count
);
562 if (!handles
|| !priorities
) {
569 handles
[0] = extra_bo
->bo
;
573 for (unsigned i
= 0; i
< count
+ !!extra_cs
; ++i
) {
574 struct radv_amdgpu_cs
*cs
;
577 cs
= (struct radv_amdgpu_cs
*)extra_cs
;
579 cs
= (struct radv_amdgpu_cs
*)cs_array
[i
];
581 if (!cs
->num_buffers
)
584 if (unique_bo_count
== 0) {
585 memcpy(handles
, cs
->handles
, cs
->num_buffers
* sizeof(amdgpu_bo_handle
));
586 memcpy(priorities
, cs
->priorities
, cs
->num_buffers
* sizeof(uint8_t));
587 unique_bo_count
= cs
->num_buffers
;
590 int unique_bo_so_far
= unique_bo_count
;
591 for (unsigned j
= 0; j
< cs
->num_buffers
; ++j
) {
593 for (unsigned k
= 0; k
< unique_bo_so_far
; ++k
) {
594 if (handles
[k
] == cs
->handles
[j
]) {
596 priorities
[k
] = MAX2(priorities
[k
],
602 handles
[unique_bo_count
] = cs
->handles
[j
];
603 priorities
[unique_bo_count
] = cs
->priorities
[j
];
607 for (unsigned j
= 0; j
< cs
->num_virtual_buffers
; ++j
) {
608 struct radv_amdgpu_winsys_bo
*virtual_bo
= radv_amdgpu_winsys_bo(cs
->virtual_buffers
[j
]);
609 for(unsigned k
= 0; k
< virtual_bo
->bo_count
; ++k
) {
610 struct radv_amdgpu_winsys_bo
*bo
= virtual_bo
->bos
[k
];
612 for (unsigned m
= 0; m
< unique_bo_count
; ++m
) {
613 if (handles
[m
] == bo
->bo
) {
615 priorities
[m
] = MAX2(priorities
[m
],
616 cs
->virtual_buffer_priorities
[j
]);
621 handles
[unique_bo_count
] = bo
->bo
;
622 priorities
[unique_bo_count
] = cs
->virtual_buffer_priorities
[j
];
628 r
= amdgpu_bo_list_create(ws
->dev
, unique_bo_count
, handles
,
629 priorities
, bo_list
);
638 static struct amdgpu_cs_fence_info
radv_set_cs_fence(struct radv_amdgpu_ctx
*ctx
, int ip_type
, int ring
)
640 struct amdgpu_cs_fence_info ret
= {0};
641 if (ctx
->fence_map
) {
642 ret
.handle
= radv_amdgpu_winsys_bo(ctx
->fence_bo
)->bo
;
643 ret
.offset
= (ip_type
* MAX_RINGS_PER_TYPE
+ ring
) * sizeof(uint64_t);
648 static void radv_assign_last_submit(struct radv_amdgpu_ctx
*ctx
,
649 struct amdgpu_cs_request
*request
)
651 radv_amdgpu_request_to_fence(ctx
,
652 &ctx
->last_submission
[request
->ip_type
][request
->ring
],
656 static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx
*_ctx
,
658 struct radv_winsys_sem_info
*sem_info
,
659 struct radeon_winsys_cs
**cs_array
,
661 struct radeon_winsys_cs
*initial_preamble_cs
,
662 struct radeon_winsys_cs
*continue_preamble_cs
,
663 struct radeon_winsys_fence
*_fence
)
666 struct radv_amdgpu_ctx
*ctx
= radv_amdgpu_ctx(_ctx
);
667 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
668 struct radv_amdgpu_cs
*cs0
= radv_amdgpu_cs(cs_array
[0]);
669 amdgpu_bo_list_handle bo_list
;
670 struct amdgpu_cs_request request
= {0};
671 struct amdgpu_cs_ib_info ibs
[2];
673 for (unsigned i
= cs_count
; i
--;) {
674 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(cs_array
[i
]);
676 if (cs
->is_chained
) {
677 *cs
->ib_size_ptr
-= 4;
678 cs
->is_chained
= false;
681 if (i
+ 1 < cs_count
) {
682 struct radv_amdgpu_cs
*next
= radv_amdgpu_cs(cs_array
[i
+ 1]);
683 assert(cs
->base
.cdw
+ 4 <= cs
->base
.max_dw
);
685 cs
->is_chained
= true;
686 *cs
->ib_size_ptr
+= 4;
688 cs
->base
.buf
[cs
->base
.cdw
+ 0] = PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0);
689 cs
->base
.buf
[cs
->base
.cdw
+ 1] = next
->ib
.ib_mc_address
;
690 cs
->base
.buf
[cs
->base
.cdw
+ 2] = next
->ib
.ib_mc_address
>> 32;
691 cs
->base
.buf
[cs
->base
.cdw
+ 3] = S_3F2_CHAIN(1) | S_3F2_VALID(1) | next
->ib
.size
;
695 r
= radv_amdgpu_create_bo_list(cs0
->ws
, cs_array
, cs_count
, NULL
, initial_preamble_cs
, &bo_list
);
697 fprintf(stderr
, "amdgpu: Failed to created the BO list for submission\n");
701 request
.ip_type
= cs0
->hw_ip
;
702 request
.ring
= queue_idx
;
703 request
.number_of_ibs
= 1;
704 request
.ibs
= &cs0
->ib
;
705 request
.resources
= bo_list
;
706 request
.fence_info
= radv_set_cs_fence(ctx
, cs0
->hw_ip
, queue_idx
);
708 if (initial_preamble_cs
) {
710 request
.number_of_ibs
= 2;
712 ibs
[0] = ((struct radv_amdgpu_cs
*)initial_preamble_cs
)->ib
;
715 r
= radv_amdgpu_cs_submit(ctx
, &request
, sem_info
);
718 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
720 fprintf(stderr
, "amdgpu: The CS has been rejected, "
721 "see dmesg for more information.\n");
724 amdgpu_bo_list_destroy(bo_list
);
727 radv_amdgpu_request_to_fence(ctx
, fence
, &request
);
729 radv_assign_last_submit(ctx
, &request
);
734 static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx
*_ctx
,
736 struct radv_winsys_sem_info
*sem_info
,
737 struct radeon_winsys_cs
**cs_array
,
739 struct radeon_winsys_cs
*initial_preamble_cs
,
740 struct radeon_winsys_cs
*continue_preamble_cs
,
741 struct radeon_winsys_fence
*_fence
)
744 struct radv_amdgpu_ctx
*ctx
= radv_amdgpu_ctx(_ctx
);
745 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
746 amdgpu_bo_list_handle bo_list
;
747 struct amdgpu_cs_request request
;
748 bool emit_signal_sem
= sem_info
->cs_emit_signal
;
751 for (unsigned i
= 0; i
< cs_count
;) {
752 struct radv_amdgpu_cs
*cs0
= radv_amdgpu_cs(cs_array
[i
]);
753 struct amdgpu_cs_ib_info ibs
[AMDGPU_CS_MAX_IBS_PER_SUBMIT
];
754 struct radeon_winsys_cs
*preamble_cs
= i
? continue_preamble_cs
: initial_preamble_cs
;
755 unsigned cnt
= MIN2(AMDGPU_CS_MAX_IBS_PER_SUBMIT
- !!preamble_cs
,
758 memset(&request
, 0, sizeof(request
));
760 r
= radv_amdgpu_create_bo_list(cs0
->ws
, &cs_array
[i
], cnt
, NULL
,
761 preamble_cs
, &bo_list
);
763 fprintf(stderr
, "amdgpu: Failed to created the BO list for submission\n");
767 request
.ip_type
= cs0
->hw_ip
;
768 request
.ring
= queue_idx
;
769 request
.resources
= bo_list
;
770 request
.number_of_ibs
= cnt
+ !!preamble_cs
;
772 request
.fence_info
= radv_set_cs_fence(ctx
, cs0
->hw_ip
, queue_idx
);
775 ibs
[0] = radv_amdgpu_cs(preamble_cs
)->ib
;
778 for (unsigned j
= 0; j
< cnt
; ++j
) {
779 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(cs_array
[i
+ j
]);
780 ibs
[j
+ !!preamble_cs
] = cs
->ib
;
782 if (cs
->is_chained
) {
783 *cs
->ib_size_ptr
-= 4;
784 cs
->is_chained
= false;
788 sem_info
->cs_emit_signal
= (i
== cs_count
- cnt
) ? emit_signal_sem
: false;
789 r
= radv_amdgpu_cs_submit(ctx
, &request
, sem_info
);
792 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
794 fprintf(stderr
, "amdgpu: The CS has been rejected, "
795 "see dmesg for more information.\n");
798 amdgpu_bo_list_destroy(bo_list
);
806 radv_amdgpu_request_to_fence(ctx
, fence
, &request
);
808 radv_assign_last_submit(ctx
, &request
);
813 static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx
*_ctx
,
815 struct radv_winsys_sem_info
*sem_info
,
816 struct radeon_winsys_cs
**cs_array
,
818 struct radeon_winsys_cs
*initial_preamble_cs
,
819 struct radeon_winsys_cs
*continue_preamble_cs
,
820 struct radeon_winsys_fence
*_fence
)
823 struct radv_amdgpu_ctx
*ctx
= radv_amdgpu_ctx(_ctx
);
824 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
825 struct radv_amdgpu_cs
*cs0
= radv_amdgpu_cs(cs_array
[0]);
826 struct radeon_winsys
*ws
= (struct radeon_winsys
*)cs0
->ws
;
827 amdgpu_bo_list_handle bo_list
;
828 struct amdgpu_cs_request request
;
829 uint32_t pad_word
= 0xffff1000U
;
830 bool emit_signal_sem
= sem_info
->cs_emit_signal
;
832 if (radv_amdgpu_winsys(ws
)->info
.chip_class
== SI
)
833 pad_word
= 0x80000000;
837 for (unsigned i
= 0; i
< cs_count
;) {
838 struct amdgpu_cs_ib_info ib
= {0};
839 struct radeon_winsys_bo
*bo
= NULL
;
840 struct radeon_winsys_cs
*preamble_cs
= i
? continue_preamble_cs
: initial_preamble_cs
;
844 unsigned pad_words
= 0;
846 size
+= preamble_cs
->cdw
;
848 while (i
+ cnt
< cs_count
&& 0xffff8 - size
>= radv_amdgpu_cs(cs_array
[i
+ cnt
])->base
.cdw
) {
849 size
+= radv_amdgpu_cs(cs_array
[i
+ cnt
])->base
.cdw
;
853 while(!size
|| (size
& 7)) {
859 bo
= ws
->buffer_create(ws
, 4 * size
, 4096, RADEON_DOMAIN_GTT
, RADEON_FLAG_CPU_ACCESS
);
860 ptr
= ws
->buffer_map(bo
);
863 memcpy(ptr
, preamble_cs
->buf
, preamble_cs
->cdw
* 4);
864 ptr
+= preamble_cs
->cdw
;
867 for (unsigned j
= 0; j
< cnt
; ++j
) {
868 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(cs_array
[i
+ j
]);
869 memcpy(ptr
, cs
->base
.buf
, 4 * cs
->base
.cdw
);
874 for (unsigned j
= 0; j
< pad_words
; ++j
)
877 memset(&request
, 0, sizeof(request
));
880 r
= radv_amdgpu_create_bo_list(cs0
->ws
, &cs_array
[i
], cnt
,
881 (struct radv_amdgpu_winsys_bo
*)bo
,
882 preamble_cs
, &bo_list
);
884 fprintf(stderr
, "amdgpu: Failed to created the BO list for submission\n");
889 ib
.ib_mc_address
= ws
->buffer_get_va(bo
);
891 request
.ip_type
= cs0
->hw_ip
;
892 request
.ring
= queue_idx
;
893 request
.resources
= bo_list
;
894 request
.number_of_ibs
= 1;
896 request
.fence_info
= radv_set_cs_fence(ctx
, cs0
->hw_ip
, queue_idx
);
898 sem_info
->cs_emit_signal
= (i
== cs_count
- cnt
) ? emit_signal_sem
: false;
899 r
= radv_amdgpu_cs_submit(ctx
, &request
, sem_info
);
902 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
904 fprintf(stderr
, "amdgpu: The CS has been rejected, "
905 "see dmesg for more information.\n");
908 amdgpu_bo_list_destroy(bo_list
);
910 ws
->buffer_destroy(bo
);
917 radv_amdgpu_request_to_fence(ctx
, fence
, &request
);
919 radv_assign_last_submit(ctx
, &request
);
924 static int radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx
*_ctx
,
926 struct radeon_winsys_cs
**cs_array
,
928 struct radeon_winsys_cs
*initial_preamble_cs
,
929 struct radeon_winsys_cs
*continue_preamble_cs
,
930 struct radv_winsys_sem_info
*sem_info
,
932 struct radeon_winsys_fence
*_fence
)
934 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(cs_array
[0]);
935 struct radv_amdgpu_ctx
*ctx
= radv_amdgpu_ctx(_ctx
);
939 if (!cs
->ws
->use_ib_bos
) {
940 ret
= radv_amdgpu_winsys_cs_submit_sysmem(_ctx
, queue_idx
, sem_info
, cs_array
,
941 cs_count
, initial_preamble_cs
, continue_preamble_cs
, _fence
);
942 } else if (can_patch
&& cs_count
> AMDGPU_CS_MAX_IBS_PER_SUBMIT
&& cs
->ws
->batchchain
) {
943 ret
= radv_amdgpu_winsys_cs_submit_chained(_ctx
, queue_idx
, sem_info
, cs_array
,
944 cs_count
, initial_preamble_cs
, continue_preamble_cs
, _fence
);
946 ret
= radv_amdgpu_winsys_cs_submit_fallback(_ctx
, queue_idx
, sem_info
, cs_array
,
947 cs_count
, initial_preamble_cs
, continue_preamble_cs
, _fence
);
950 radv_amdgpu_signal_sems(ctx
, cs
->hw_ip
, queue_idx
, sem_info
);
955 static void *radv_amdgpu_winsys_get_cpu_addr(void *_cs
, uint64_t addr
)
957 struct radv_amdgpu_cs
*cs
= (struct radv_amdgpu_cs
*)_cs
;
962 for (unsigned i
= 0; i
<= cs
->num_old_ib_buffers
; ++i
) {
963 struct radv_amdgpu_winsys_bo
*bo
;
965 bo
= (struct radv_amdgpu_winsys_bo
*)
966 (i
== cs
->num_old_ib_buffers
? cs
->ib_buffer
: cs
->old_ib_buffers
[i
]);
967 if (addr
>= bo
->va
&& addr
- bo
->va
< bo
->size
) {
968 if (amdgpu_bo_cpu_map(bo
->bo
, &ret
) == 0)
969 return (char *)ret
+ (addr
- bo
->va
);
975 static void radv_amdgpu_winsys_cs_dump(struct radeon_winsys_cs
*_cs
,
979 struct radv_amdgpu_cs
*cs
= (struct radv_amdgpu_cs
*)_cs
;
980 void *ib
= cs
->base
.buf
;
981 int num_dw
= cs
->base
.cdw
;
983 if (cs
->ws
->use_ib_bos
) {
984 ib
= radv_amdgpu_winsys_get_cpu_addr(cs
, cs
->ib
.ib_mc_address
);
985 num_dw
= cs
->ib
.size
;
988 ac_parse_ib(file
, ib
, num_dw
, trace_id
, "main IB", cs
->ws
->info
.chip_class
,
989 radv_amdgpu_winsys_get_cpu_addr
, cs
);
992 static struct radeon_winsys_ctx
*radv_amdgpu_ctx_create(struct radeon_winsys
*_ws
)
994 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
995 struct radv_amdgpu_ctx
*ctx
= CALLOC_STRUCT(radv_amdgpu_ctx
);
1000 r
= amdgpu_cs_ctx_create(ws
->dev
, &ctx
->ctx
);
1002 fprintf(stderr
, "amdgpu: radv_amdgpu_cs_ctx_create failed. (%i)\n", r
);
1007 assert(AMDGPU_HW_IP_NUM
* MAX_RINGS_PER_TYPE
* sizeof(uint64_t) <= 4096);
1008 ctx
->fence_bo
= ws
->base
.buffer_create(&ws
->base
, 4096, 8,
1010 RADEON_FLAG_CPU_ACCESS
);
1012 ctx
->fence_map
= (uint64_t*)ws
->base
.buffer_map(ctx
->fence_bo
);
1014 memset(ctx
->fence_map
, 0, 4096);
1015 return (struct radeon_winsys_ctx
*)ctx
;
1021 static void radv_amdgpu_ctx_destroy(struct radeon_winsys_ctx
*rwctx
)
1023 struct radv_amdgpu_ctx
*ctx
= (struct radv_amdgpu_ctx
*)rwctx
;
1024 ctx
->ws
->base
.buffer_destroy(ctx
->fence_bo
);
1025 amdgpu_cs_ctx_free(ctx
->ctx
);
1029 static bool radv_amdgpu_ctx_wait_idle(struct radeon_winsys_ctx
*rwctx
,
1030 enum ring_type ring_type
, int ring_index
)
1032 struct radv_amdgpu_ctx
*ctx
= (struct radv_amdgpu_ctx
*)rwctx
;
1033 int ip_type
= ring_to_hw_ip(ring_type
);
1035 if (ctx
->last_submission
[ip_type
][ring_index
].fence
.fence
) {
1037 int ret
= amdgpu_cs_query_fence_status(&ctx
->last_submission
[ip_type
][ring_index
].fence
,
1038 1000000000ull, 0, &expired
);
1040 if (ret
|| !expired
)
1047 static struct radeon_winsys_sem
*radv_amdgpu_create_sem(struct radeon_winsys
*_ws
)
1049 struct amdgpu_cs_fence
*sem
= CALLOC_STRUCT(amdgpu_cs_fence
);
1053 return (struct radeon_winsys_sem
*)sem
;
1056 static void radv_amdgpu_destroy_sem(struct radeon_winsys_sem
*_sem
)
1058 struct amdgpu_cs_fence
*sem
= (struct amdgpu_cs_fence
*)_sem
;
1062 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx
*ctx
,
1065 struct radv_winsys_sem_info
*sem_info
)
1067 for (unsigned i
= 0; i
< sem_info
->signal
.sem_count
; i
++) {
1068 struct amdgpu_cs_fence
*sem
= (struct amdgpu_cs_fence
*)(sem_info
->signal
.sem
)[i
];
1073 *sem
= ctx
->last_submission
[ip_type
][ring
].fence
;
1078 static struct drm_amdgpu_cs_chunk_sem
*radv_amdgpu_cs_alloc_syncobj_chunk(struct radv_winsys_sem_counts
*counts
,
1079 struct drm_amdgpu_cs_chunk
*chunk
, int chunk_id
)
1081 struct drm_amdgpu_cs_chunk_sem
*syncobj
= malloc(sizeof(struct drm_amdgpu_cs_chunk_sem
) * counts
->syncobj_count
);
1085 for (unsigned i
= 0; i
< counts
->syncobj_count
; i
++) {
1086 struct drm_amdgpu_cs_chunk_sem
*sem
= &syncobj
[i
];
1087 sem
->handle
= counts
->syncobj
[i
];
1090 chunk
->chunk_id
= chunk_id
;
1091 chunk
->length_dw
= sizeof(struct drm_amdgpu_cs_chunk_sem
) / 4 * counts
->syncobj_count
;
1092 chunk
->chunk_data
= (uint64_t)(uintptr_t)syncobj
;
1096 static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx
*ctx
,
1097 struct amdgpu_cs_request
*request
,
1098 struct radv_winsys_sem_info
*sem_info
)
1104 struct drm_amdgpu_cs_chunk
*chunks
;
1105 struct drm_amdgpu_cs_chunk_data
*chunk_data
;
1106 struct drm_amdgpu_cs_chunk_dep
*sem_dependencies
= NULL
;
1107 struct drm_amdgpu_cs_chunk_sem
*wait_syncobj
= NULL
, *signal_syncobj
= NULL
;
1109 struct amdgpu_cs_fence
*sem
;
1111 user_fence
= (request
->fence_info
.handle
!= NULL
);
1112 size
= request
->number_of_ibs
+ (user_fence
? 2 : 1) + 3;
1114 chunks
= alloca(sizeof(struct drm_amdgpu_cs_chunk
) * size
);
1116 size
= request
->number_of_ibs
+ (user_fence
? 1 : 0);
1118 chunk_data
= alloca(sizeof(struct drm_amdgpu_cs_chunk_data
) * size
);
1120 num_chunks
= request
->number_of_ibs
;
1121 for (i
= 0; i
< request
->number_of_ibs
; i
++) {
1122 struct amdgpu_cs_ib_info
*ib
;
1123 chunks
[i
].chunk_id
= AMDGPU_CHUNK_ID_IB
;
1124 chunks
[i
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_ib
) / 4;
1125 chunks
[i
].chunk_data
= (uint64_t)(uintptr_t)&chunk_data
[i
];
1127 ib
= &request
->ibs
[i
];
1129 chunk_data
[i
].ib_data
._pad
= 0;
1130 chunk_data
[i
].ib_data
.va_start
= ib
->ib_mc_address
;
1131 chunk_data
[i
].ib_data
.ib_bytes
= ib
->size
* 4;
1132 chunk_data
[i
].ib_data
.ip_type
= request
->ip_type
;
1133 chunk_data
[i
].ib_data
.ip_instance
= request
->ip_instance
;
1134 chunk_data
[i
].ib_data
.ring
= request
->ring
;
1135 chunk_data
[i
].ib_data
.flags
= ib
->flags
;
1141 chunks
[i
].chunk_id
= AMDGPU_CHUNK_ID_FENCE
;
1142 chunks
[i
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_fence
) / 4;
1143 chunks
[i
].chunk_data
= (uint64_t)(uintptr_t)&chunk_data
[i
];
1145 amdgpu_cs_chunk_fence_info_to_data(&request
->fence_info
,
1149 if (sem_info
->wait
.syncobj_count
&& sem_info
->cs_emit_wait
) {
1150 wait_syncobj
= radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info
->wait
,
1151 &chunks
[num_chunks
],
1152 AMDGPU_CHUNK_ID_SYNCOBJ_IN
);
1153 if (!wait_syncobj
) {
1159 if (sem_info
->wait
.sem_count
== 0)
1160 sem_info
->cs_emit_wait
= false;
1164 if (sem_info
->wait
.sem_count
&& sem_info
->cs_emit_wait
) {
1165 sem_dependencies
= malloc(sizeof(struct drm_amdgpu_cs_chunk_dep
) * sem_info
->wait
.sem_count
);
1166 if (!sem_dependencies
) {
1171 for (unsigned j
= 0; j
< sem_info
->wait
.sem_count
; j
++) {
1172 sem
= (struct amdgpu_cs_fence
*)sem_info
->wait
.sem
[j
];
1175 struct drm_amdgpu_cs_chunk_dep
*dep
= &sem_dependencies
[sem_count
++];
1177 amdgpu_cs_chunk_fence_to_dep(sem
, dep
);
1179 sem
->context
= NULL
;
1183 /* dependencies chunk */
1184 chunks
[i
].chunk_id
= AMDGPU_CHUNK_ID_DEPENDENCIES
;
1185 chunks
[i
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_dep
) / 4 * sem_count
;
1186 chunks
[i
].chunk_data
= (uint64_t)(uintptr_t)sem_dependencies
;
1188 sem_info
->cs_emit_wait
= false;
1191 if (sem_info
->signal
.syncobj_count
&& sem_info
->cs_emit_signal
) {
1192 signal_syncobj
= radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info
->signal
,
1193 &chunks
[num_chunks
],
1194 AMDGPU_CHUNK_ID_SYNCOBJ_OUT
);
1195 if (!signal_syncobj
) {
1202 r
= amdgpu_cs_submit_raw(ctx
->ws
->dev
,
1209 free(sem_dependencies
);
1211 free(signal_syncobj
);
1215 static int radv_amdgpu_create_syncobj(struct radeon_winsys
*_ws
,
1218 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1219 return amdgpu_cs_create_syncobj(ws
->dev
, handle
);
1222 static void radv_amdgpu_destroy_syncobj(struct radeon_winsys
*_ws
,
1225 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1226 amdgpu_cs_destroy_syncobj(ws
->dev
, handle
);
1229 static int radv_amdgpu_export_syncobj(struct radeon_winsys
*_ws
,
1233 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1235 return amdgpu_cs_export_syncobj(ws
->dev
, syncobj
, fd
);
1238 static int radv_amdgpu_import_syncobj(struct radeon_winsys
*_ws
,
1242 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1244 return amdgpu_cs_import_syncobj(ws
->dev
, fd
, syncobj
);
1247 void radv_amdgpu_cs_init_functions(struct radv_amdgpu_winsys
*ws
)
1249 ws
->base
.ctx_create
= radv_amdgpu_ctx_create
;
1250 ws
->base
.ctx_destroy
= radv_amdgpu_ctx_destroy
;
1251 ws
->base
.ctx_wait_idle
= radv_amdgpu_ctx_wait_idle
;
1252 ws
->base
.cs_create
= radv_amdgpu_cs_create
;
1253 ws
->base
.cs_destroy
= radv_amdgpu_cs_destroy
;
1254 ws
->base
.cs_grow
= radv_amdgpu_cs_grow
;
1255 ws
->base
.cs_finalize
= radv_amdgpu_cs_finalize
;
1256 ws
->base
.cs_reset
= radv_amdgpu_cs_reset
;
1257 ws
->base
.cs_add_buffer
= radv_amdgpu_cs_add_buffer
;
1258 ws
->base
.cs_execute_secondary
= radv_amdgpu_cs_execute_secondary
;
1259 ws
->base
.cs_submit
= radv_amdgpu_winsys_cs_submit
;
1260 ws
->base
.cs_dump
= radv_amdgpu_winsys_cs_dump
;
1261 ws
->base
.create_fence
= radv_amdgpu_create_fence
;
1262 ws
->base
.destroy_fence
= radv_amdgpu_destroy_fence
;
1263 ws
->base
.create_sem
= radv_amdgpu_create_sem
;
1264 ws
->base
.destroy_sem
= radv_amdgpu_destroy_sem
;
1265 ws
->base
.create_syncobj
= radv_amdgpu_create_syncobj
;
1266 ws
->base
.destroy_syncobj
= radv_amdgpu_destroy_syncobj
;
1267 ws
->base
.export_syncobj
= radv_amdgpu_export_syncobj
;
1268 ws
->base
.import_syncobj
= radv_amdgpu_import_syncobj
;
1269 ws
->base
.fence_wait
= radv_amdgpu_fence_wait
;