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[mesa.git] / src / amd / vulkan / winsys / amdgpu / radv_amdgpu_cs.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <stdlib.h>
26 #include <amdgpu.h>
27 #include "drm-uapi/amdgpu_drm.h"
28 #include <assert.h>
29 #include <pthread.h>
30 #include <errno.h>
31
32 #include "util/u_memory.h"
33 #include "ac_debug.h"
34 #include "radv_radeon_winsys.h"
35 #include "radv_amdgpu_cs.h"
36 #include "radv_amdgpu_bo.h"
37 #include "sid.h"
38
39
40 enum {
41 VIRTUAL_BUFFER_HASH_TABLE_SIZE = 1024
42 };
43
44 struct radv_amdgpu_cs {
45 struct radeon_cmdbuf base;
46 struct radv_amdgpu_winsys *ws;
47
48 struct amdgpu_cs_ib_info ib;
49
50 struct radeon_winsys_bo *ib_buffer;
51 uint8_t *ib_mapped;
52 unsigned max_num_buffers;
53 unsigned num_buffers;
54 struct drm_amdgpu_bo_list_entry *handles;
55
56 struct radeon_winsys_bo **old_ib_buffers;
57 unsigned num_old_ib_buffers;
58 unsigned max_num_old_ib_buffers;
59 unsigned *ib_size_ptr;
60 bool failed;
61 bool is_chained;
62
63 int buffer_hash_table[1024];
64 unsigned hw_ip;
65
66 unsigned num_virtual_buffers;
67 unsigned max_num_virtual_buffers;
68 struct radeon_winsys_bo **virtual_buffers;
69 int *virtual_buffer_hash_table;
70
71 /* For chips that don't support chaining. */
72 struct radeon_cmdbuf *old_cs_buffers;
73 unsigned num_old_cs_buffers;
74 };
75
76 static inline struct radv_amdgpu_cs *
77 radv_amdgpu_cs(struct radeon_cmdbuf *base)
78 {
79 return (struct radv_amdgpu_cs*)base;
80 }
81
82 static int ring_to_hw_ip(enum ring_type ring)
83 {
84 switch (ring) {
85 case RING_GFX:
86 return AMDGPU_HW_IP_GFX;
87 case RING_DMA:
88 return AMDGPU_HW_IP_DMA;
89 case RING_COMPUTE:
90 return AMDGPU_HW_IP_COMPUTE;
91 default:
92 unreachable("unsupported ring");
93 }
94 }
95
96 struct radv_amdgpu_cs_request {
97 /** Specify flags with additional information */
98 uint64_t flags;
99
100 /** Specify HW IP block type to which to send the IB. */
101 unsigned ip_type;
102
103 /** IP instance index if there are several IPs of the same type. */
104 unsigned ip_instance;
105
106 /**
107 * Specify ring index of the IP. We could have several rings
108 * in the same IP. E.g. 0 for SDMA0 and 1 for SDMA1.
109 */
110 uint32_t ring;
111
112 /**
113 * List handle with resources used by this request. This is a raw
114 * bo list handle used by the kernel.
115 */
116 uint32_t resources;
117
118 /**
119 * Number of dependencies this Command submission needs to
120 * wait for before starting execution.
121 */
122 uint32_t number_of_dependencies;
123
124 /**
125 * Array of dependencies which need to be met before
126 * execution can start.
127 */
128 struct amdgpu_cs_fence *dependencies;
129
130 /** Number of IBs to submit in the field ibs. */
131 uint32_t number_of_ibs;
132
133 /**
134 * IBs to submit. Those IBs will be submit together as single entity
135 */
136 struct amdgpu_cs_ib_info *ibs;
137
138 /**
139 * The returned sequence number for the command submission
140 */
141 uint64_t seq_no;
142
143 /**
144 * The fence information
145 */
146 struct amdgpu_cs_fence_info fence_info;
147 };
148
149
150 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx *ctx,
151 uint32_t ip_type,
152 uint32_t ring,
153 struct radv_winsys_sem_info *sem_info);
154 static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx,
155 struct radv_amdgpu_cs_request *request,
156 struct radv_winsys_sem_info *sem_info);
157
158 static void radv_amdgpu_request_to_fence(struct radv_amdgpu_ctx *ctx,
159 struct radv_amdgpu_fence *fence,
160 struct radv_amdgpu_cs_request *req)
161 {
162 fence->fence.context = ctx->ctx;
163 fence->fence.ip_type = req->ip_type;
164 fence->fence.ip_instance = req->ip_instance;
165 fence->fence.ring = req->ring;
166 fence->fence.fence = req->seq_no;
167 fence->user_ptr = (volatile uint64_t*)(ctx->fence_map + (req->ip_type * MAX_RINGS_PER_TYPE + req->ring) * sizeof(uint64_t));
168 }
169
170 static struct radeon_winsys_fence *radv_amdgpu_create_fence()
171 {
172 struct radv_amdgpu_fence *fence = calloc(1, sizeof(struct radv_amdgpu_fence));
173 fence->fence.fence = UINT64_MAX;
174 return (struct radeon_winsys_fence*)fence;
175 }
176
177 static void radv_amdgpu_destroy_fence(struct radeon_winsys_fence *_fence)
178 {
179 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
180 free(fence);
181 }
182
183 static void radv_amdgpu_reset_fence(struct radeon_winsys_fence *_fence)
184 {
185 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
186 fence->fence.fence = UINT64_MAX;
187 }
188
189 static void radv_amdgpu_signal_fence(struct radeon_winsys_fence *_fence)
190 {
191 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
192 fence->fence.fence = 0;
193 }
194
195 static bool radv_amdgpu_is_fence_waitable(struct radeon_winsys_fence *_fence)
196 {
197 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
198 return fence->fence.fence < UINT64_MAX;
199 }
200
201 static bool radv_amdgpu_fence_wait(struct radeon_winsys *_ws,
202 struct radeon_winsys_fence *_fence,
203 bool absolute,
204 uint64_t timeout)
205 {
206 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
207 unsigned flags = absolute ? AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE : 0;
208 int r;
209 uint32_t expired = 0;
210
211 /* Special casing 0 and UINT64_MAX so that they work without user_ptr/fence.ctx */
212 if (fence->fence.fence == UINT64_MAX)
213 return false;
214
215 if (fence->fence.fence == 0)
216 return true;
217
218 if (fence->user_ptr) {
219 if (*fence->user_ptr >= fence->fence.fence)
220 return true;
221 if (!absolute && !timeout)
222 return false;
223 }
224
225 /* Now use the libdrm query. */
226 r = amdgpu_cs_query_fence_status(&fence->fence,
227 timeout,
228 flags,
229 &expired);
230
231 if (r) {
232 fprintf(stderr, "amdgpu: radv_amdgpu_cs_query_fence_status failed.\n");
233 return false;
234 }
235
236 if (expired)
237 return true;
238
239 return false;
240 }
241
242
243 static bool radv_amdgpu_fences_wait(struct radeon_winsys *_ws,
244 struct radeon_winsys_fence *const *_fences,
245 uint32_t fence_count,
246 bool wait_all,
247 uint64_t timeout)
248 {
249 struct amdgpu_cs_fence *fences = malloc(sizeof(struct amdgpu_cs_fence) * fence_count);
250 int r;
251 uint32_t expired = 0, first = 0;
252
253 if (!fences)
254 return false;
255
256 for (uint32_t i = 0; i < fence_count; ++i)
257 fences[i] = ((struct radv_amdgpu_fence *)_fences[i])->fence;
258
259 /* Now use the libdrm query. */
260 r = amdgpu_cs_wait_fences(fences, fence_count, wait_all,
261 timeout, &expired, &first);
262
263 free(fences);
264 if (r) {
265 fprintf(stderr, "amdgpu: amdgpu_cs_wait_fences failed.\n");
266 return false;
267 }
268
269 if (expired)
270 return true;
271
272 return false;
273 }
274
275 static void radv_amdgpu_cs_destroy(struct radeon_cmdbuf *rcs)
276 {
277 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(rcs);
278
279 if (cs->ib_buffer)
280 cs->ws->base.buffer_destroy(cs->ib_buffer);
281 else
282 free(cs->base.buf);
283
284 for (unsigned i = 0; i < cs->num_old_ib_buffers; ++i)
285 cs->ws->base.buffer_destroy(cs->old_ib_buffers[i]);
286
287 for (unsigned i = 0; i < cs->num_old_cs_buffers; ++i) {
288 struct radeon_cmdbuf *rcs = &cs->old_cs_buffers[i];
289 free(rcs->buf);
290 }
291
292 free(cs->old_cs_buffers);
293 free(cs->old_ib_buffers);
294 free(cs->virtual_buffers);
295 free(cs->virtual_buffer_hash_table);
296 free(cs->handles);
297 free(cs);
298 }
299
300 static void radv_amdgpu_init_cs(struct radv_amdgpu_cs *cs,
301 enum ring_type ring_type)
302 {
303 for (int i = 0; i < ARRAY_SIZE(cs->buffer_hash_table); ++i)
304 cs->buffer_hash_table[i] = -1;
305
306 cs->hw_ip = ring_to_hw_ip(ring_type);
307 }
308
309 static struct radeon_cmdbuf *
310 radv_amdgpu_cs_create(struct radeon_winsys *ws,
311 enum ring_type ring_type)
312 {
313 struct radv_amdgpu_cs *cs;
314 uint32_t ib_size = 20 * 1024 * 4;
315 cs = calloc(1, sizeof(struct radv_amdgpu_cs));
316 if (!cs)
317 return NULL;
318
319 cs->ws = radv_amdgpu_winsys(ws);
320 radv_amdgpu_init_cs(cs, ring_type);
321
322 if (cs->ws->use_ib_bos) {
323 cs->ib_buffer = ws->buffer_create(ws, ib_size, 0,
324 RADEON_DOMAIN_GTT,
325 RADEON_FLAG_CPU_ACCESS |
326 RADEON_FLAG_NO_INTERPROCESS_SHARING |
327 RADEON_FLAG_READ_ONLY,
328 RADV_BO_PRIORITY_CS);
329 if (!cs->ib_buffer) {
330 free(cs);
331 return NULL;
332 }
333
334 cs->ib_mapped = ws->buffer_map(cs->ib_buffer);
335 if (!cs->ib_mapped) {
336 ws->buffer_destroy(cs->ib_buffer);
337 free(cs);
338 return NULL;
339 }
340
341 cs->ib.ib_mc_address = radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va;
342 cs->base.buf = (uint32_t *)cs->ib_mapped;
343 cs->base.max_dw = ib_size / 4 - 4;
344 cs->ib_size_ptr = &cs->ib.size;
345 cs->ib.size = 0;
346
347 ws->cs_add_buffer(&cs->base, cs->ib_buffer);
348 } else {
349 cs->base.buf = malloc(16384);
350 cs->base.max_dw = 4096;
351 if (!cs->base.buf) {
352 free(cs);
353 return NULL;
354 }
355 }
356
357 return &cs->base;
358 }
359
360 static void radv_amdgpu_cs_grow(struct radeon_cmdbuf *_cs, size_t min_size)
361 {
362 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
363
364 if (cs->failed) {
365 cs->base.cdw = 0;
366 return;
367 }
368
369 if (!cs->ws->use_ib_bos) {
370 const uint64_t limit_dws = 0xffff8;
371 uint64_t ib_dws = MAX2(cs->base.cdw + min_size,
372 MIN2(cs->base.max_dw * 2, limit_dws));
373
374 /* The total ib size cannot exceed limit_dws dwords. */
375 if (ib_dws > limit_dws)
376 {
377 /* The maximum size in dwords has been reached,
378 * try to allocate a new one.
379 */
380 cs->old_cs_buffers =
381 realloc(cs->old_cs_buffers,
382 (cs->num_old_cs_buffers + 1) * sizeof(*cs->old_cs_buffers));
383 if (!cs->old_cs_buffers) {
384 cs->failed = true;
385 cs->base.cdw = 0;
386 return;
387 }
388
389 /* Store the current one for submitting it later. */
390 cs->old_cs_buffers[cs->num_old_cs_buffers].cdw = cs->base.cdw;
391 cs->old_cs_buffers[cs->num_old_cs_buffers].max_dw = cs->base.max_dw;
392 cs->old_cs_buffers[cs->num_old_cs_buffers].buf = cs->base.buf;
393 cs->num_old_cs_buffers++;
394
395 /* Reset the cs, it will be re-allocated below. */
396 cs->base.cdw = 0;
397 cs->base.buf = NULL;
398
399 /* Re-compute the number of dwords to allocate. */
400 ib_dws = MAX2(cs->base.cdw + min_size,
401 MIN2(cs->base.max_dw * 2, limit_dws));
402 if (ib_dws > limit_dws) {
403 fprintf(stderr, "amdgpu: Too high number of "
404 "dwords to allocate\n");
405 cs->failed = true;
406 return;
407 }
408 }
409
410 uint32_t *new_buf = realloc(cs->base.buf, ib_dws * 4);
411 if (new_buf) {
412 cs->base.buf = new_buf;
413 cs->base.max_dw = ib_dws;
414 } else {
415 cs->failed = true;
416 cs->base.cdw = 0;
417 }
418 return;
419 }
420
421 uint64_t ib_size = MAX2(min_size * 4 + 16, cs->base.max_dw * 4 * 2);
422
423 /* max that fits in the chain size field. */
424 ib_size = MIN2(ib_size, 0xfffff);
425
426 while (!cs->base.cdw || (cs->base.cdw & 7) != 4)
427 radeon_emit(&cs->base, 0xffff1000);
428
429 *cs->ib_size_ptr |= cs->base.cdw + 4;
430
431 if (cs->num_old_ib_buffers == cs->max_num_old_ib_buffers) {
432 cs->max_num_old_ib_buffers = MAX2(1, cs->max_num_old_ib_buffers * 2);
433 cs->old_ib_buffers = realloc(cs->old_ib_buffers,
434 cs->max_num_old_ib_buffers * sizeof(void*));
435 }
436
437 cs->old_ib_buffers[cs->num_old_ib_buffers++] = cs->ib_buffer;
438
439 cs->ib_buffer = cs->ws->base.buffer_create(&cs->ws->base, ib_size, 0,
440 RADEON_DOMAIN_GTT,
441 RADEON_FLAG_CPU_ACCESS |
442 RADEON_FLAG_NO_INTERPROCESS_SHARING |
443 RADEON_FLAG_READ_ONLY,
444 RADV_BO_PRIORITY_CS);
445
446 if (!cs->ib_buffer) {
447 cs->base.cdw = 0;
448 cs->failed = true;
449 cs->ib_buffer = cs->old_ib_buffers[--cs->num_old_ib_buffers];
450 }
451
452 cs->ib_mapped = cs->ws->base.buffer_map(cs->ib_buffer);
453 if (!cs->ib_mapped) {
454 cs->ws->base.buffer_destroy(cs->ib_buffer);
455 cs->base.cdw = 0;
456 cs->failed = true;
457 cs->ib_buffer = cs->old_ib_buffers[--cs->num_old_ib_buffers];
458 }
459
460 cs->ws->base.cs_add_buffer(&cs->base, cs->ib_buffer);
461
462 radeon_emit(&cs->base, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
463 radeon_emit(&cs->base, radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va);
464 radeon_emit(&cs->base, radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va >> 32);
465 radeon_emit(&cs->base, S_3F2_CHAIN(1) | S_3F2_VALID(1));
466
467 cs->ib_size_ptr = cs->base.buf + cs->base.cdw - 1;
468
469 cs->base.buf = (uint32_t *)cs->ib_mapped;
470 cs->base.cdw = 0;
471 cs->base.max_dw = ib_size / 4 - 4;
472
473 }
474
475 static bool radv_amdgpu_cs_finalize(struct radeon_cmdbuf *_cs)
476 {
477 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
478
479 if (cs->ws->use_ib_bos) {
480 while (!cs->base.cdw || (cs->base.cdw & 7) != 0)
481 radeon_emit(&cs->base, 0xffff1000);
482
483 *cs->ib_size_ptr |= cs->base.cdw;
484
485 cs->is_chained = false;
486 }
487
488 return !cs->failed;
489 }
490
491 static void radv_amdgpu_cs_reset(struct radeon_cmdbuf *_cs)
492 {
493 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
494 cs->base.cdw = 0;
495 cs->failed = false;
496
497 for (unsigned i = 0; i < cs->num_buffers; ++i) {
498 unsigned hash = cs->handles[i].bo_handle &
499 (ARRAY_SIZE(cs->buffer_hash_table) - 1);
500 cs->buffer_hash_table[hash] = -1;
501 }
502
503 for (unsigned i = 0; i < cs->num_virtual_buffers; ++i) {
504 unsigned hash = ((uintptr_t)cs->virtual_buffers[i] >> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE - 1);
505 cs->virtual_buffer_hash_table[hash] = -1;
506 }
507
508 cs->num_buffers = 0;
509 cs->num_virtual_buffers = 0;
510
511 if (cs->ws->use_ib_bos) {
512 cs->ws->base.cs_add_buffer(&cs->base, cs->ib_buffer);
513
514 for (unsigned i = 0; i < cs->num_old_ib_buffers; ++i)
515 cs->ws->base.buffer_destroy(cs->old_ib_buffers[i]);
516
517 cs->num_old_ib_buffers = 0;
518 cs->ib.ib_mc_address = radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va;
519 cs->ib_size_ptr = &cs->ib.size;
520 cs->ib.size = 0;
521 } else {
522 for (unsigned i = 0; i < cs->num_old_cs_buffers; ++i) {
523 struct radeon_cmdbuf *rcs = &cs->old_cs_buffers[i];
524 free(rcs->buf);
525 }
526
527 free(cs->old_cs_buffers);
528 cs->old_cs_buffers = NULL;
529 cs->num_old_cs_buffers = 0;
530 }
531 }
532
533 static int radv_amdgpu_cs_find_buffer(struct radv_amdgpu_cs *cs,
534 uint32_t bo)
535 {
536 unsigned hash = bo & (ARRAY_SIZE(cs->buffer_hash_table) - 1);
537 int index = cs->buffer_hash_table[hash];
538
539 if (index == -1)
540 return -1;
541
542 if (cs->handles[index].bo_handle == bo)
543 return index;
544
545 for (unsigned i = 0; i < cs->num_buffers; ++i) {
546 if (cs->handles[i].bo_handle == bo) {
547 cs->buffer_hash_table[hash] = i;
548 return i;
549 }
550 }
551
552 return -1;
553 }
554
555 static void radv_amdgpu_cs_add_buffer_internal(struct radv_amdgpu_cs *cs,
556 uint32_t bo, uint8_t priority)
557 {
558 unsigned hash;
559 int index = radv_amdgpu_cs_find_buffer(cs, bo);
560
561 if (index != -1)
562 return;
563
564 if (cs->num_buffers == cs->max_num_buffers) {
565 unsigned new_count = MAX2(1, cs->max_num_buffers * 2);
566 cs->handles = realloc(cs->handles, new_count * sizeof(struct drm_amdgpu_bo_list_entry));
567 cs->max_num_buffers = new_count;
568 }
569
570 cs->handles[cs->num_buffers].bo_handle = bo;
571 cs->handles[cs->num_buffers].bo_priority = priority;
572
573 hash = bo & (ARRAY_SIZE(cs->buffer_hash_table) - 1);
574 cs->buffer_hash_table[hash] = cs->num_buffers;
575
576 ++cs->num_buffers;
577 }
578
579 static void radv_amdgpu_cs_add_virtual_buffer(struct radeon_cmdbuf *_cs,
580 struct radeon_winsys_bo *bo)
581 {
582 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
583 unsigned hash = ((uintptr_t)bo >> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE - 1);
584
585
586 if (!cs->virtual_buffer_hash_table) {
587 cs->virtual_buffer_hash_table = malloc(VIRTUAL_BUFFER_HASH_TABLE_SIZE * sizeof(int));
588 for (int i = 0; i < VIRTUAL_BUFFER_HASH_TABLE_SIZE; ++i)
589 cs->virtual_buffer_hash_table[i] = -1;
590 }
591
592 if (cs->virtual_buffer_hash_table[hash] >= 0) {
593 int idx = cs->virtual_buffer_hash_table[hash];
594 if (cs->virtual_buffers[idx] == bo) {
595 return;
596 }
597 for (unsigned i = 0; i < cs->num_virtual_buffers; ++i) {
598 if (cs->virtual_buffers[i] == bo) {
599 cs->virtual_buffer_hash_table[hash] = i;
600 return;
601 }
602 }
603 }
604
605 if(cs->max_num_virtual_buffers <= cs->num_virtual_buffers) {
606 cs->max_num_virtual_buffers = MAX2(2, cs->max_num_virtual_buffers * 2);
607 cs->virtual_buffers = realloc(cs->virtual_buffers, sizeof(struct radv_amdgpu_virtual_virtual_buffer*) * cs->max_num_virtual_buffers);
608 }
609
610 cs->virtual_buffers[cs->num_virtual_buffers] = bo;
611
612 cs->virtual_buffer_hash_table[hash] = cs->num_virtual_buffers;
613 ++cs->num_virtual_buffers;
614
615 }
616
617 static void radv_amdgpu_cs_add_buffer(struct radeon_cmdbuf *_cs,
618 struct radeon_winsys_bo *_bo)
619 {
620 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
621 struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(_bo);
622
623 if (bo->is_virtual) {
624 radv_amdgpu_cs_add_virtual_buffer(_cs, _bo);
625 return;
626 }
627
628 if (bo->base.is_local)
629 return;
630
631 radv_amdgpu_cs_add_buffer_internal(cs, bo->bo_handle, bo->priority);
632 }
633
634 static void radv_amdgpu_cs_execute_secondary(struct radeon_cmdbuf *_parent,
635 struct radeon_cmdbuf *_child)
636 {
637 struct radv_amdgpu_cs *parent = radv_amdgpu_cs(_parent);
638 struct radv_amdgpu_cs *child = radv_amdgpu_cs(_child);
639
640 for (unsigned i = 0; i < child->num_buffers; ++i) {
641 radv_amdgpu_cs_add_buffer_internal(parent,
642 child->handles[i].bo_handle,
643 child->handles[i].bo_priority);
644 }
645
646 for (unsigned i = 0; i < child->num_virtual_buffers; ++i) {
647 radv_amdgpu_cs_add_buffer(&parent->base, child->virtual_buffers[i]);
648 }
649
650 if (parent->ws->use_ib_bos) {
651 if (parent->base.cdw + 4 > parent->base.max_dw)
652 radv_amdgpu_cs_grow(&parent->base, 4);
653
654 radeon_emit(&parent->base, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
655 radeon_emit(&parent->base, child->ib.ib_mc_address);
656 radeon_emit(&parent->base, child->ib.ib_mc_address >> 32);
657 radeon_emit(&parent->base, child->ib.size);
658 } else {
659 if (parent->base.cdw + child->base.cdw > parent->base.max_dw)
660 radv_amdgpu_cs_grow(&parent->base, child->base.cdw);
661
662 memcpy(parent->base.buf + parent->base.cdw, child->base.buf, 4 * child->base.cdw);
663 parent->base.cdw += child->base.cdw;
664 }
665 }
666
667 static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws,
668 struct radeon_cmdbuf **cs_array,
669 unsigned count,
670 struct radv_amdgpu_winsys_bo **extra_bo_array,
671 unsigned num_extra_bo,
672 struct radeon_cmdbuf *extra_cs,
673 const struct radv_winsys_bo_list *radv_bo_list,
674 uint32_t *bo_list)
675 {
676 int r = 0;
677
678 if (ws->debug_all_bos) {
679 struct radv_amdgpu_winsys_bo *bo;
680 struct drm_amdgpu_bo_list_entry *handles;
681 unsigned num = 0;
682
683 pthread_mutex_lock(&ws->global_bo_list_lock);
684
685 handles = malloc(sizeof(handles[0]) * ws->num_buffers);
686 if (!handles) {
687 pthread_mutex_unlock(&ws->global_bo_list_lock);
688 return -ENOMEM;
689 }
690
691 LIST_FOR_EACH_ENTRY(bo, &ws->global_bo_list, global_list_item) {
692 assert(num < ws->num_buffers);
693 handles[num].bo_handle = bo->bo_handle;
694 handles[num].bo_priority = bo->priority;
695 num++;
696 }
697
698 r = amdgpu_bo_list_create_raw(ws->dev, ws->num_buffers,
699 handles, bo_list);
700 free(handles);
701 pthread_mutex_unlock(&ws->global_bo_list_lock);
702 } else if (count == 1 && !num_extra_bo && !extra_cs && !radv_bo_list &&
703 !radv_amdgpu_cs(cs_array[0])->num_virtual_buffers) {
704 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs*)cs_array[0];
705 if (cs->num_buffers == 0) {
706 *bo_list = 0;
707 return 0;
708 }
709 r = amdgpu_bo_list_create_raw(ws->dev, cs->num_buffers, cs->handles,
710 bo_list);
711 } else {
712 unsigned total_buffer_count = num_extra_bo;
713 unsigned unique_bo_count = num_extra_bo;
714 for (unsigned i = 0; i < count; ++i) {
715 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs*)cs_array[i];
716 total_buffer_count += cs->num_buffers;
717 for (unsigned j = 0; j < cs->num_virtual_buffers; ++j)
718 total_buffer_count += radv_amdgpu_winsys_bo(cs->virtual_buffers[j])->bo_count;
719 }
720
721 if (extra_cs) {
722 total_buffer_count += ((struct radv_amdgpu_cs*)extra_cs)->num_buffers;
723 }
724
725 if (radv_bo_list) {
726 total_buffer_count += radv_bo_list->count;
727 }
728
729 if (total_buffer_count == 0) {
730 *bo_list = 0;
731 return 0;
732 }
733 struct drm_amdgpu_bo_list_entry *handles = malloc(sizeof(struct drm_amdgpu_bo_list_entry) * total_buffer_count);
734 if (!handles) {
735 free(handles);
736 return -ENOMEM;
737 }
738
739 for (unsigned i = 0; i < num_extra_bo; i++) {
740 handles[i].bo_handle = extra_bo_array[i]->bo_handle;
741 handles[i].bo_priority = extra_bo_array[i]->priority;
742 }
743
744 for (unsigned i = 0; i < count + !!extra_cs; ++i) {
745 struct radv_amdgpu_cs *cs;
746
747 if (i == count)
748 cs = (struct radv_amdgpu_cs*)extra_cs;
749 else
750 cs = (struct radv_amdgpu_cs*)cs_array[i];
751
752 if (!cs->num_buffers)
753 continue;
754
755 if (unique_bo_count == 0 && !cs->num_virtual_buffers) {
756 memcpy(handles, cs->handles, cs->num_buffers * sizeof(struct drm_amdgpu_bo_list_entry));
757 unique_bo_count = cs->num_buffers;
758 continue;
759 }
760 int unique_bo_so_far = unique_bo_count;
761 for (unsigned j = 0; j < cs->num_buffers; ++j) {
762 bool found = false;
763 for (unsigned k = 0; k < unique_bo_so_far; ++k) {
764 if (handles[k].bo_handle == cs->handles[j].bo_handle) {
765 found = true;
766 break;
767 }
768 }
769 if (!found) {
770 handles[unique_bo_count] = cs->handles[j];
771 ++unique_bo_count;
772 }
773 }
774 for (unsigned j = 0; j < cs->num_virtual_buffers; ++j) {
775 struct radv_amdgpu_winsys_bo *virtual_bo = radv_amdgpu_winsys_bo(cs->virtual_buffers[j]);
776 for(unsigned k = 0; k < virtual_bo->bo_count; ++k) {
777 struct radv_amdgpu_winsys_bo *bo = virtual_bo->bos[k];
778 bool found = false;
779 for (unsigned m = 0; m < unique_bo_count; ++m) {
780 if (handles[m].bo_handle == bo->bo_handle) {
781 found = true;
782 break;
783 }
784 }
785 if (!found) {
786 handles[unique_bo_count].bo_handle = bo->bo_handle;
787 handles[unique_bo_count].bo_priority = bo->priority;
788 ++unique_bo_count;
789 }
790 }
791 }
792 }
793
794 if (radv_bo_list) {
795 unsigned unique_bo_so_far = unique_bo_count;
796 for (unsigned i = 0; i < radv_bo_list->count; ++i) {
797 struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(radv_bo_list->bos[i]);
798 bool found = false;
799 for (unsigned j = 0; j < unique_bo_so_far; ++j) {
800 if (bo->bo_handle == handles[j].bo_handle) {
801 found = true;
802 break;
803 }
804 }
805 if (!found) {
806 handles[unique_bo_count].bo_handle = bo->bo_handle;
807 handles[unique_bo_count].bo_priority = bo->priority;
808 ++unique_bo_count;
809 }
810 }
811 }
812
813 if (unique_bo_count > 0) {
814 r = amdgpu_bo_list_create_raw(ws->dev, unique_bo_count, handles,
815 bo_list);
816 } else {
817 *bo_list = 0;
818 }
819
820 free(handles);
821 }
822
823 return r;
824 }
825
826 static struct amdgpu_cs_fence_info radv_set_cs_fence(struct radv_amdgpu_ctx *ctx, int ip_type, int ring)
827 {
828 struct amdgpu_cs_fence_info ret = {0};
829 if (ctx->fence_map) {
830 ret.handle = radv_amdgpu_winsys_bo(ctx->fence_bo)->bo;
831 ret.offset = (ip_type * MAX_RINGS_PER_TYPE + ring) * sizeof(uint64_t);
832 }
833 return ret;
834 }
835
836 static void radv_assign_last_submit(struct radv_amdgpu_ctx *ctx,
837 struct radv_amdgpu_cs_request *request)
838 {
839 radv_amdgpu_request_to_fence(ctx,
840 &ctx->last_submission[request->ip_type][request->ring],
841 request);
842 }
843
844 static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx *_ctx,
845 int queue_idx,
846 struct radv_winsys_sem_info *sem_info,
847 const struct radv_winsys_bo_list *radv_bo_list,
848 struct radeon_cmdbuf **cs_array,
849 unsigned cs_count,
850 struct radeon_cmdbuf *initial_preamble_cs,
851 struct radeon_cmdbuf *continue_preamble_cs,
852 struct radeon_winsys_fence *_fence)
853 {
854 int r;
855 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
856 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
857 struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[0]);
858 uint32_t bo_list;
859 struct radv_amdgpu_cs_request request = {0};
860 struct amdgpu_cs_ib_info ibs[2];
861 unsigned number_of_ibs = 1;
862
863 for (unsigned i = cs_count; i--;) {
864 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
865
866 if (cs->is_chained) {
867 *cs->ib_size_ptr -= 4;
868 cs->is_chained = false;
869 }
870
871 if (i + 1 < cs_count) {
872 struct radv_amdgpu_cs *next = radv_amdgpu_cs(cs_array[i + 1]);
873 assert(cs->base.cdw + 4 <= cs->base.max_dw);
874
875 cs->is_chained = true;
876 *cs->ib_size_ptr += 4;
877
878 cs->base.buf[cs->base.cdw + 0] = PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0);
879 cs->base.buf[cs->base.cdw + 1] = next->ib.ib_mc_address;
880 cs->base.buf[cs->base.cdw + 2] = next->ib.ib_mc_address >> 32;
881 cs->base.buf[cs->base.cdw + 3] = S_3F2_CHAIN(1) | S_3F2_VALID(1) | next->ib.size;
882 }
883 }
884
885 /* Create a buffer object list. */
886 r = radv_amdgpu_create_bo_list(cs0->ws, cs_array, cs_count, NULL, 0,
887 initial_preamble_cs, radv_bo_list,
888 &bo_list);
889 if (r) {
890 fprintf(stderr, "amdgpu: buffer list creation failed for the "
891 "chained submission(%d)\n", r);
892 return r;
893 }
894
895 /* Configure the CS request. */
896 if (initial_preamble_cs) {
897 ibs[0] = radv_amdgpu_cs(initial_preamble_cs)->ib;
898 ibs[1] = cs0->ib;
899 number_of_ibs++;
900 } else {
901 ibs[0] = cs0->ib;
902 }
903
904 request.ip_type = cs0->hw_ip;
905 request.ring = queue_idx;
906 request.number_of_ibs = number_of_ibs;
907 request.ibs = ibs;
908 request.resources = bo_list;
909 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
910
911 /* Submit the CS. */
912 r = radv_amdgpu_cs_submit(ctx, &request, sem_info);
913 if (r) {
914 if (r == -ENOMEM)
915 fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
916 else
917 fprintf(stderr, "amdgpu: The CS has been rejected, "
918 "see dmesg for more information.\n");
919 }
920
921 amdgpu_bo_list_destroy_raw(ctx->ws->dev, bo_list);
922
923 if (r)
924 return r;
925
926 if (fence)
927 radv_amdgpu_request_to_fence(ctx, fence, &request);
928
929 radv_assign_last_submit(ctx, &request);
930
931 return 0;
932 }
933
934 static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx *_ctx,
935 int queue_idx,
936 struct radv_winsys_sem_info *sem_info,
937 const struct radv_winsys_bo_list *radv_bo_list,
938 struct radeon_cmdbuf **cs_array,
939 unsigned cs_count,
940 struct radeon_cmdbuf *initial_preamble_cs,
941 struct radeon_cmdbuf *continue_preamble_cs,
942 struct radeon_winsys_fence *_fence)
943 {
944 int r;
945 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
946 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
947 uint32_t bo_list;
948 struct radv_amdgpu_cs_request request = {};
949 struct amdgpu_cs_ib_info *ibs;
950 struct radv_amdgpu_cs *cs0;
951 unsigned number_of_ibs;
952
953 assert(cs_count);
954 cs0 = radv_amdgpu_cs(cs_array[0]);
955
956 /* Compute the number of IBs for this submit. */
957 number_of_ibs = cs_count + !!initial_preamble_cs;
958
959 /* Create a buffer object list. */
960 r = radv_amdgpu_create_bo_list(cs0->ws, &cs_array[0], cs_count, NULL, 0,
961 initial_preamble_cs, radv_bo_list,
962 &bo_list);
963 if (r) {
964 fprintf(stderr, "amdgpu: buffer list creation failed "
965 "for the fallback submission (%d)\n", r);
966 return r;
967 }
968
969 ibs = malloc(number_of_ibs * sizeof(*ibs));
970 if (!ibs) {
971 amdgpu_bo_list_destroy_raw(ctx->ws->dev, bo_list);
972 return -ENOMEM;
973 }
974
975 /* Configure the CS request. */
976 if (initial_preamble_cs)
977 ibs[0] = radv_amdgpu_cs(initial_preamble_cs)->ib;
978
979 for (unsigned i = 0; i < cs_count; i++) {
980 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
981
982 ibs[i + !!initial_preamble_cs] = cs->ib;
983
984 if (cs->is_chained) {
985 *cs->ib_size_ptr -= 4;
986 cs->is_chained = false;
987 }
988 }
989
990 request.ip_type = cs0->hw_ip;
991 request.ring = queue_idx;
992 request.resources = bo_list;
993 request.number_of_ibs = number_of_ibs;
994 request.ibs = ibs;
995 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
996
997 /* Submit the CS. */
998 r = radv_amdgpu_cs_submit(ctx, &request, sem_info);
999 if (r) {
1000 if (r == -ENOMEM)
1001 fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
1002 else
1003 fprintf(stderr, "amdgpu: The CS has been rejected, "
1004 "see dmesg for more information.\n");
1005 }
1006
1007 amdgpu_bo_list_destroy_raw(ctx->ws->dev, bo_list);
1008 free(ibs);
1009
1010 if (r)
1011 return r;
1012
1013 if (fence)
1014 radv_amdgpu_request_to_fence(ctx, fence, &request);
1015
1016 radv_assign_last_submit(ctx, &request);
1017
1018 return 0;
1019 }
1020
1021 static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
1022 int queue_idx,
1023 struct radv_winsys_sem_info *sem_info,
1024 const struct radv_winsys_bo_list *radv_bo_list,
1025 struct radeon_cmdbuf **cs_array,
1026 unsigned cs_count,
1027 struct radeon_cmdbuf *initial_preamble_cs,
1028 struct radeon_cmdbuf *continue_preamble_cs,
1029 struct radeon_winsys_fence *_fence)
1030 {
1031 int r;
1032 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
1033 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
1034 struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[0]);
1035 struct radeon_winsys *ws = (struct radeon_winsys*)cs0->ws;
1036 uint32_t bo_list;
1037 struct radv_amdgpu_cs_request request;
1038 uint32_t pad_word = 0xffff1000U;
1039 bool emit_signal_sem = sem_info->cs_emit_signal;
1040
1041 if (radv_amdgpu_winsys(ws)->info.chip_class == GFX6)
1042 pad_word = 0x80000000;
1043
1044 assert(cs_count);
1045
1046 for (unsigned i = 0; i < cs_count;) {
1047 struct amdgpu_cs_ib_info *ibs;
1048 struct radeon_winsys_bo **bos;
1049 struct radeon_cmdbuf *preamble_cs = i ? continue_preamble_cs : initial_preamble_cs;
1050 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
1051 unsigned number_of_ibs;
1052 uint32_t *ptr;
1053 unsigned cnt = 0;
1054 unsigned size = 0;
1055 unsigned pad_words = 0;
1056
1057 /* Compute the number of IBs for this submit. */
1058 number_of_ibs = cs->num_old_cs_buffers + 1;
1059
1060 ibs = malloc(number_of_ibs * sizeof(*ibs));
1061 if (!ibs)
1062 return -ENOMEM;
1063
1064 bos = malloc(number_of_ibs * sizeof(*bos));
1065 if (!bos) {
1066 free(ibs);
1067 return -ENOMEM;
1068 }
1069
1070 if (number_of_ibs > 1) {
1071 /* Special path when the maximum size in dwords has
1072 * been reached because we need to handle more than one
1073 * IB per submit.
1074 */
1075 struct radeon_cmdbuf **new_cs_array;
1076 unsigned idx = 0;
1077
1078 new_cs_array = malloc(cs->num_old_cs_buffers *
1079 sizeof(*new_cs_array));
1080 assert(new_cs_array);
1081
1082 for (unsigned j = 0; j < cs->num_old_cs_buffers; j++)
1083 new_cs_array[idx++] = &cs->old_cs_buffers[j];
1084 new_cs_array[idx++] = cs_array[i];
1085
1086 for (unsigned j = 0; j < number_of_ibs; j++) {
1087 struct radeon_cmdbuf *rcs = new_cs_array[j];
1088 bool needs_preamble = preamble_cs && j == 0;
1089 unsigned size = 0;
1090
1091 if (needs_preamble)
1092 size += preamble_cs->cdw;
1093 size += rcs->cdw;
1094
1095 assert(size < 0xffff8);
1096
1097 while (!size || (size & 7)) {
1098 size++;
1099 pad_words++;
1100 }
1101
1102 bos[j] = ws->buffer_create(ws, 4 * size, 4096,
1103 RADEON_DOMAIN_GTT,
1104 RADEON_FLAG_CPU_ACCESS |
1105 RADEON_FLAG_NO_INTERPROCESS_SHARING |
1106 RADEON_FLAG_READ_ONLY,
1107 RADV_BO_PRIORITY_CS);
1108 ptr = ws->buffer_map(bos[j]);
1109
1110 if (needs_preamble) {
1111 memcpy(ptr, preamble_cs->buf, preamble_cs->cdw * 4);
1112 ptr += preamble_cs->cdw;
1113 }
1114
1115 memcpy(ptr, rcs->buf, 4 * rcs->cdw);
1116 ptr += rcs->cdw;
1117
1118 for (unsigned k = 0; k < pad_words; ++k)
1119 *ptr++ = pad_word;
1120
1121 ibs[j].size = size;
1122 ibs[j].ib_mc_address = radv_buffer_get_va(bos[j]);
1123 ibs[j].flags = 0;
1124 }
1125
1126 cnt++;
1127 free(new_cs_array);
1128 } else {
1129 if (preamble_cs)
1130 size += preamble_cs->cdw;
1131
1132 while (i + cnt < cs_count && 0xffff8 - size >= radv_amdgpu_cs(cs_array[i + cnt])->base.cdw) {
1133 size += radv_amdgpu_cs(cs_array[i + cnt])->base.cdw;
1134 ++cnt;
1135 }
1136
1137 while (!size || (size & 7)) {
1138 size++;
1139 pad_words++;
1140 }
1141 assert(cnt);
1142
1143 bos[0] = ws->buffer_create(ws, 4 * size, 4096,
1144 RADEON_DOMAIN_GTT,
1145 RADEON_FLAG_CPU_ACCESS |
1146 RADEON_FLAG_NO_INTERPROCESS_SHARING |
1147 RADEON_FLAG_READ_ONLY,
1148 RADV_BO_PRIORITY_CS);
1149 ptr = ws->buffer_map(bos[0]);
1150
1151 if (preamble_cs) {
1152 memcpy(ptr, preamble_cs->buf, preamble_cs->cdw * 4);
1153 ptr += preamble_cs->cdw;
1154 }
1155
1156 for (unsigned j = 0; j < cnt; ++j) {
1157 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i + j]);
1158 memcpy(ptr, cs->base.buf, 4 * cs->base.cdw);
1159 ptr += cs->base.cdw;
1160
1161 }
1162
1163 for (unsigned j = 0; j < pad_words; ++j)
1164 *ptr++ = pad_word;
1165
1166 ibs[0].size = size;
1167 ibs[0].ib_mc_address = radv_buffer_get_va(bos[0]);
1168 ibs[0].flags = 0;
1169 }
1170
1171 r = radv_amdgpu_create_bo_list(cs0->ws, &cs_array[i], cnt,
1172 (struct radv_amdgpu_winsys_bo **)bos,
1173 number_of_ibs, preamble_cs,
1174 radv_bo_list, &bo_list);
1175 if (r) {
1176 fprintf(stderr, "amdgpu: buffer list creation failed "
1177 "for the sysmem submission (%d)\n", r);
1178 free(ibs);
1179 free(bos);
1180 return r;
1181 }
1182
1183 memset(&request, 0, sizeof(request));
1184
1185 request.ip_type = cs0->hw_ip;
1186 request.ring = queue_idx;
1187 request.resources = bo_list;
1188 request.number_of_ibs = number_of_ibs;
1189 request.ibs = ibs;
1190 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
1191
1192 sem_info->cs_emit_signal = (i == cs_count - cnt) ? emit_signal_sem : false;
1193 r = radv_amdgpu_cs_submit(ctx, &request, sem_info);
1194 if (r) {
1195 if (r == -ENOMEM)
1196 fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
1197 else
1198 fprintf(stderr, "amdgpu: The CS has been rejected, "
1199 "see dmesg for more information.\n");
1200 }
1201
1202 amdgpu_bo_list_destroy_raw(ctx->ws->dev, bo_list);
1203
1204 for (unsigned j = 0; j < number_of_ibs; j++) {
1205 ws->buffer_destroy(bos[j]);
1206 }
1207
1208 free(ibs);
1209 free(bos);
1210
1211 if (r)
1212 return r;
1213
1214 i += cnt;
1215 }
1216 if (fence)
1217 radv_amdgpu_request_to_fence(ctx, fence, &request);
1218
1219 radv_assign_last_submit(ctx, &request);
1220
1221 return 0;
1222 }
1223
1224 static int radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx,
1225 int queue_idx,
1226 struct radeon_cmdbuf **cs_array,
1227 unsigned cs_count,
1228 struct radeon_cmdbuf *initial_preamble_cs,
1229 struct radeon_cmdbuf *continue_preamble_cs,
1230 struct radv_winsys_sem_info *sem_info,
1231 const struct radv_winsys_bo_list *bo_list,
1232 bool can_patch,
1233 struct radeon_winsys_fence *_fence)
1234 {
1235 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[0]);
1236 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
1237 int ret;
1238
1239 assert(sem_info);
1240 if (!cs->ws->use_ib_bos) {
1241 ret = radv_amdgpu_winsys_cs_submit_sysmem(_ctx, queue_idx, sem_info, bo_list, cs_array,
1242 cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
1243 } else if (can_patch) {
1244 ret = radv_amdgpu_winsys_cs_submit_chained(_ctx, queue_idx, sem_info, bo_list, cs_array,
1245 cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
1246 } else {
1247 ret = radv_amdgpu_winsys_cs_submit_fallback(_ctx, queue_idx, sem_info, bo_list, cs_array,
1248 cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
1249 }
1250
1251 radv_amdgpu_signal_sems(ctx, cs->hw_ip, queue_idx, sem_info);
1252 return ret;
1253 }
1254
1255 static void *radv_amdgpu_winsys_get_cpu_addr(void *_cs, uint64_t addr)
1256 {
1257 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)_cs;
1258 void *ret = NULL;
1259
1260 if (!cs->ib_buffer)
1261 return NULL;
1262 for (unsigned i = 0; i <= cs->num_old_ib_buffers; ++i) {
1263 struct radv_amdgpu_winsys_bo *bo;
1264
1265 bo = (struct radv_amdgpu_winsys_bo*)
1266 (i == cs->num_old_ib_buffers ? cs->ib_buffer : cs->old_ib_buffers[i]);
1267 if (addr >= bo->base.va && addr - bo->base.va < bo->size) {
1268 if (amdgpu_bo_cpu_map(bo->bo, &ret) == 0)
1269 return (char *)ret + (addr - bo->base.va);
1270 }
1271 }
1272 if(cs->ws->debug_all_bos) {
1273 pthread_mutex_lock(&cs->ws->global_bo_list_lock);
1274 list_for_each_entry(struct radv_amdgpu_winsys_bo, bo,
1275 &cs->ws->global_bo_list, global_list_item) {
1276 if (addr >= bo->base.va && addr - bo->base.va < bo->size) {
1277 if (amdgpu_bo_cpu_map(bo->bo, &ret) == 0) {
1278 pthread_mutex_unlock(&cs->ws->global_bo_list_lock);
1279 return (char *)ret + (addr - bo->base.va);
1280 }
1281 }
1282 }
1283 pthread_mutex_unlock(&cs->ws->global_bo_list_lock);
1284 }
1285 return ret;
1286 }
1287
1288 static void radv_amdgpu_winsys_cs_dump(struct radeon_cmdbuf *_cs,
1289 FILE* file,
1290 const int *trace_ids, int trace_id_count)
1291 {
1292 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)_cs;
1293 void *ib = cs->base.buf;
1294 int num_dw = cs->base.cdw;
1295
1296 if (cs->ws->use_ib_bos) {
1297 ib = radv_amdgpu_winsys_get_cpu_addr(cs, cs->ib.ib_mc_address);
1298 num_dw = cs->ib.size;
1299 }
1300 assert(ib);
1301 ac_parse_ib(file, ib, num_dw, trace_ids, trace_id_count, "main IB",
1302 cs->ws->info.chip_class, radv_amdgpu_winsys_get_cpu_addr, cs);
1303 }
1304
1305 static uint32_t radv_to_amdgpu_priority(enum radeon_ctx_priority radv_priority)
1306 {
1307 switch (radv_priority) {
1308 case RADEON_CTX_PRIORITY_REALTIME:
1309 return AMDGPU_CTX_PRIORITY_VERY_HIGH;
1310 case RADEON_CTX_PRIORITY_HIGH:
1311 return AMDGPU_CTX_PRIORITY_HIGH;
1312 case RADEON_CTX_PRIORITY_MEDIUM:
1313 return AMDGPU_CTX_PRIORITY_NORMAL;
1314 case RADEON_CTX_PRIORITY_LOW:
1315 return AMDGPU_CTX_PRIORITY_LOW;
1316 default:
1317 unreachable("Invalid context priority");
1318 }
1319 }
1320
1321 static VkResult radv_amdgpu_ctx_create(struct radeon_winsys *_ws,
1322 enum radeon_ctx_priority priority,
1323 struct radeon_winsys_ctx **rctx)
1324 {
1325 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1326 struct radv_amdgpu_ctx *ctx = CALLOC_STRUCT(radv_amdgpu_ctx);
1327 uint32_t amdgpu_priority = radv_to_amdgpu_priority(priority);
1328 VkResult result;
1329 int r;
1330
1331 if (!ctx)
1332 return VK_ERROR_OUT_OF_HOST_MEMORY;
1333
1334 r = amdgpu_cs_ctx_create2(ws->dev, amdgpu_priority, &ctx->ctx);
1335 if (r && r == -EACCES) {
1336 result = VK_ERROR_NOT_PERMITTED_EXT;
1337 goto error_create;
1338 } else if (r) {
1339 fprintf(stderr, "amdgpu: radv_amdgpu_cs_ctx_create2 failed. (%i)\n", r);
1340 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1341 goto error_create;
1342 }
1343 ctx->ws = ws;
1344
1345 assert(AMDGPU_HW_IP_NUM * MAX_RINGS_PER_TYPE * sizeof(uint64_t) <= 4096);
1346 ctx->fence_bo = ws->base.buffer_create(&ws->base, 4096, 8,
1347 RADEON_DOMAIN_GTT,
1348 RADEON_FLAG_CPU_ACCESS |
1349 RADEON_FLAG_NO_INTERPROCESS_SHARING,
1350 RADV_BO_PRIORITY_CS);
1351 if (ctx->fence_bo)
1352 ctx->fence_map = (uint64_t*)ws->base.buffer_map(ctx->fence_bo);
1353 if (ctx->fence_map)
1354 memset(ctx->fence_map, 0, 4096);
1355
1356 *rctx = (struct radeon_winsys_ctx *)ctx;
1357 return VK_SUCCESS;
1358 error_create:
1359 FREE(ctx);
1360 return result;
1361 }
1362
1363 static void radv_amdgpu_ctx_destroy(struct radeon_winsys_ctx *rwctx)
1364 {
1365 struct radv_amdgpu_ctx *ctx = (struct radv_amdgpu_ctx *)rwctx;
1366 ctx->ws->base.buffer_destroy(ctx->fence_bo);
1367 amdgpu_cs_ctx_free(ctx->ctx);
1368 FREE(ctx);
1369 }
1370
1371 static bool radv_amdgpu_ctx_wait_idle(struct radeon_winsys_ctx *rwctx,
1372 enum ring_type ring_type, int ring_index)
1373 {
1374 struct radv_amdgpu_ctx *ctx = (struct radv_amdgpu_ctx *)rwctx;
1375 int ip_type = ring_to_hw_ip(ring_type);
1376
1377 if (ctx->last_submission[ip_type][ring_index].fence.fence) {
1378 uint32_t expired;
1379 int ret = amdgpu_cs_query_fence_status(&ctx->last_submission[ip_type][ring_index].fence,
1380 1000000000ull, 0, &expired);
1381
1382 if (ret || !expired)
1383 return false;
1384 }
1385
1386 return true;
1387 }
1388
1389 static struct radeon_winsys_sem *radv_amdgpu_create_sem(struct radeon_winsys *_ws)
1390 {
1391 struct amdgpu_cs_fence *sem = CALLOC_STRUCT(amdgpu_cs_fence);
1392 if (!sem)
1393 return NULL;
1394
1395 return (struct radeon_winsys_sem *)sem;
1396 }
1397
1398 static void radv_amdgpu_destroy_sem(struct radeon_winsys_sem *_sem)
1399 {
1400 struct amdgpu_cs_fence *sem = (struct amdgpu_cs_fence *)_sem;
1401 FREE(sem);
1402 }
1403
1404 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx *ctx,
1405 uint32_t ip_type,
1406 uint32_t ring,
1407 struct radv_winsys_sem_info *sem_info)
1408 {
1409 for (unsigned i = 0; i < sem_info->signal.sem_count; i++) {
1410 struct amdgpu_cs_fence *sem = (struct amdgpu_cs_fence *)(sem_info->signal.sem)[i];
1411
1412 if (sem->context)
1413 return -EINVAL;
1414
1415 *sem = ctx->last_submission[ip_type][ring].fence;
1416 }
1417 return 0;
1418 }
1419
1420 static struct drm_amdgpu_cs_chunk_sem *radv_amdgpu_cs_alloc_syncobj_chunk(struct radv_winsys_sem_counts *counts,
1421 struct drm_amdgpu_cs_chunk *chunk, int chunk_id)
1422 {
1423 struct drm_amdgpu_cs_chunk_sem *syncobj = malloc(sizeof(struct drm_amdgpu_cs_chunk_sem) * counts->syncobj_count);
1424 if (!syncobj)
1425 return NULL;
1426
1427 for (unsigned i = 0; i < counts->syncobj_count; i++) {
1428 struct drm_amdgpu_cs_chunk_sem *sem = &syncobj[i];
1429 sem->handle = counts->syncobj[i];
1430 }
1431
1432 chunk->chunk_id = chunk_id;
1433 chunk->length_dw = sizeof(struct drm_amdgpu_cs_chunk_sem) / 4 * counts->syncobj_count;
1434 chunk->chunk_data = (uint64_t)(uintptr_t)syncobj;
1435 return syncobj;
1436 }
1437
1438 static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx,
1439 struct radv_amdgpu_cs_request *request,
1440 struct radv_winsys_sem_info *sem_info)
1441 {
1442 int r;
1443 int num_chunks;
1444 int size;
1445 bool user_fence;
1446 struct drm_amdgpu_cs_chunk *chunks;
1447 struct drm_amdgpu_cs_chunk_data *chunk_data;
1448 struct drm_amdgpu_cs_chunk_dep *sem_dependencies = NULL;
1449 struct drm_amdgpu_cs_chunk_sem *wait_syncobj = NULL, *signal_syncobj = NULL;
1450 int i;
1451 struct amdgpu_cs_fence *sem;
1452
1453 user_fence = (request->fence_info.handle != NULL);
1454 size = request->number_of_ibs + (user_fence ? 2 : 1) + 3;
1455
1456 chunks = alloca(sizeof(struct drm_amdgpu_cs_chunk) * size);
1457
1458 size = request->number_of_ibs + (user_fence ? 1 : 0);
1459
1460 chunk_data = alloca(sizeof(struct drm_amdgpu_cs_chunk_data) * size);
1461
1462 num_chunks = request->number_of_ibs;
1463 for (i = 0; i < request->number_of_ibs; i++) {
1464 struct amdgpu_cs_ib_info *ib;
1465 chunks[i].chunk_id = AMDGPU_CHUNK_ID_IB;
1466 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
1467 chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
1468
1469 ib = &request->ibs[i];
1470
1471 chunk_data[i].ib_data._pad = 0;
1472 chunk_data[i].ib_data.va_start = ib->ib_mc_address;
1473 chunk_data[i].ib_data.ib_bytes = ib->size * 4;
1474 chunk_data[i].ib_data.ip_type = request->ip_type;
1475 chunk_data[i].ib_data.ip_instance = request->ip_instance;
1476 chunk_data[i].ib_data.ring = request->ring;
1477 chunk_data[i].ib_data.flags = ib->flags;
1478 }
1479
1480 if (user_fence) {
1481 i = num_chunks++;
1482
1483 chunks[i].chunk_id = AMDGPU_CHUNK_ID_FENCE;
1484 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_fence) / 4;
1485 chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
1486
1487 amdgpu_cs_chunk_fence_info_to_data(&request->fence_info,
1488 &chunk_data[i]);
1489 }
1490
1491 if (sem_info->wait.syncobj_count && sem_info->cs_emit_wait) {
1492 wait_syncobj = radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info->wait,
1493 &chunks[num_chunks],
1494 AMDGPU_CHUNK_ID_SYNCOBJ_IN);
1495 if (!wait_syncobj) {
1496 r = -ENOMEM;
1497 goto error_out;
1498 }
1499 num_chunks++;
1500
1501 if (sem_info->wait.sem_count == 0)
1502 sem_info->cs_emit_wait = false;
1503
1504 }
1505
1506 if (sem_info->wait.sem_count && sem_info->cs_emit_wait) {
1507 sem_dependencies = alloca(sizeof(struct drm_amdgpu_cs_chunk_dep) * sem_info->wait.sem_count);
1508 int sem_count = 0;
1509
1510 for (unsigned j = 0; j < sem_info->wait.sem_count; j++) {
1511 sem = (struct amdgpu_cs_fence *)sem_info->wait.sem[j];
1512 if (!sem->context)
1513 continue;
1514 struct drm_amdgpu_cs_chunk_dep *dep = &sem_dependencies[sem_count++];
1515
1516 amdgpu_cs_chunk_fence_to_dep(sem, dep);
1517
1518 sem->context = NULL;
1519 }
1520 i = num_chunks++;
1521
1522 /* dependencies chunk */
1523 chunks[i].chunk_id = AMDGPU_CHUNK_ID_DEPENDENCIES;
1524 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_dep) / 4 * sem_count;
1525 chunks[i].chunk_data = (uint64_t)(uintptr_t)sem_dependencies;
1526
1527 sem_info->cs_emit_wait = false;
1528 }
1529
1530 if (sem_info->signal.syncobj_count && sem_info->cs_emit_signal) {
1531 signal_syncobj = radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info->signal,
1532 &chunks[num_chunks],
1533 AMDGPU_CHUNK_ID_SYNCOBJ_OUT);
1534 if (!signal_syncobj) {
1535 r = -ENOMEM;
1536 goto error_out;
1537 }
1538 num_chunks++;
1539 }
1540
1541 r = amdgpu_cs_submit_raw2(ctx->ws->dev,
1542 ctx->ctx,
1543 request->resources,
1544 num_chunks,
1545 chunks,
1546 &request->seq_no);
1547 error_out:
1548 free(wait_syncobj);
1549 free(signal_syncobj);
1550 return r;
1551 }
1552
1553 static int radv_amdgpu_create_syncobj(struct radeon_winsys *_ws,
1554 uint32_t *handle)
1555 {
1556 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1557 return amdgpu_cs_create_syncobj(ws->dev, handle);
1558 }
1559
1560 static void radv_amdgpu_destroy_syncobj(struct radeon_winsys *_ws,
1561 uint32_t handle)
1562 {
1563 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1564 amdgpu_cs_destroy_syncobj(ws->dev, handle);
1565 }
1566
1567 static void radv_amdgpu_reset_syncobj(struct radeon_winsys *_ws,
1568 uint32_t handle)
1569 {
1570 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1571 amdgpu_cs_syncobj_reset(ws->dev, &handle, 1);
1572 }
1573
1574 static void radv_amdgpu_signal_syncobj(struct radeon_winsys *_ws,
1575 uint32_t handle)
1576 {
1577 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1578 amdgpu_cs_syncobj_signal(ws->dev, &handle, 1);
1579 }
1580
1581 static bool radv_amdgpu_wait_syncobj(struct radeon_winsys *_ws, const uint32_t *handles,
1582 uint32_t handle_count, bool wait_all, uint64_t timeout)
1583 {
1584 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1585 uint32_t tmp;
1586
1587 /* The timeouts are signed, while vulkan timeouts are unsigned. */
1588 timeout = MIN2(timeout, INT64_MAX);
1589
1590 int ret = amdgpu_cs_syncobj_wait(ws->dev, (uint32_t*)handles, handle_count, timeout,
1591 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT |
1592 (wait_all ? DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL : 0),
1593 &tmp);
1594 if (ret == 0) {
1595 return true;
1596 } else if (ret == -ETIME) {
1597 return false;
1598 } else {
1599 fprintf(stderr, "amdgpu: radv_amdgpu_wait_syncobj failed!\nerrno: %d\n", errno);
1600 return false;
1601 }
1602 }
1603
1604 static int radv_amdgpu_export_syncobj(struct radeon_winsys *_ws,
1605 uint32_t syncobj,
1606 int *fd)
1607 {
1608 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1609
1610 return amdgpu_cs_export_syncobj(ws->dev, syncobj, fd);
1611 }
1612
1613 static int radv_amdgpu_import_syncobj(struct radeon_winsys *_ws,
1614 int fd,
1615 uint32_t *syncobj)
1616 {
1617 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1618
1619 return amdgpu_cs_import_syncobj(ws->dev, fd, syncobj);
1620 }
1621
1622
1623 static int radv_amdgpu_export_syncobj_to_sync_file(struct radeon_winsys *_ws,
1624 uint32_t syncobj,
1625 int *fd)
1626 {
1627 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1628
1629 return amdgpu_cs_syncobj_export_sync_file(ws->dev, syncobj, fd);
1630 }
1631
1632 static int radv_amdgpu_import_syncobj_from_sync_file(struct radeon_winsys *_ws,
1633 uint32_t syncobj,
1634 int fd)
1635 {
1636 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1637
1638 return amdgpu_cs_syncobj_import_sync_file(ws->dev, syncobj, fd);
1639 }
1640
1641 void radv_amdgpu_cs_init_functions(struct radv_amdgpu_winsys *ws)
1642 {
1643 ws->base.ctx_create = radv_amdgpu_ctx_create;
1644 ws->base.ctx_destroy = radv_amdgpu_ctx_destroy;
1645 ws->base.ctx_wait_idle = radv_amdgpu_ctx_wait_idle;
1646 ws->base.cs_create = radv_amdgpu_cs_create;
1647 ws->base.cs_destroy = radv_amdgpu_cs_destroy;
1648 ws->base.cs_grow = radv_amdgpu_cs_grow;
1649 ws->base.cs_finalize = radv_amdgpu_cs_finalize;
1650 ws->base.cs_reset = radv_amdgpu_cs_reset;
1651 ws->base.cs_add_buffer = radv_amdgpu_cs_add_buffer;
1652 ws->base.cs_execute_secondary = radv_amdgpu_cs_execute_secondary;
1653 ws->base.cs_submit = radv_amdgpu_winsys_cs_submit;
1654 ws->base.cs_dump = radv_amdgpu_winsys_cs_dump;
1655 ws->base.create_fence = radv_amdgpu_create_fence;
1656 ws->base.destroy_fence = radv_amdgpu_destroy_fence;
1657 ws->base.reset_fence = radv_amdgpu_reset_fence;
1658 ws->base.signal_fence = radv_amdgpu_signal_fence;
1659 ws->base.is_fence_waitable = radv_amdgpu_is_fence_waitable;
1660 ws->base.create_sem = radv_amdgpu_create_sem;
1661 ws->base.destroy_sem = radv_amdgpu_destroy_sem;
1662 ws->base.create_syncobj = radv_amdgpu_create_syncobj;
1663 ws->base.destroy_syncobj = radv_amdgpu_destroy_syncobj;
1664 ws->base.reset_syncobj = radv_amdgpu_reset_syncobj;
1665 ws->base.signal_syncobj = radv_amdgpu_signal_syncobj;
1666 ws->base.wait_syncobj = radv_amdgpu_wait_syncobj;
1667 ws->base.export_syncobj = radv_amdgpu_export_syncobj;
1668 ws->base.import_syncobj = radv_amdgpu_import_syncobj;
1669 ws->base.export_syncobj_to_sync_file = radv_amdgpu_export_syncobj_to_sync_file;
1670 ws->base.import_syncobj_from_sync_file = radv_amdgpu_import_syncobj_from_sync_file;
1671 ws->base.fence_wait = radv_amdgpu_fence_wait;
1672 ws->base.fences_wait = radv_amdgpu_fences_wait;
1673 }