2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include <amdgpu_drm.h>
31 #include "radv_radeon_winsys.h"
32 #include "radv_amdgpu_cs.h"
33 #include "radv_amdgpu_bo.h"
38 VIRTUAL_BUFFER_HASH_TABLE_SIZE
= 1024
41 struct radv_amdgpu_cs
{
42 struct radeon_winsys_cs base
;
43 struct radv_amdgpu_winsys
*ws
;
45 struct amdgpu_cs_ib_info ib
;
47 struct radeon_winsys_bo
*ib_buffer
;
49 unsigned max_num_buffers
;
51 amdgpu_bo_handle
*handles
;
54 struct radeon_winsys_bo
**old_ib_buffers
;
55 unsigned num_old_ib_buffers
;
56 unsigned max_num_old_ib_buffers
;
57 unsigned *ib_size_ptr
;
61 int buffer_hash_table
[1024];
64 unsigned num_virtual_buffers
;
65 unsigned max_num_virtual_buffers
;
66 struct radeon_winsys_bo
**virtual_buffers
;
67 uint8_t *virtual_buffer_priorities
;
68 int *virtual_buffer_hash_table
;
71 static inline struct radv_amdgpu_cs
*
72 radv_amdgpu_cs(struct radeon_winsys_cs
*base
)
74 return (struct radv_amdgpu_cs
*)base
;
77 static int ring_to_hw_ip(enum ring_type ring
)
81 return AMDGPU_HW_IP_GFX
;
83 return AMDGPU_HW_IP_DMA
;
85 return AMDGPU_HW_IP_COMPUTE
;
87 unreachable("unsupported ring");
91 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx
*ctx
,
94 struct radv_winsys_sem_info
*sem_info
);
95 static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx
*ctx
,
96 struct amdgpu_cs_request
*request
,
97 struct radv_winsys_sem_info
*sem_info
);
99 static void radv_amdgpu_request_to_fence(struct radv_amdgpu_ctx
*ctx
,
100 struct radv_amdgpu_fence
*fence
,
101 struct amdgpu_cs_request
*req
)
103 fence
->fence
.context
= ctx
->ctx
;
104 fence
->fence
.ip_type
= req
->ip_type
;
105 fence
->fence
.ip_instance
= req
->ip_instance
;
106 fence
->fence
.ring
= req
->ring
;
107 fence
->fence
.fence
= req
->seq_no
;
108 fence
->user_ptr
= (volatile uint64_t*)(ctx
->fence_map
+ (req
->ip_type
* MAX_RINGS_PER_TYPE
+ req
->ring
) * sizeof(uint64_t));
111 static struct radeon_winsys_fence
*radv_amdgpu_create_fence()
113 struct radv_amdgpu_fence
*fence
= calloc(1, sizeof(struct radv_amdgpu_fence
));
114 return (struct radeon_winsys_fence
*)fence
;
117 static void radv_amdgpu_destroy_fence(struct radeon_winsys_fence
*_fence
)
119 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
123 static bool radv_amdgpu_fence_wait(struct radeon_winsys
*_ws
,
124 struct radeon_winsys_fence
*_fence
,
128 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
129 unsigned flags
= absolute
? AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE
: 0;
131 uint32_t expired
= 0;
133 if (fence
->user_ptr
) {
134 if (*fence
->user_ptr
>= fence
->fence
.fence
)
136 if (!absolute
&& !timeout
)
140 /* Now use the libdrm query. */
141 r
= amdgpu_cs_query_fence_status(&fence
->fence
,
147 fprintf(stderr
, "amdgpu: radv_amdgpu_cs_query_fence_status failed.\n");
157 static void radv_amdgpu_cs_destroy(struct radeon_winsys_cs
*rcs
)
159 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(rcs
);
162 cs
->ws
->base
.buffer_destroy(cs
->ib_buffer
);
166 for (unsigned i
= 0; i
< cs
->num_old_ib_buffers
; ++i
)
167 cs
->ws
->base
.buffer_destroy(cs
->old_ib_buffers
[i
]);
169 free(cs
->old_ib_buffers
);
170 free(cs
->virtual_buffers
);
171 free(cs
->virtual_buffer_priorities
);
172 free(cs
->virtual_buffer_hash_table
);
174 free(cs
->priorities
);
178 static boolean
radv_amdgpu_init_cs(struct radv_amdgpu_cs
*cs
,
179 enum ring_type ring_type
)
181 for (int i
= 0; i
< ARRAY_SIZE(cs
->buffer_hash_table
); ++i
)
182 cs
->buffer_hash_table
[i
] = -1;
184 cs
->hw_ip
= ring_to_hw_ip(ring_type
);
188 static struct radeon_winsys_cs
*
189 radv_amdgpu_cs_create(struct radeon_winsys
*ws
,
190 enum ring_type ring_type
)
192 struct radv_amdgpu_cs
*cs
;
193 uint32_t ib_size
= 20 * 1024 * 4;
194 cs
= calloc(1, sizeof(struct radv_amdgpu_cs
));
198 cs
->ws
= radv_amdgpu_winsys(ws
);
199 radv_amdgpu_init_cs(cs
, ring_type
);
201 if (cs
->ws
->use_ib_bos
) {
202 cs
->ib_buffer
= ws
->buffer_create(ws
, ib_size
, 0,
204 RADEON_FLAG_CPU_ACCESS
|
205 RADEON_FLAG_NO_INTERPROCESS_SHARING
);
206 if (!cs
->ib_buffer
) {
211 cs
->ib_mapped
= ws
->buffer_map(cs
->ib_buffer
);
212 if (!cs
->ib_mapped
) {
213 ws
->buffer_destroy(cs
->ib_buffer
);
218 cs
->ib
.ib_mc_address
= radv_amdgpu_winsys_bo(cs
->ib_buffer
)->base
.va
;
219 cs
->base
.buf
= (uint32_t *)cs
->ib_mapped
;
220 cs
->base
.max_dw
= ib_size
/ 4 - 4;
221 cs
->ib_size_ptr
= &cs
->ib
.size
;
224 ws
->cs_add_buffer(&cs
->base
, cs
->ib_buffer
, 8);
226 cs
->base
.buf
= malloc(16384);
227 cs
->base
.max_dw
= 4096;
237 static void radv_amdgpu_cs_grow(struct radeon_winsys_cs
*_cs
, size_t min_size
)
239 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(_cs
);
246 if (!cs
->ws
->use_ib_bos
) {
247 const uint64_t limit_dws
= 0xffff8;
248 uint64_t ib_dws
= MAX2(cs
->base
.cdw
+ min_size
,
249 MIN2(cs
->base
.max_dw
* 2, limit_dws
));
251 /* The total ib size cannot exceed limit_dws dwords. */
252 if (ib_dws
> limit_dws
)
259 uint32_t *new_buf
= realloc(cs
->base
.buf
, ib_dws
* 4);
261 cs
->base
.buf
= new_buf
;
262 cs
->base
.max_dw
= ib_dws
;
270 uint64_t ib_size
= MAX2(min_size
* 4 + 16, cs
->base
.max_dw
* 4 * 2);
272 /* max that fits in the chain size field. */
273 ib_size
= MIN2(ib_size
, 0xfffff);
275 while (!cs
->base
.cdw
|| (cs
->base
.cdw
& 7) != 4)
276 cs
->base
.buf
[cs
->base
.cdw
++] = 0xffff1000;
278 *cs
->ib_size_ptr
|= cs
->base
.cdw
+ 4;
280 if (cs
->num_old_ib_buffers
== cs
->max_num_old_ib_buffers
) {
281 cs
->max_num_old_ib_buffers
= MAX2(1, cs
->max_num_old_ib_buffers
* 2);
282 cs
->old_ib_buffers
= realloc(cs
->old_ib_buffers
,
283 cs
->max_num_old_ib_buffers
* sizeof(void*));
286 cs
->old_ib_buffers
[cs
->num_old_ib_buffers
++] = cs
->ib_buffer
;
288 cs
->ib_buffer
= cs
->ws
->base
.buffer_create(&cs
->ws
->base
, ib_size
, 0,
290 RADEON_FLAG_CPU_ACCESS
|
291 RADEON_FLAG_NO_INTERPROCESS_SHARING
);
293 if (!cs
->ib_buffer
) {
296 cs
->ib_buffer
= cs
->old_ib_buffers
[--cs
->num_old_ib_buffers
];
299 cs
->ib_mapped
= cs
->ws
->base
.buffer_map(cs
->ib_buffer
);
300 if (!cs
->ib_mapped
) {
301 cs
->ws
->base
.buffer_destroy(cs
->ib_buffer
);
304 cs
->ib_buffer
= cs
->old_ib_buffers
[--cs
->num_old_ib_buffers
];
307 cs
->ws
->base
.cs_add_buffer(&cs
->base
, cs
->ib_buffer
, 8);
309 cs
->base
.buf
[cs
->base
.cdw
++] = PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0);
310 cs
->base
.buf
[cs
->base
.cdw
++] = radv_amdgpu_winsys_bo(cs
->ib_buffer
)->base
.va
;
311 cs
->base
.buf
[cs
->base
.cdw
++] = radv_amdgpu_winsys_bo(cs
->ib_buffer
)->base
.va
>> 32;
312 cs
->ib_size_ptr
= cs
->base
.buf
+ cs
->base
.cdw
;
313 cs
->base
.buf
[cs
->base
.cdw
++] = S_3F2_CHAIN(1) | S_3F2_VALID(1);
315 cs
->base
.buf
= (uint32_t *)cs
->ib_mapped
;
317 cs
->base
.max_dw
= ib_size
/ 4 - 4;
321 static bool radv_amdgpu_cs_finalize(struct radeon_winsys_cs
*_cs
)
323 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(_cs
);
325 if (cs
->ws
->use_ib_bos
) {
326 while (!cs
->base
.cdw
|| (cs
->base
.cdw
& 7) != 0)
327 cs
->base
.buf
[cs
->base
.cdw
++] = 0xffff1000;
329 *cs
->ib_size_ptr
|= cs
->base
.cdw
;
331 cs
->is_chained
= false;
337 static void radv_amdgpu_cs_reset(struct radeon_winsys_cs
*_cs
)
339 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(_cs
);
343 for (unsigned i
= 0; i
< cs
->num_buffers
; ++i
) {
344 unsigned hash
= ((uintptr_t)cs
->handles
[i
] >> 6) &
345 (ARRAY_SIZE(cs
->buffer_hash_table
) - 1);
346 cs
->buffer_hash_table
[hash
] = -1;
349 for (unsigned i
= 0; i
< cs
->num_virtual_buffers
; ++i
) {
350 unsigned hash
= ((uintptr_t)cs
->virtual_buffers
[i
] >> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE
- 1);
351 cs
->virtual_buffer_hash_table
[hash
] = -1;
355 cs
->num_virtual_buffers
= 0;
357 if (cs
->ws
->use_ib_bos
) {
358 cs
->ws
->base
.cs_add_buffer(&cs
->base
, cs
->ib_buffer
, 8);
360 for (unsigned i
= 0; i
< cs
->num_old_ib_buffers
; ++i
)
361 cs
->ws
->base
.buffer_destroy(cs
->old_ib_buffers
[i
]);
363 cs
->num_old_ib_buffers
= 0;
364 cs
->ib
.ib_mc_address
= radv_amdgpu_winsys_bo(cs
->ib_buffer
)->base
.va
;
365 cs
->ib_size_ptr
= &cs
->ib
.size
;
370 static int radv_amdgpu_cs_find_buffer(struct radv_amdgpu_cs
*cs
,
373 unsigned hash
= ((uintptr_t)bo
>> 6) & (ARRAY_SIZE(cs
->buffer_hash_table
) - 1);
374 int index
= cs
->buffer_hash_table
[hash
];
379 if (cs
->handles
[index
] == bo
)
382 for (unsigned i
= 0; i
< cs
->num_buffers
; ++i
) {
383 if (cs
->handles
[i
] == bo
) {
384 cs
->buffer_hash_table
[hash
] = i
;
392 static void radv_amdgpu_cs_add_buffer_internal(struct radv_amdgpu_cs
*cs
,
397 int index
= radv_amdgpu_cs_find_buffer(cs
, bo
);
400 cs
->priorities
[index
] = MAX2(cs
->priorities
[index
], priority
);
404 if (cs
->num_buffers
== cs
->max_num_buffers
) {
405 unsigned new_count
= MAX2(1, cs
->max_num_buffers
* 2);
406 cs
->handles
= realloc(cs
->handles
, new_count
* sizeof(amdgpu_bo_handle
));
407 cs
->priorities
= realloc(cs
->priorities
, new_count
* sizeof(uint8_t));
408 cs
->max_num_buffers
= new_count
;
411 cs
->handles
[cs
->num_buffers
] = bo
;
412 cs
->priorities
[cs
->num_buffers
] = priority
;
414 hash
= ((uintptr_t)bo
>> 6) & (ARRAY_SIZE(cs
->buffer_hash_table
) - 1);
415 cs
->buffer_hash_table
[hash
] = cs
->num_buffers
;
420 static void radv_amdgpu_cs_add_virtual_buffer(struct radeon_winsys_cs
*_cs
,
421 struct radeon_winsys_bo
*bo
,
424 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(_cs
);
425 unsigned hash
= ((uintptr_t)bo
>> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE
- 1);
428 if (!cs
->virtual_buffer_hash_table
) {
429 cs
->virtual_buffer_hash_table
= malloc(VIRTUAL_BUFFER_HASH_TABLE_SIZE
* sizeof(int));
430 for (int i
= 0; i
< VIRTUAL_BUFFER_HASH_TABLE_SIZE
; ++i
)
431 cs
->virtual_buffer_hash_table
[i
] = -1;
434 if (cs
->virtual_buffer_hash_table
[hash
] >= 0) {
435 int idx
= cs
->virtual_buffer_hash_table
[hash
];
436 if (cs
->virtual_buffers
[idx
] == bo
) {
437 cs
->virtual_buffer_priorities
[idx
] = MAX2(cs
->virtual_buffer_priorities
[idx
], priority
);
440 for (unsigned i
= 0; i
< cs
->num_virtual_buffers
; ++i
) {
441 if (cs
->virtual_buffers
[i
] == bo
) {
442 cs
->virtual_buffer_priorities
[i
] = MAX2(cs
->virtual_buffer_priorities
[i
], priority
);
443 cs
->virtual_buffer_hash_table
[hash
] = i
;
449 if(cs
->max_num_virtual_buffers
<= cs
->num_virtual_buffers
) {
450 cs
->max_num_virtual_buffers
= MAX2(2, cs
->max_num_virtual_buffers
* 2);
451 cs
->virtual_buffers
= realloc(cs
->virtual_buffers
, sizeof(struct radv_amdgpu_virtual_virtual_buffer
*) * cs
->max_num_virtual_buffers
);
452 cs
->virtual_buffer_priorities
= realloc(cs
->virtual_buffer_priorities
, sizeof(uint8_t) * cs
->max_num_virtual_buffers
);
455 cs
->virtual_buffers
[cs
->num_virtual_buffers
] = bo
;
456 cs
->virtual_buffer_priorities
[cs
->num_virtual_buffers
] = priority
;
458 cs
->virtual_buffer_hash_table
[hash
] = cs
->num_virtual_buffers
;
459 ++cs
->num_virtual_buffers
;
463 static void radv_amdgpu_cs_add_buffer(struct radeon_winsys_cs
*_cs
,
464 struct radeon_winsys_bo
*_bo
,
467 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(_cs
);
468 struct radv_amdgpu_winsys_bo
*bo
= radv_amdgpu_winsys_bo(_bo
);
470 if (bo
->is_virtual
) {
471 radv_amdgpu_cs_add_virtual_buffer(_cs
, _bo
, priority
);
475 if (bo
->base
.is_local
)
478 radv_amdgpu_cs_add_buffer_internal(cs
, bo
->bo
, priority
);
481 static void radv_amdgpu_cs_execute_secondary(struct radeon_winsys_cs
*_parent
,
482 struct radeon_winsys_cs
*_child
)
484 struct radv_amdgpu_cs
*parent
= radv_amdgpu_cs(_parent
);
485 struct radv_amdgpu_cs
*child
= radv_amdgpu_cs(_child
);
487 for (unsigned i
= 0; i
< child
->num_buffers
; ++i
) {
488 radv_amdgpu_cs_add_buffer_internal(parent
, child
->handles
[i
],
489 child
->priorities
[i
]);
492 for (unsigned i
= 0; i
< child
->num_virtual_buffers
; ++i
) {
493 radv_amdgpu_cs_add_buffer(&parent
->base
, child
->virtual_buffers
[i
],
494 child
->virtual_buffer_priorities
[i
]);
497 if (parent
->ws
->use_ib_bos
) {
498 if (parent
->base
.cdw
+ 4 > parent
->base
.max_dw
)
499 radv_amdgpu_cs_grow(&parent
->base
, 4);
501 parent
->base
.buf
[parent
->base
.cdw
++] = PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0);
502 parent
->base
.buf
[parent
->base
.cdw
++] = child
->ib
.ib_mc_address
;
503 parent
->base
.buf
[parent
->base
.cdw
++] = child
->ib
.ib_mc_address
>> 32;
504 parent
->base
.buf
[parent
->base
.cdw
++] = child
->ib
.size
;
506 if (parent
->base
.cdw
+ child
->base
.cdw
> parent
->base
.max_dw
)
507 radv_amdgpu_cs_grow(&parent
->base
, child
->base
.cdw
);
509 memcpy(parent
->base
.buf
+ parent
->base
.cdw
, child
->base
.buf
, 4 * child
->base
.cdw
);
510 parent
->base
.cdw
+= child
->base
.cdw
;
514 static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys
*ws
,
515 struct radeon_winsys_cs
**cs_array
,
517 struct radv_amdgpu_winsys_bo
*extra_bo
,
518 struct radeon_winsys_cs
*extra_cs
,
519 amdgpu_bo_list_handle
*bo_list
)
523 if (ws
->debug_all_bos
) {
524 struct radv_amdgpu_winsys_bo
*bo
;
525 amdgpu_bo_handle
*handles
;
528 pthread_mutex_lock(&ws
->global_bo_list_lock
);
530 handles
= malloc(sizeof(handles
[0]) * ws
->num_buffers
);
532 pthread_mutex_unlock(&ws
->global_bo_list_lock
);
536 LIST_FOR_EACH_ENTRY(bo
, &ws
->global_bo_list
, global_list_item
) {
537 assert(num
< ws
->num_buffers
);
538 handles
[num
++] = bo
->bo
;
541 r
= amdgpu_bo_list_create(ws
->dev
, ws
->num_buffers
,
545 pthread_mutex_unlock(&ws
->global_bo_list_lock
);
546 } else if (count
== 1 && !extra_bo
&& !extra_cs
&&
547 !radv_amdgpu_cs(cs_array
[0])->num_virtual_buffers
) {
548 struct radv_amdgpu_cs
*cs
= (struct radv_amdgpu_cs
*)cs_array
[0];
549 if (cs
->num_buffers
== 0) {
553 r
= amdgpu_bo_list_create(ws
->dev
, cs
->num_buffers
, cs
->handles
,
554 cs
->priorities
, bo_list
);
556 unsigned total_buffer_count
= !!extra_bo
;
557 unsigned unique_bo_count
= !!extra_bo
;
558 for (unsigned i
= 0; i
< count
; ++i
) {
559 struct radv_amdgpu_cs
*cs
= (struct radv_amdgpu_cs
*)cs_array
[i
];
560 total_buffer_count
+= cs
->num_buffers
;
561 for (unsigned j
= 0; j
< cs
->num_virtual_buffers
; ++j
)
562 total_buffer_count
+= radv_amdgpu_winsys_bo(cs
->virtual_buffers
[j
])->bo_count
;
566 total_buffer_count
+= ((struct radv_amdgpu_cs
*)extra_cs
)->num_buffers
;
568 if (total_buffer_count
== 0) {
572 amdgpu_bo_handle
*handles
= malloc(sizeof(amdgpu_bo_handle
) * total_buffer_count
);
573 uint8_t *priorities
= malloc(sizeof(uint8_t) * total_buffer_count
);
574 if (!handles
|| !priorities
) {
581 handles
[0] = extra_bo
->bo
;
585 for (unsigned i
= 0; i
< count
+ !!extra_cs
; ++i
) {
586 struct radv_amdgpu_cs
*cs
;
589 cs
= (struct radv_amdgpu_cs
*)extra_cs
;
591 cs
= (struct radv_amdgpu_cs
*)cs_array
[i
];
593 if (!cs
->num_buffers
)
596 if (unique_bo_count
== 0) {
597 memcpy(handles
, cs
->handles
, cs
->num_buffers
* sizeof(amdgpu_bo_handle
));
598 memcpy(priorities
, cs
->priorities
, cs
->num_buffers
* sizeof(uint8_t));
599 unique_bo_count
= cs
->num_buffers
;
602 int unique_bo_so_far
= unique_bo_count
;
603 for (unsigned j
= 0; j
< cs
->num_buffers
; ++j
) {
605 for (unsigned k
= 0; k
< unique_bo_so_far
; ++k
) {
606 if (handles
[k
] == cs
->handles
[j
]) {
608 priorities
[k
] = MAX2(priorities
[k
],
614 handles
[unique_bo_count
] = cs
->handles
[j
];
615 priorities
[unique_bo_count
] = cs
->priorities
[j
];
619 for (unsigned j
= 0; j
< cs
->num_virtual_buffers
; ++j
) {
620 struct radv_amdgpu_winsys_bo
*virtual_bo
= radv_amdgpu_winsys_bo(cs
->virtual_buffers
[j
]);
621 for(unsigned k
= 0; k
< virtual_bo
->bo_count
; ++k
) {
622 struct radv_amdgpu_winsys_bo
*bo
= virtual_bo
->bos
[k
];
624 for (unsigned m
= 0; m
< unique_bo_count
; ++m
) {
625 if (handles
[m
] == bo
->bo
) {
627 priorities
[m
] = MAX2(priorities
[m
],
628 cs
->virtual_buffer_priorities
[j
]);
633 handles
[unique_bo_count
] = bo
->bo
;
634 priorities
[unique_bo_count
] = cs
->virtual_buffer_priorities
[j
];
641 if (unique_bo_count
> 0) {
642 r
= amdgpu_bo_list_create(ws
->dev
, unique_bo_count
, handles
,
643 priorities
, bo_list
);
655 static struct amdgpu_cs_fence_info
radv_set_cs_fence(struct radv_amdgpu_ctx
*ctx
, int ip_type
, int ring
)
657 struct amdgpu_cs_fence_info ret
= {0};
658 if (ctx
->fence_map
) {
659 ret
.handle
= radv_amdgpu_winsys_bo(ctx
->fence_bo
)->bo
;
660 ret
.offset
= (ip_type
* MAX_RINGS_PER_TYPE
+ ring
) * sizeof(uint64_t);
665 static void radv_assign_last_submit(struct radv_amdgpu_ctx
*ctx
,
666 struct amdgpu_cs_request
*request
)
668 radv_amdgpu_request_to_fence(ctx
,
669 &ctx
->last_submission
[request
->ip_type
][request
->ring
],
673 static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx
*_ctx
,
675 struct radv_winsys_sem_info
*sem_info
,
676 struct radeon_winsys_cs
**cs_array
,
678 struct radeon_winsys_cs
*initial_preamble_cs
,
679 struct radeon_winsys_cs
*continue_preamble_cs
,
680 struct radeon_winsys_fence
*_fence
)
683 struct radv_amdgpu_ctx
*ctx
= radv_amdgpu_ctx(_ctx
);
684 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
685 struct radv_amdgpu_cs
*cs0
= radv_amdgpu_cs(cs_array
[0]);
686 amdgpu_bo_list_handle bo_list
;
687 struct amdgpu_cs_request request
= {0};
688 struct amdgpu_cs_ib_info ibs
[2];
690 for (unsigned i
= cs_count
; i
--;) {
691 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(cs_array
[i
]);
693 if (cs
->is_chained
) {
694 *cs
->ib_size_ptr
-= 4;
695 cs
->is_chained
= false;
698 if (i
+ 1 < cs_count
) {
699 struct radv_amdgpu_cs
*next
= radv_amdgpu_cs(cs_array
[i
+ 1]);
700 assert(cs
->base
.cdw
+ 4 <= cs
->base
.max_dw
);
702 cs
->is_chained
= true;
703 *cs
->ib_size_ptr
+= 4;
705 cs
->base
.buf
[cs
->base
.cdw
+ 0] = PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0);
706 cs
->base
.buf
[cs
->base
.cdw
+ 1] = next
->ib
.ib_mc_address
;
707 cs
->base
.buf
[cs
->base
.cdw
+ 2] = next
->ib
.ib_mc_address
>> 32;
708 cs
->base
.buf
[cs
->base
.cdw
+ 3] = S_3F2_CHAIN(1) | S_3F2_VALID(1) | next
->ib
.size
;
712 r
= radv_amdgpu_create_bo_list(cs0
->ws
, cs_array
, cs_count
, NULL
, initial_preamble_cs
, &bo_list
);
714 fprintf(stderr
, "amdgpu: buffer list creation failed for the "
715 "chained submission(%d)\n", r
);
719 request
.ip_type
= cs0
->hw_ip
;
720 request
.ring
= queue_idx
;
721 request
.number_of_ibs
= 1;
722 request
.ibs
= &cs0
->ib
;
723 request
.resources
= bo_list
;
724 request
.fence_info
= radv_set_cs_fence(ctx
, cs0
->hw_ip
, queue_idx
);
726 if (initial_preamble_cs
) {
728 request
.number_of_ibs
= 2;
730 ibs
[0] = ((struct radv_amdgpu_cs
*)initial_preamble_cs
)->ib
;
733 r
= radv_amdgpu_cs_submit(ctx
, &request
, sem_info
);
736 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
738 fprintf(stderr
, "amdgpu: The CS has been rejected, "
739 "see dmesg for more information.\n");
743 amdgpu_bo_list_destroy(bo_list
);
746 radv_amdgpu_request_to_fence(ctx
, fence
, &request
);
748 radv_assign_last_submit(ctx
, &request
);
753 static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx
*_ctx
,
755 struct radv_winsys_sem_info
*sem_info
,
756 struct radeon_winsys_cs
**cs_array
,
758 struct radeon_winsys_cs
*initial_preamble_cs
,
759 struct radeon_winsys_cs
*continue_preamble_cs
,
760 struct radeon_winsys_fence
*_fence
)
763 struct radv_amdgpu_ctx
*ctx
= radv_amdgpu_ctx(_ctx
);
764 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
765 amdgpu_bo_list_handle bo_list
;
766 struct amdgpu_cs_request request
;
767 bool emit_signal_sem
= sem_info
->cs_emit_signal
;
770 for (unsigned i
= 0; i
< cs_count
;) {
771 struct radv_amdgpu_cs
*cs0
= radv_amdgpu_cs(cs_array
[i
]);
772 struct amdgpu_cs_ib_info ibs
[AMDGPU_CS_MAX_IBS_PER_SUBMIT
];
773 struct radeon_winsys_cs
*preamble_cs
= i
? continue_preamble_cs
: initial_preamble_cs
;
774 unsigned cnt
= MIN2(AMDGPU_CS_MAX_IBS_PER_SUBMIT
- !!preamble_cs
,
777 memset(&request
, 0, sizeof(request
));
779 r
= radv_amdgpu_create_bo_list(cs0
->ws
, &cs_array
[i
], cnt
, NULL
,
780 preamble_cs
, &bo_list
);
782 fprintf(stderr
, "amdgpu: buffer list creation failed "
783 "for the fallback submission (%d)\n", r
);
787 request
.ip_type
= cs0
->hw_ip
;
788 request
.ring
= queue_idx
;
789 request
.resources
= bo_list
;
790 request
.number_of_ibs
= cnt
+ !!preamble_cs
;
792 request
.fence_info
= radv_set_cs_fence(ctx
, cs0
->hw_ip
, queue_idx
);
795 ibs
[0] = radv_amdgpu_cs(preamble_cs
)->ib
;
798 for (unsigned j
= 0; j
< cnt
; ++j
) {
799 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(cs_array
[i
+ j
]);
800 ibs
[j
+ !!preamble_cs
] = cs
->ib
;
802 if (cs
->is_chained
) {
803 *cs
->ib_size_ptr
-= 4;
804 cs
->is_chained
= false;
808 sem_info
->cs_emit_signal
= (i
== cs_count
- cnt
) ? emit_signal_sem
: false;
809 r
= radv_amdgpu_cs_submit(ctx
, &request
, sem_info
);
812 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
814 fprintf(stderr
, "amdgpu: The CS has been rejected, "
815 "see dmesg for more information.\n");
819 amdgpu_bo_list_destroy(bo_list
);
827 radv_amdgpu_request_to_fence(ctx
, fence
, &request
);
829 radv_assign_last_submit(ctx
, &request
);
834 static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx
*_ctx
,
836 struct radv_winsys_sem_info
*sem_info
,
837 struct radeon_winsys_cs
**cs_array
,
839 struct radeon_winsys_cs
*initial_preamble_cs
,
840 struct radeon_winsys_cs
*continue_preamble_cs
,
841 struct radeon_winsys_fence
*_fence
)
844 struct radv_amdgpu_ctx
*ctx
= radv_amdgpu_ctx(_ctx
);
845 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
846 struct radv_amdgpu_cs
*cs0
= radv_amdgpu_cs(cs_array
[0]);
847 struct radeon_winsys
*ws
= (struct radeon_winsys
*)cs0
->ws
;
848 amdgpu_bo_list_handle bo_list
;
849 struct amdgpu_cs_request request
;
850 uint32_t pad_word
= 0xffff1000U
;
851 bool emit_signal_sem
= sem_info
->cs_emit_signal
;
853 if (radv_amdgpu_winsys(ws
)->info
.chip_class
== SI
)
854 pad_word
= 0x80000000;
858 for (unsigned i
= 0; i
< cs_count
;) {
859 struct amdgpu_cs_ib_info ib
= {0};
860 struct radeon_winsys_bo
*bo
= NULL
;
861 struct radeon_winsys_cs
*preamble_cs
= i
? continue_preamble_cs
: initial_preamble_cs
;
865 unsigned pad_words
= 0;
867 size
+= preamble_cs
->cdw
;
869 while (i
+ cnt
< cs_count
&& 0xffff8 - size
>= radv_amdgpu_cs(cs_array
[i
+ cnt
])->base
.cdw
) {
870 size
+= radv_amdgpu_cs(cs_array
[i
+ cnt
])->base
.cdw
;
874 while(!size
|| (size
& 7)) {
880 bo
= ws
->buffer_create(ws
, 4 * size
, 4096, RADEON_DOMAIN_GTT
, RADEON_FLAG_CPU_ACCESS
|RADEON_FLAG_NO_INTERPROCESS_SHARING
);
881 ptr
= ws
->buffer_map(bo
);
884 memcpy(ptr
, preamble_cs
->buf
, preamble_cs
->cdw
* 4);
885 ptr
+= preamble_cs
->cdw
;
888 for (unsigned j
= 0; j
< cnt
; ++j
) {
889 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(cs_array
[i
+ j
]);
890 memcpy(ptr
, cs
->base
.buf
, 4 * cs
->base
.cdw
);
895 for (unsigned j
= 0; j
< pad_words
; ++j
)
898 memset(&request
, 0, sizeof(request
));
901 r
= radv_amdgpu_create_bo_list(cs0
->ws
, &cs_array
[i
], cnt
,
902 (struct radv_amdgpu_winsys_bo
*)bo
,
903 preamble_cs
, &bo_list
);
905 fprintf(stderr
, "amdgpu: buffer list creation failed "
906 "for the sysmem submission (%d)\n", r
);
911 ib
.ib_mc_address
= radv_buffer_get_va(bo
);
913 request
.ip_type
= cs0
->hw_ip
;
914 request
.ring
= queue_idx
;
915 request
.resources
= bo_list
;
916 request
.number_of_ibs
= 1;
918 request
.fence_info
= radv_set_cs_fence(ctx
, cs0
->hw_ip
, queue_idx
);
920 sem_info
->cs_emit_signal
= (i
== cs_count
- cnt
) ? emit_signal_sem
: false;
921 r
= radv_amdgpu_cs_submit(ctx
, &request
, sem_info
);
924 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
926 fprintf(stderr
, "amdgpu: The CS has been rejected, "
927 "see dmesg for more information.\n");
931 amdgpu_bo_list_destroy(bo_list
);
933 ws
->buffer_destroy(bo
);
940 radv_amdgpu_request_to_fence(ctx
, fence
, &request
);
942 radv_assign_last_submit(ctx
, &request
);
947 static int radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx
*_ctx
,
949 struct radeon_winsys_cs
**cs_array
,
951 struct radeon_winsys_cs
*initial_preamble_cs
,
952 struct radeon_winsys_cs
*continue_preamble_cs
,
953 struct radv_winsys_sem_info
*sem_info
,
955 struct radeon_winsys_fence
*_fence
)
957 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(cs_array
[0]);
958 struct radv_amdgpu_ctx
*ctx
= radv_amdgpu_ctx(_ctx
);
962 if (!cs
->ws
->use_ib_bos
) {
963 ret
= radv_amdgpu_winsys_cs_submit_sysmem(_ctx
, queue_idx
, sem_info
, cs_array
,
964 cs_count
, initial_preamble_cs
, continue_preamble_cs
, _fence
);
965 } else if (can_patch
&& cs_count
> AMDGPU_CS_MAX_IBS_PER_SUBMIT
&& cs
->ws
->batchchain
) {
966 ret
= radv_amdgpu_winsys_cs_submit_chained(_ctx
, queue_idx
, sem_info
, cs_array
,
967 cs_count
, initial_preamble_cs
, continue_preamble_cs
, _fence
);
969 ret
= radv_amdgpu_winsys_cs_submit_fallback(_ctx
, queue_idx
, sem_info
, cs_array
,
970 cs_count
, initial_preamble_cs
, continue_preamble_cs
, _fence
);
973 radv_amdgpu_signal_sems(ctx
, cs
->hw_ip
, queue_idx
, sem_info
);
977 static void *radv_amdgpu_winsys_get_cpu_addr(void *_cs
, uint64_t addr
)
979 struct radv_amdgpu_cs
*cs
= (struct radv_amdgpu_cs
*)_cs
;
984 for (unsigned i
= 0; i
<= cs
->num_old_ib_buffers
; ++i
) {
985 struct radv_amdgpu_winsys_bo
*bo
;
987 bo
= (struct radv_amdgpu_winsys_bo
*)
988 (i
== cs
->num_old_ib_buffers
? cs
->ib_buffer
: cs
->old_ib_buffers
[i
]);
989 if (addr
>= bo
->base
.va
&& addr
- bo
->base
.va
< bo
->size
) {
990 if (amdgpu_bo_cpu_map(bo
->bo
, &ret
) == 0)
991 return (char *)ret
+ (addr
- bo
->base
.va
);
994 if(cs
->ws
->debug_all_bos
) {
995 pthread_mutex_lock(&cs
->ws
->global_bo_list_lock
);
996 list_for_each_entry(struct radv_amdgpu_winsys_bo
, bo
,
997 &cs
->ws
->global_bo_list
, global_list_item
) {
998 if (addr
>= bo
->base
.va
&& addr
- bo
->base
.va
< bo
->size
) {
999 if (amdgpu_bo_cpu_map(bo
->bo
, &ret
) == 0) {
1000 pthread_mutex_unlock(&cs
->ws
->global_bo_list_lock
);
1001 return (char *)ret
+ (addr
- bo
->base
.va
);
1005 pthread_mutex_unlock(&cs
->ws
->global_bo_list_lock
);
1010 static void radv_amdgpu_winsys_cs_dump(struct radeon_winsys_cs
*_cs
,
1012 const int *trace_ids
, int trace_id_count
)
1014 struct radv_amdgpu_cs
*cs
= (struct radv_amdgpu_cs
*)_cs
;
1015 void *ib
= cs
->base
.buf
;
1016 int num_dw
= cs
->base
.cdw
;
1018 if (cs
->ws
->use_ib_bos
) {
1019 ib
= radv_amdgpu_winsys_get_cpu_addr(cs
, cs
->ib
.ib_mc_address
);
1020 num_dw
= cs
->ib
.size
;
1023 ac_parse_ib(file
, ib
, num_dw
, trace_ids
, trace_id_count
, "main IB",
1024 cs
->ws
->info
.chip_class
, radv_amdgpu_winsys_get_cpu_addr
, cs
);
1027 static uint32_t radv_to_amdgpu_priority(enum radeon_ctx_priority radv_priority
)
1029 switch (radv_priority
) {
1030 case RADEON_CTX_PRIORITY_REALTIME
:
1031 return AMDGPU_CTX_PRIORITY_VERY_HIGH
;
1032 case RADEON_CTX_PRIORITY_HIGH
:
1033 return AMDGPU_CTX_PRIORITY_HIGH
;
1034 case RADEON_CTX_PRIORITY_MEDIUM
:
1035 return AMDGPU_CTX_PRIORITY_NORMAL
;
1036 case RADEON_CTX_PRIORITY_LOW
:
1037 return AMDGPU_CTX_PRIORITY_LOW
;
1039 unreachable("Invalid context priority");
1043 static struct radeon_winsys_ctx
*radv_amdgpu_ctx_create(struct radeon_winsys
*_ws
,
1044 enum radeon_ctx_priority priority
)
1046 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1047 struct radv_amdgpu_ctx
*ctx
= CALLOC_STRUCT(radv_amdgpu_ctx
);
1048 uint32_t amdgpu_priority
= radv_to_amdgpu_priority(priority
);
1054 r
= amdgpu_cs_ctx_create2(ws
->dev
, amdgpu_priority
, &ctx
->ctx
);
1056 fprintf(stderr
, "amdgpu: radv_amdgpu_cs_ctx_create2 failed. (%i)\n", r
);
1061 assert(AMDGPU_HW_IP_NUM
* MAX_RINGS_PER_TYPE
* sizeof(uint64_t) <= 4096);
1062 ctx
->fence_bo
= ws
->base
.buffer_create(&ws
->base
, 4096, 8,
1064 RADEON_FLAG_CPU_ACCESS
|
1065 RADEON_FLAG_NO_INTERPROCESS_SHARING
);
1067 ctx
->fence_map
= (uint64_t*)ws
->base
.buffer_map(ctx
->fence_bo
);
1069 memset(ctx
->fence_map
, 0, 4096);
1070 return (struct radeon_winsys_ctx
*)ctx
;
1076 static void radv_amdgpu_ctx_destroy(struct radeon_winsys_ctx
*rwctx
)
1078 struct radv_amdgpu_ctx
*ctx
= (struct radv_amdgpu_ctx
*)rwctx
;
1079 ctx
->ws
->base
.buffer_destroy(ctx
->fence_bo
);
1080 amdgpu_cs_ctx_free(ctx
->ctx
);
1084 static bool radv_amdgpu_ctx_wait_idle(struct radeon_winsys_ctx
*rwctx
,
1085 enum ring_type ring_type
, int ring_index
)
1087 struct radv_amdgpu_ctx
*ctx
= (struct radv_amdgpu_ctx
*)rwctx
;
1088 int ip_type
= ring_to_hw_ip(ring_type
);
1090 if (ctx
->last_submission
[ip_type
][ring_index
].fence
.fence
) {
1092 int ret
= amdgpu_cs_query_fence_status(&ctx
->last_submission
[ip_type
][ring_index
].fence
,
1093 1000000000ull, 0, &expired
);
1095 if (ret
|| !expired
)
1102 static struct radeon_winsys_sem
*radv_amdgpu_create_sem(struct radeon_winsys
*_ws
)
1104 struct amdgpu_cs_fence
*sem
= CALLOC_STRUCT(amdgpu_cs_fence
);
1108 return (struct radeon_winsys_sem
*)sem
;
1111 static void radv_amdgpu_destroy_sem(struct radeon_winsys_sem
*_sem
)
1113 struct amdgpu_cs_fence
*sem
= (struct amdgpu_cs_fence
*)_sem
;
1117 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx
*ctx
,
1120 struct radv_winsys_sem_info
*sem_info
)
1122 for (unsigned i
= 0; i
< sem_info
->signal
.sem_count
; i
++) {
1123 struct amdgpu_cs_fence
*sem
= (struct amdgpu_cs_fence
*)(sem_info
->signal
.sem
)[i
];
1128 *sem
= ctx
->last_submission
[ip_type
][ring
].fence
;
1133 static struct drm_amdgpu_cs_chunk_sem
*radv_amdgpu_cs_alloc_syncobj_chunk(struct radv_winsys_sem_counts
*counts
,
1134 struct drm_amdgpu_cs_chunk
*chunk
, int chunk_id
)
1136 struct drm_amdgpu_cs_chunk_sem
*syncobj
= malloc(sizeof(struct drm_amdgpu_cs_chunk_sem
) * counts
->syncobj_count
);
1140 for (unsigned i
= 0; i
< counts
->syncobj_count
; i
++) {
1141 struct drm_amdgpu_cs_chunk_sem
*sem
= &syncobj
[i
];
1142 sem
->handle
= counts
->syncobj
[i
];
1145 chunk
->chunk_id
= chunk_id
;
1146 chunk
->length_dw
= sizeof(struct drm_amdgpu_cs_chunk_sem
) / 4 * counts
->syncobj_count
;
1147 chunk
->chunk_data
= (uint64_t)(uintptr_t)syncobj
;
1151 static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx
*ctx
,
1152 struct amdgpu_cs_request
*request
,
1153 struct radv_winsys_sem_info
*sem_info
)
1159 struct drm_amdgpu_cs_chunk
*chunks
;
1160 struct drm_amdgpu_cs_chunk_data
*chunk_data
;
1161 struct drm_amdgpu_cs_chunk_dep
*sem_dependencies
= NULL
;
1162 struct drm_amdgpu_cs_chunk_sem
*wait_syncobj
= NULL
, *signal_syncobj
= NULL
;
1164 struct amdgpu_cs_fence
*sem
;
1166 user_fence
= (request
->fence_info
.handle
!= NULL
);
1167 size
= request
->number_of_ibs
+ (user_fence
? 2 : 1) + 3;
1169 chunks
= alloca(sizeof(struct drm_amdgpu_cs_chunk
) * size
);
1171 size
= request
->number_of_ibs
+ (user_fence
? 1 : 0);
1173 chunk_data
= alloca(sizeof(struct drm_amdgpu_cs_chunk_data
) * size
);
1175 num_chunks
= request
->number_of_ibs
;
1176 for (i
= 0; i
< request
->number_of_ibs
; i
++) {
1177 struct amdgpu_cs_ib_info
*ib
;
1178 chunks
[i
].chunk_id
= AMDGPU_CHUNK_ID_IB
;
1179 chunks
[i
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_ib
) / 4;
1180 chunks
[i
].chunk_data
= (uint64_t)(uintptr_t)&chunk_data
[i
];
1182 ib
= &request
->ibs
[i
];
1184 chunk_data
[i
].ib_data
._pad
= 0;
1185 chunk_data
[i
].ib_data
.va_start
= ib
->ib_mc_address
;
1186 chunk_data
[i
].ib_data
.ib_bytes
= ib
->size
* 4;
1187 chunk_data
[i
].ib_data
.ip_type
= request
->ip_type
;
1188 chunk_data
[i
].ib_data
.ip_instance
= request
->ip_instance
;
1189 chunk_data
[i
].ib_data
.ring
= request
->ring
;
1190 chunk_data
[i
].ib_data
.flags
= ib
->flags
;
1196 chunks
[i
].chunk_id
= AMDGPU_CHUNK_ID_FENCE
;
1197 chunks
[i
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_fence
) / 4;
1198 chunks
[i
].chunk_data
= (uint64_t)(uintptr_t)&chunk_data
[i
];
1200 amdgpu_cs_chunk_fence_info_to_data(&request
->fence_info
,
1204 if (sem_info
->wait
.syncobj_count
&& sem_info
->cs_emit_wait
) {
1205 wait_syncobj
= radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info
->wait
,
1206 &chunks
[num_chunks
],
1207 AMDGPU_CHUNK_ID_SYNCOBJ_IN
);
1208 if (!wait_syncobj
) {
1214 if (sem_info
->wait
.sem_count
== 0)
1215 sem_info
->cs_emit_wait
= false;
1219 if (sem_info
->wait
.sem_count
&& sem_info
->cs_emit_wait
) {
1220 sem_dependencies
= malloc(sizeof(struct drm_amdgpu_cs_chunk_dep
) * sem_info
->wait
.sem_count
);
1221 if (!sem_dependencies
) {
1226 for (unsigned j
= 0; j
< sem_info
->wait
.sem_count
; j
++) {
1227 sem
= (struct amdgpu_cs_fence
*)sem_info
->wait
.sem
[j
];
1230 struct drm_amdgpu_cs_chunk_dep
*dep
= &sem_dependencies
[sem_count
++];
1232 amdgpu_cs_chunk_fence_to_dep(sem
, dep
);
1234 sem
->context
= NULL
;
1238 /* dependencies chunk */
1239 chunks
[i
].chunk_id
= AMDGPU_CHUNK_ID_DEPENDENCIES
;
1240 chunks
[i
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_dep
) / 4 * sem_count
;
1241 chunks
[i
].chunk_data
= (uint64_t)(uintptr_t)sem_dependencies
;
1243 sem_info
->cs_emit_wait
= false;
1246 if (sem_info
->signal
.syncobj_count
&& sem_info
->cs_emit_signal
) {
1247 signal_syncobj
= radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info
->signal
,
1248 &chunks
[num_chunks
],
1249 AMDGPU_CHUNK_ID_SYNCOBJ_OUT
);
1250 if (!signal_syncobj
) {
1257 r
= amdgpu_cs_submit_raw(ctx
->ws
->dev
,
1264 free(sem_dependencies
);
1266 free(signal_syncobj
);
1270 static int radv_amdgpu_create_syncobj(struct radeon_winsys
*_ws
,
1273 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1274 return amdgpu_cs_create_syncobj(ws
->dev
, handle
);
1277 static void radv_amdgpu_destroy_syncobj(struct radeon_winsys
*_ws
,
1280 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1281 amdgpu_cs_destroy_syncobj(ws
->dev
, handle
);
1284 static void radv_amdgpu_reset_syncobj(struct radeon_winsys
*_ws
,
1287 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1288 amdgpu_cs_syncobj_reset(ws
->dev
, &handle
, 1);
1291 static void radv_amdgpu_signal_syncobj(struct radeon_winsys
*_ws
,
1294 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1295 amdgpu_cs_syncobj_signal(ws
->dev
, &handle
, 1);
1298 static bool radv_amdgpu_wait_syncobj(struct radeon_winsys
*_ws
,
1299 uint32_t handle
, uint64_t timeout
)
1301 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1304 /* The timeouts are signed, while vulkan timeouts are unsigned. */
1305 timeout
= MIN2(timeout
, INT64_MAX
);
1307 int ret
= amdgpu_cs_syncobj_wait(ws
->dev
, &handle
, 1, timeout
,
1308 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT
|
1309 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL
,
1313 } else if (ret
== -1 && errno
== ETIME
) {
1316 fprintf(stderr
, "amdgpu: radv_amdgpu_wait_syncobj failed!\nerrno: %d\n", errno
);
1321 static int radv_amdgpu_export_syncobj(struct radeon_winsys
*_ws
,
1325 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1327 return amdgpu_cs_export_syncobj(ws
->dev
, syncobj
, fd
);
1330 static int radv_amdgpu_import_syncobj(struct radeon_winsys
*_ws
,
1334 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1336 return amdgpu_cs_import_syncobj(ws
->dev
, fd
, syncobj
);
1339 void radv_amdgpu_cs_init_functions(struct radv_amdgpu_winsys
*ws
)
1341 ws
->base
.ctx_create
= radv_amdgpu_ctx_create
;
1342 ws
->base
.ctx_destroy
= radv_amdgpu_ctx_destroy
;
1343 ws
->base
.ctx_wait_idle
= radv_amdgpu_ctx_wait_idle
;
1344 ws
->base
.cs_create
= radv_amdgpu_cs_create
;
1345 ws
->base
.cs_destroy
= radv_amdgpu_cs_destroy
;
1346 ws
->base
.cs_grow
= radv_amdgpu_cs_grow
;
1347 ws
->base
.cs_finalize
= radv_amdgpu_cs_finalize
;
1348 ws
->base
.cs_reset
= radv_amdgpu_cs_reset
;
1349 ws
->base
.cs_add_buffer
= radv_amdgpu_cs_add_buffer
;
1350 ws
->base
.cs_execute_secondary
= radv_amdgpu_cs_execute_secondary
;
1351 ws
->base
.cs_submit
= radv_amdgpu_winsys_cs_submit
;
1352 ws
->base
.cs_dump
= radv_amdgpu_winsys_cs_dump
;
1353 ws
->base
.create_fence
= radv_amdgpu_create_fence
;
1354 ws
->base
.destroy_fence
= radv_amdgpu_destroy_fence
;
1355 ws
->base
.create_sem
= radv_amdgpu_create_sem
;
1356 ws
->base
.destroy_sem
= radv_amdgpu_destroy_sem
;
1357 ws
->base
.create_syncobj
= radv_amdgpu_create_syncobj
;
1358 ws
->base
.destroy_syncobj
= radv_amdgpu_destroy_syncobj
;
1359 ws
->base
.reset_syncobj
= radv_amdgpu_reset_syncobj
;
1360 ws
->base
.signal_syncobj
= radv_amdgpu_signal_syncobj
;
1361 ws
->base
.wait_syncobj
= radv_amdgpu_wait_syncobj
;
1362 ws
->base
.export_syncobj
= radv_amdgpu_export_syncobj
;
1363 ws
->base
.import_syncobj
= radv_amdgpu_import_syncobj
;
1364 ws
->base
.fence_wait
= radv_amdgpu_fence_wait
;