src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based on amdgpu winsys.
   6  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   7  * Copyright © 2015 Advanced Micro Devices, Inc.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  26  * IN THE SOFTWARE.
  27  */
  28
  29 #include <errno.h>
  30
  31 #include "radv_private.h"
  32 #include "addrlib/addrinterface.h"
  33 #include "util/bitset.h"
  34 #include "radv_amdgpu_winsys.h"
  35 #include "radv_amdgpu_surface.h"
  36 #include "sid.h"
  37
  38 #include "ac_surface.h"
  39
  40 #ifndef NO_ENTRIES
  41 #define NO_ENTRIES 32
  42 #endif
  43
  44 #ifndef NO_MACRO_ENTRIES
  45 #define NO_MACRO_ENTRIES 16
  46 #endif
  47
  48 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
  49 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
  50 #endif
  51
  52 static int radv_amdgpu_surface_sanity(const struct ac_surf_info *surf_info,
  53                                       const struct radeon_surf *surf)
  54 {
  55         unsigned type = RADEON_SURF_GET(surf->flags, TYPE);
  56
  57         if (!(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))
  58                 return -EINVAL;
  59
  60         /* all dimension must be at least 1 ! */
  61         if (!surf_info->width || !surf_info->height || !surf_info->depth ||
  62             !surf_info->array_size)
  63                 return -EINVAL;
  64
  65         if (!surf->blk_w || !surf->blk_h)
  66                 return -EINVAL;
  67
  68         switch (surf_info->samples) {
  69         case 1:
  70         case 2:
  71         case 4:
  72         case 8:
  73                 break;
  74         default:
  75                 return -EINVAL;
  76         }
  77
  78         switch (type) {
  79         case RADEON_SURF_TYPE_1D:
  80                 if (surf_info->height > 1)
  81                         return -EINVAL;
  82                 /* fall through */
  83         case RADEON_SURF_TYPE_2D:
  84         case RADEON_SURF_TYPE_CUBEMAP:
  85                 if (surf_info->depth > 1 || surf_info->array_size > 1)
  86                         return -EINVAL;
  87                 break;
  88         case RADEON_SURF_TYPE_3D:
  89                 if (surf_info->array_size > 1)
  90                         return -EINVAL;
  91                 break;
  92         case RADEON_SURF_TYPE_1D_ARRAY:
  93                 if (surf_info->height > 1)
  94                         return -EINVAL;
  95                 /* fall through */
  96         case RADEON_SURF_TYPE_2D_ARRAY:
  97                 if (surf_info->depth > 1)
  98                         return -EINVAL;
  99                 break;
 100         default:
 101                 return -EINVAL;
 102         }
 103         return 0;
 104 }
 105
 106 static void *ADDR_API radv_allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
 107 {
 108         return malloc(pInput->sizeInBytes);
 109 }
 110
 111 static ADDR_E_RETURNCODE ADDR_API radv_freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
 112 {
 113         free(pInput->pVirtAddr);
 114         return ADDR_OK;
 115 }
 116
 117 ADDR_HANDLE radv_amdgpu_addr_create(struct amdgpu_gpu_info *amdinfo, int family, int rev_id,
 118                                     enum chip_class chip_class)
 119 {
 120         ADDR_CREATE_INPUT addrCreateInput = {0};
 121         ADDR_CREATE_OUTPUT addrCreateOutput = {0};
 122         ADDR_REGISTER_VALUE regValue = {0};
 123         ADDR_CREATE_FLAGS createFlags = {{0}};
 124         ADDR_E_RETURNCODE addrRet;
 125
 126         addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
 127         addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
 128
 129         regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
 130         regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
 131         regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
 132
 133         regValue.backendDisables = amdinfo->backend_disable[0];
 134         regValue.pTileConfig = amdinfo->gb_tile_mode;
 135         regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
 136         if (chip_class == SI) {
 137                 regValue.pMacroTileConfig = NULL;
 138                 regValue.noOfMacroEntries = 0;
 139         } else {
 140                 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
 141                 regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
 142         }
 143
 144         createFlags.value = 0;
 145         createFlags.useTileIndex = 1;
 146
 147         addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
 148         addrCreateInput.chipFamily = family;
 149         addrCreateInput.chipRevision = rev_id;
 150         addrCreateInput.createFlags = createFlags;
 151         addrCreateInput.callbacks.allocSysMem = radv_allocSysMem;
 152         addrCreateInput.callbacks.freeSysMem = radv_freeSysMem;
 153         addrCreateInput.callbacks.debugPrint = 0;
 154         addrCreateInput.regValue = regValue;
 155
 156         addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
 157         if (addrRet != ADDR_OK)
 158                 return NULL;
 159
 160         return addrCreateOutput.hLib;
 161 }
 162
 163 static int radv_compute_level(ADDR_HANDLE addrlib,
 164                               const struct ac_surf_info *surf_info,
 165                               struct radeon_surf *surf, bool is_stencil,
 166                               unsigned level, unsigned type, bool compressed,
 167                               ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
 168                               ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
 169                               ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
 170                               ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut)
 171 {
 172         struct legacy_surf_level *surf_level;
 173         ADDR_E_RETURNCODE ret;
 174
 175         AddrSurfInfoIn->mipLevel = level;
 176         AddrSurfInfoIn->width = u_minify(surf_info->width, level);
 177         AddrSurfInfoIn->height = u_minify(surf_info->height, level);
 178
 179         if (type == RADEON_SURF_TYPE_3D)
 180                 AddrSurfInfoIn->numSlices = u_minify(surf_info->depth, level);
 181         else if (type == RADEON_SURF_TYPE_CUBEMAP)
 182                 AddrSurfInfoIn->numSlices = 6;
 183         else
 184                 AddrSurfInfoIn->numSlices = surf_info->array_size;
 185
 186         if (level > 0) {
 187                 /* Set the base level pitch. This is needed for calculation
 188                  * of non-zero levels. */
 189                 if (is_stencil)
 190                         AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
 191                 else
 192                         AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
 193
 194                 /* Convert blocks to pixels for compressed formats. */
 195                 if (compressed)
 196                         AddrSurfInfoIn->basePitch *= surf->blk_w;
 197         }
 198
 199         ret = AddrComputeSurfaceInfo(addrlib,
 200                                      AddrSurfInfoIn,
 201                                      AddrSurfInfoOut);
 202         if (ret != ADDR_OK)
 203                 return ret;
 204
 205         surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
 206         surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
 207         surf_level->slice_size = AddrSurfInfoOut->sliceSize;
 208         surf_level->nblk_x = AddrSurfInfoOut->pitch;
 209         surf_level->nblk_y = AddrSurfInfoOut->height;
 210
 211         switch (AddrSurfInfoOut->tileMode) {
 212         case ADDR_TM_LINEAR_ALIGNED:
 213                 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
 214                 break;
 215         case ADDR_TM_1D_TILED_THIN1:
 216                 surf_level->mode = RADEON_SURF_MODE_1D;
 217                 break;
 218         case ADDR_TM_2D_TILED_THIN1:
 219                 surf_level->mode = RADEON_SURF_MODE_2D;
 220                 break;
 221         default:
 222                 assert(0);
 223         }
 224
 225         if (is_stencil)
 226                 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
 227         else
 228                 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
 229
 230         surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
 231
 232         /* Clear DCC fields at the beginning. */
 233         surf_level->dcc_offset = 0;
 234
 235         /* The previous level's flag tells us if we can use DCC for this level. */
 236         if (AddrSurfInfoIn->flags.dccCompatible &&
 237             (level == 0 || AddrDccOut->subLvlCompressible)) {
 238                 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
 239                 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
 240                 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
 241                 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
 242                 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
 243
 244                 ret = AddrComputeDccInfo(addrlib,
 245                                          AddrDccIn,
 246                                          AddrDccOut);
 247
 248                 if (ret == ADDR_OK) {
 249                         surf_level->dcc_offset = surf->dcc_size;
 250                         surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
 251                         surf->num_dcc_levels = level + 1;
 252                         surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
 253                         surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
 254                 }
 255         }
 256
 257         if (!is_stencil && AddrSurfInfoIn->flags.depth &&
 258             surf_level->mode == RADEON_SURF_MODE_2D && level == 0) {
 259                 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
 260                 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
 261                 AddrHtileIn.flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
 262                 AddrHtileIn.pitch = AddrSurfInfoOut->pitch;
 263                 AddrHtileIn.height = AddrSurfInfoOut->height;
 264                 AddrHtileIn.numSlices = AddrSurfInfoOut->depth;
 265                 AddrHtileIn.blockWidth = ADDR_HTILE_BLOCKSIZE_8;
 266                 AddrHtileIn.blockHeight = ADDR_HTILE_BLOCKSIZE_8;
 267                 AddrHtileIn.pTileInfo = AddrSurfInfoOut->pTileInfo;
 268                 AddrHtileIn.tileIndex = AddrSurfInfoOut->tileIndex;
 269                 AddrHtileIn.macroModeIndex = AddrSurfInfoOut->macroModeIndex;
 270
 271                 ret = AddrComputeHtileInfo(addrlib,
 272                                            &AddrHtileIn,
 273                                            &AddrHtileOut);
 274
 275                 if (ret == ADDR_OK) {
 276                         surf->htile_size = AddrHtileOut.htileBytes;
 277                         surf->htile_slice_size = AddrHtileOut.sliceSize;
 278                         surf->htile_alignment = AddrHtileOut.baseAlign;
 279                 }
 280         }
 281         return 0;
 282 }
 283
 284 static void radv_set_micro_tile_mode(struct radeon_surf *surf,
 285                                      struct radeon_info *info)
 286 {
 287         uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
 288
 289         if (info->chip_class >= CIK)
 290                 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
 291         else
 292                 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
 293 }
 294
 295 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
 296 {
 297         unsigned index, tileb;
 298
 299         tileb = 8 * 8 * surf->bpe;
 300         tileb = MIN2(surf->u.legacy.tile_split, tileb);
 301
 302         for (index = 0; tileb > 64; index++)
 303                 tileb >>= 1;
 304
 305         assert(index < 16);
 306         return index;
 307 }
 308
 309 static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
 310                                            const struct ac_surf_info *surf_info,
 311                                            struct radeon_surf *surf)
 312 {
 313         struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
 314         unsigned level, mode, type;
 315         bool compressed;
 316         ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
 317         ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
 318         ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
 319         ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
 320         ADDR_TILEINFO AddrTileInfoIn = {0};
 321         ADDR_TILEINFO AddrTileInfoOut = {0};
 322         int r;
 323         uint32_t last_level = surf_info->levels - 1;
 324
 325         r = radv_amdgpu_surface_sanity(surf_info, surf);
 326         if (r)
 327                 return r;
 328
 329         AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
 330         AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
 331         AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
 332         AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
 333         AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
 334
 335         type = RADEON_SURF_GET(surf->flags, TYPE);
 336         mode = RADEON_SURF_GET(surf->flags, MODE);
 337         compressed = surf->blk_w == 4 && surf->blk_h == 4;
 338
 339         /* MSAA and FMASK require 2D tiling. */
 340         if (surf_info->samples > 1 ||
 341             (surf->flags & RADEON_SURF_FMASK))
 342                 mode = RADEON_SURF_MODE_2D;
 343
 344         /* DB doesn't support linear layouts. */
 345         if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
 346             mode < RADEON_SURF_MODE_1D)
 347                 mode = RADEON_SURF_MODE_1D;
 348
 349         /* Set the requested tiling mode. */
 350         switch (mode) {
 351         case RADEON_SURF_MODE_LINEAR_ALIGNED:
 352                 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
 353                 break;
 354         case RADEON_SURF_MODE_1D:
 355                 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
 356                 break;
 357         case RADEON_SURF_MODE_2D:
 358                 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
 359                 break;
 360         default:
 361                 assert(0);
 362         }
 363
 364         /* The format must be set correctly for the allocation of compressed
 365          * textures to work. In other cases, setting the bpp is sufficient. */
 366         if (compressed) {
 367                 switch (surf->bpe) {
 368                 case 8:
 369                         AddrSurfInfoIn.format = ADDR_FMT_BC1;
 370                         break;
 371                 case 16:
 372                         AddrSurfInfoIn.format = ADDR_FMT_BC3;
 373                         break;
 374                 default:
 375                         assert(0);
 376                 }
 377         } else {
 378                 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
 379         }
 380
 381         AddrDccIn.numSamples = AddrSurfInfoIn.numSamples = surf_info->samples;
 382         AddrSurfInfoIn.tileIndex = -1;
 383
 384         /* Set the micro tile type. */
 385         if (surf->flags & RADEON_SURF_SCANOUT)
 386                 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
 387         else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
 388                 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
 389         else
 390                 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
 391
 392         AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
 393         AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
 394         AddrSurfInfoIn.flags.cube = type == RADEON_SURF_TYPE_CUBEMAP;
 395         AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
 396         AddrSurfInfoIn.flags.pow2Pad = last_level > 0;
 397         AddrSurfInfoIn.flags.opt4Space = 1;
 398
 399         /* DCC notes:
 400          * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
 401          *   with samples >= 4.
 402          * - Mipmapped array textures have low performance (discovered by a closed
 403          *   driver team).
 404          */
 405         AddrSurfInfoIn.flags.dccCompatible = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
 406                 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
 407                 !compressed && AddrDccIn.numSamples <= 1 &&
 408                 ((surf_info->array_size == 1 && surf_info->depth == 1) ||
 409                  last_level == 0);
 410
 411         AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
 412         AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
 413
 414         /* noStencil = 0 can result in a depth part that is incompatible with
 415          * mipmapped texturing. So set noStencil = 1 when mipmaps are requested (in
 416          * this case, we may end up setting stencil_adjusted).
 417          *
 418          * TODO: update addrlib to a newer version, remove this, and
 419          * use flags.matchStencilTileCfg = 1 as an alternative fix.
 420          */
 421         if (last_level > 0)
 422                 AddrSurfInfoIn.flags.noStencil = 1;
 423
 424         /* Set preferred macrotile parameters. This is usually required
 425          * for shared resources. This is for 2D tiling only. */
 426         if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
 427             surf->u.legacy.bankw && surf->u.legacy.bankh && surf->u.legacy.mtilea &&
 428             surf->u.legacy.tile_split) {
 429                 /* If any of these parameters are incorrect, the calculation
 430                  * will fail. */
 431                 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
 432                 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
 433                 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
 434                 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
 435                 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
 436                 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
 437                 AddrSurfInfoIn.flags.opt4Space = 0;
 438                 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
 439
 440                 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
 441                  * the tile index, because we are expected to know it if
 442                  * we know the other parameters.
 443                  *
 444                  * This is something that can easily be fixed in Addrlib.
 445                  * For now, just figure it out here.
 446                  * Note that only 2D_TILE_THIN1 is handled here.
 447                  */
 448                 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
 449                 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
 450
 451                 if (ws->info.chip_class == SI) {
 452                         if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
 453                                 if (surf->bpe == 2)
 454                                         AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
 455                                 else
 456                                         AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
 457                         } else {
 458                                 if (surf->bpe == 1)
 459                                         AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
 460                                 else if (surf->bpe == 2)
 461                                         AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
 462                                 else if (surf->bpe == 4)
 463                                         AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
 464                                 else
 465                                         AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
 466                         }
 467                 } else {
 468                         if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
 469                                 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
 470                         else
 471                                 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
 472                         AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
 473                 }
 474         }
 475
 476         surf->surf_size = 0;
 477         surf->num_dcc_levels = 0;
 478         surf->dcc_size = 0;
 479         surf->dcc_alignment = 1;
 480         surf->htile_size = surf->htile_slice_size = 0;
 481         surf->htile_alignment = 1;
 482
 483         /* Calculate texture layout information. */
 484         for (level = 0; level <= last_level; level++) {
 485                 r = radv_compute_level(ws->addrlib, surf_info, surf, false, level, type, compressed,
 486                                        &AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut);
 487                 if (r)
 488                         break;
 489
 490                 if (level == 0) {
 491                         surf->surf_alignment = AddrSurfInfoOut.baseAlign;
 492                         surf->u.legacy.pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
 493                         radv_set_micro_tile_mode(surf, &ws->info);
 494
 495                         /* For 2D modes only. */
 496                         if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
 497                                 surf->u.legacy.bankw = AddrSurfInfoOut.pTileInfo->bankWidth;
 498                                 surf->u.legacy.bankh = AddrSurfInfoOut.pTileInfo->bankHeight;
 499                                 surf->u.legacy.mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio;
 500                                 surf->u.legacy.tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
 501                                 surf->u.legacy.num_banks = AddrSurfInfoOut.pTileInfo->banks;
 502                                 surf->u.legacy.macro_tile_index = AddrSurfInfoOut.macroModeIndex;
 503                         } else {
 504                                 surf->u.legacy.macro_tile_index = 0;
 505                         }
 506                 }
 507         }
 508
 509         /* Calculate texture layout information for stencil. */
 510         if (surf->flags & RADEON_SURF_SBUFFER) {
 511                 AddrSurfInfoIn.bpp = 8;
 512                 AddrSurfInfoIn.flags.depth = 0;
 513                 AddrSurfInfoIn.flags.stencil = 1;
 514                 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
 515                 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
 516
 517                 for (level = 0; level <= last_level; level++) {
 518                         r = radv_compute_level(ws->addrlib, surf_info, surf, true, level, type, compressed,
 519                                                &AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut);
 520                         if (r)
 521                                 return r;
 522
 523                         /* DB uses the depth pitch for both stencil and depth. */
 524                         if (surf->u.legacy.stencil_level[level].nblk_x != surf->u.legacy.level[level].nblk_x)
 525                                 surf->u.legacy.stencil_adjusted = true;
 526
 527                         if (level == 0) {
 528                                 /* For 2D modes only. */
 529                                 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
 530                                         surf->u.legacy.stencil_tile_split =
 531                                                 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
 532                                 }
 533                         }
 534                 }
 535         }
 536
 537         /* Recalculate the whole DCC miptree size including disabled levels.
 538          * This is what addrlib does, but calling addrlib would be a lot more
 539          * complicated.
 540          */
 541 #if 0
 542         if (surf->dcc_size && last_level > 0) {
 543                 surf->dcc_size = align64(surf->bo_size >> 8,
 544                                          ws->info.pipe_interleave_bytes *
 545                                          ws->info.num_tile_pipes);
 546         }
 547 #endif
 548         return 0;
 549 }
 550
 551 static int radv_amdgpu_winsys_surface_best(struct radeon_winsys *rws,
 552                                            struct radeon_surf *surf)
 553 {
 554         return 0;
 555 }
 556
 557 void radv_amdgpu_surface_init_functions(struct radv_amdgpu_winsys *ws)
 558 {
 559         ws->base.surface_init = radv_amdgpu_winsys_surface_init;
 560         ws->base.surface_best = radv_amdgpu_winsys_surface_best;
 561 }