src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based on amdgpu winsys.
   6  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   7  * Copyright © 2015 Advanced Micro Devices, Inc.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  26  * IN THE SOFTWARE.
  27  */
  28
  29 #include <errno.h>
  30
  31 #include "radv_private.h"
  32 #include "addrlib/addrinterface.h"
  33 #include "util/bitset.h"
  34 #include "radv_amdgpu_winsys.h"
  35 #include "radv_amdgpu_surface.h"
  36 #include "sid.h"
  37
  38 #ifndef NO_ENTRIES
  39 #define NO_ENTRIES 32
  40 #endif
  41
  42 #ifndef NO_MACRO_ENTRIES
  43 #define NO_MACRO_ENTRIES 16
  44 #endif
  45
  46 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
  47 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
  48 #endif
  49
  50 static int radv_amdgpu_surface_sanity(const struct radeon_surf_info *surf_info,
  51                                       const struct radeon_surf *surf)
  52 {
  53         unsigned type = RADEON_SURF_GET(surf->flags, TYPE);
  54
  55         if (!(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))
  56                 return -EINVAL;
  57
  58         /* all dimension must be at least 1 ! */
  59         if (!surf_info->width || !surf_info->height || !surf_info->depth ||
  60             !surf_info->array_size)
  61                 return -EINVAL;
  62
  63         if (!surf->blk_w || !surf->blk_h)
  64                 return -EINVAL;
  65
  66         switch (surf_info->samples) {
  67         case 1:
  68         case 2:
  69         case 4:
  70         case 8:
  71                 break;
  72         default:
  73                 return -EINVAL;
  74         }
  75
  76         switch (type) {
  77         case RADEON_SURF_TYPE_1D:
  78                 if (surf_info->height > 1)
  79                         return -EINVAL;
  80                 /* fall through */
  81         case RADEON_SURF_TYPE_2D:
  82         case RADEON_SURF_TYPE_CUBEMAP:
  83                 if (surf_info->depth > 1 || surf_info->array_size > 1)
  84                         return -EINVAL;
  85                 break;
  86         case RADEON_SURF_TYPE_3D:
  87                 if (surf_info->array_size > 1)
  88                         return -EINVAL;
  89                 break;
  90         case RADEON_SURF_TYPE_1D_ARRAY:
  91                 if (surf_info->height > 1)
  92                         return -EINVAL;
  93                 /* fall through */
  94         case RADEON_SURF_TYPE_2D_ARRAY:
  95                 if (surf_info->depth > 1)
  96                         return -EINVAL;
  97                 break;
  98         default:
  99                 return -EINVAL;
 100         }
 101         return 0;
 102 }
 103
 104 static void *ADDR_API radv_allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
 105 {
 106         return malloc(pInput->sizeInBytes);
 107 }
 108
 109 static ADDR_E_RETURNCODE ADDR_API radv_freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
 110 {
 111         free(pInput->pVirtAddr);
 112         return ADDR_OK;
 113 }
 114
 115 ADDR_HANDLE radv_amdgpu_addr_create(struct amdgpu_gpu_info *amdinfo, int family, int rev_id,
 116                                     enum chip_class chip_class)
 117 {
 118         ADDR_CREATE_INPUT addrCreateInput = {0};
 119         ADDR_CREATE_OUTPUT addrCreateOutput = {0};
 120         ADDR_REGISTER_VALUE regValue = {0};
 121         ADDR_CREATE_FLAGS createFlags = {{0}};
 122         ADDR_E_RETURNCODE addrRet;
 123
 124         addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
 125         addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
 126
 127         regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
 128         regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
 129         regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
 130
 131         regValue.backendDisables = amdinfo->backend_disable[0];
 132         regValue.pTileConfig = amdinfo->gb_tile_mode;
 133         regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
 134         if (chip_class == SI) {
 135                 regValue.pMacroTileConfig = NULL;
 136                 regValue.noOfMacroEntries = 0;
 137         } else {
 138                 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
 139                 regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
 140         }
 141
 142         createFlags.value = 0;
 143         createFlags.useTileIndex = 1;
 144
 145         addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
 146         addrCreateInput.chipFamily = family;
 147         addrCreateInput.chipRevision = rev_id;
 148         addrCreateInput.createFlags = createFlags;
 149         addrCreateInput.callbacks.allocSysMem = radv_allocSysMem;
 150         addrCreateInput.callbacks.freeSysMem = radv_freeSysMem;
 151         addrCreateInput.callbacks.debugPrint = 0;
 152         addrCreateInput.regValue = regValue;
 153
 154         addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
 155         if (addrRet != ADDR_OK)
 156                 return NULL;
 157
 158         return addrCreateOutput.hLib;
 159 }
 160
 161 static int radv_compute_level(ADDR_HANDLE addrlib,
 162                               const struct radeon_surf_info *surf_info,
 163                               struct radeon_surf *surf, bool is_stencil,
 164                               unsigned level, unsigned type, bool compressed,
 165                               ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
 166                               ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
 167                               ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
 168                               ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut)
 169 {
 170         struct radeon_surf_level *surf_level;
 171         ADDR_E_RETURNCODE ret;
 172
 173         AddrSurfInfoIn->mipLevel = level;
 174         AddrSurfInfoIn->width = u_minify(surf_info->width, level);
 175         AddrSurfInfoIn->height = u_minify(surf_info->height, level);
 176
 177         if (type == RADEON_SURF_TYPE_3D)
 178                 AddrSurfInfoIn->numSlices = u_minify(surf_info->depth, level);
 179         else if (type == RADEON_SURF_TYPE_CUBEMAP)
 180                 AddrSurfInfoIn->numSlices = 6;
 181         else
 182                 AddrSurfInfoIn->numSlices = surf_info->array_size;
 183
 184         if (level > 0) {
 185                 /* Set the base level pitch. This is needed for calculation
 186                  * of non-zero levels. */
 187                 if (is_stencil)
 188                         AddrSurfInfoIn->basePitch = surf->stencil_level[0].nblk_x;
 189                 else
 190                         AddrSurfInfoIn->basePitch = surf->level[0].nblk_x;
 191
 192                 /* Convert blocks to pixels for compressed formats. */
 193                 if (compressed)
 194                         AddrSurfInfoIn->basePitch *= surf->blk_w;
 195         }
 196
 197         ret = AddrComputeSurfaceInfo(addrlib,
 198                                      AddrSurfInfoIn,
 199                                      AddrSurfInfoOut);
 200         if (ret != ADDR_OK)
 201                 return ret;
 202
 203         surf_level = is_stencil ? &surf->stencil_level[level] : &surf->level[level];
 204         surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
 205         surf_level->slice_size = AddrSurfInfoOut->sliceSize;
 206         surf_level->nblk_x = AddrSurfInfoOut->pitch;
 207         surf_level->nblk_y = AddrSurfInfoOut->height;
 208
 209         switch (AddrSurfInfoOut->tileMode) {
 210         case ADDR_TM_LINEAR_ALIGNED:
 211                 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
 212                 break;
 213         case ADDR_TM_1D_TILED_THIN1:
 214                 surf_level->mode = RADEON_SURF_MODE_1D;
 215                 break;
 216         case ADDR_TM_2D_TILED_THIN1:
 217                 surf_level->mode = RADEON_SURF_MODE_2D;
 218                 break;
 219         default:
 220                 assert(0);
 221         }
 222
 223         if (is_stencil)
 224                 surf->stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
 225         else
 226                 surf->tiling_index[level] = AddrSurfInfoOut->tileIndex;
 227
 228         surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
 229
 230         /* Clear DCC fields at the beginning. */
 231         surf_level->dcc_offset = 0;
 232
 233         /* The previous level's flag tells us if we can use DCC for this level. */
 234         if (AddrSurfInfoIn->flags.dccCompatible &&
 235             (level == 0 || AddrDccOut->subLvlCompressible)) {
 236                 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
 237                 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
 238                 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
 239                 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
 240                 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
 241
 242                 ret = AddrComputeDccInfo(addrlib,
 243                                          AddrDccIn,
 244                                          AddrDccOut);
 245
 246                 if (ret == ADDR_OK) {
 247                         surf_level->dcc_offset = surf->dcc_size;
 248                         surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
 249                         surf->num_dcc_levels = level + 1;
 250                         surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
 251                         surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
 252                 }
 253         }
 254
 255         if (!is_stencil && AddrSurfInfoIn->flags.depth &&
 256             surf_level->mode == RADEON_SURF_MODE_2D && level == 0) {
 257                 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
 258                 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
 259                 AddrHtileIn.flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
 260                 AddrHtileIn.pitch = AddrSurfInfoOut->pitch;
 261                 AddrHtileIn.height = AddrSurfInfoOut->height;
 262                 AddrHtileIn.numSlices = AddrSurfInfoOut->depth;
 263                 AddrHtileIn.blockWidth = ADDR_HTILE_BLOCKSIZE_8;
 264                 AddrHtileIn.blockHeight = ADDR_HTILE_BLOCKSIZE_8;
 265                 AddrHtileIn.pTileInfo = AddrSurfInfoOut->pTileInfo;
 266                 AddrHtileIn.tileIndex = AddrSurfInfoOut->tileIndex;
 267                 AddrHtileIn.macroModeIndex = AddrSurfInfoOut->macroModeIndex;
 268
 269                 ret = AddrComputeHtileInfo(addrlib,
 270                                            &AddrHtileIn,
 271                                            &AddrHtileOut);
 272
 273                 if (ret == ADDR_OK) {
 274                         surf->htile_size = AddrHtileOut.htileBytes;
 275                         surf->htile_slice_size = AddrHtileOut.sliceSize;
 276                         surf->htile_alignment = AddrHtileOut.baseAlign;
 277                 }
 278         }
 279         return 0;
 280 }
 281
 282 static void radv_set_micro_tile_mode(struct radeon_surf *surf,
 283                                      struct radeon_info *info)
 284 {
 285         uint32_t tile_mode = info->si_tile_mode_array[surf->tiling_index[0]];
 286
 287         if (info->chip_class >= CIK)
 288                 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
 289         else
 290                 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
 291 }
 292
 293 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
 294 {
 295         unsigned index, tileb;
 296
 297         tileb = 8 * 8 * surf->bpe;
 298         tileb = MIN2(surf->tile_split, tileb);
 299
 300         for (index = 0; tileb > 64; index++)
 301                 tileb >>= 1;
 302
 303         assert(index < 16);
 304         return index;
 305 }
 306
 307 static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
 308                                            const struct radeon_surf_info *surf_info,
 309                                            struct radeon_surf *surf)
 310 {
 311         struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
 312         unsigned level, mode, type;
 313         bool compressed;
 314         ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
 315         ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
 316         ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
 317         ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
 318         ADDR_TILEINFO AddrTileInfoIn = {0};
 319         ADDR_TILEINFO AddrTileInfoOut = {0};
 320         int r;
 321         uint32_t last_level = surf_info->levels - 1;
 322
 323         r = radv_amdgpu_surface_sanity(surf_info, surf);
 324         if (r)
 325                 return r;
 326
 327         AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
 328         AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
 329         AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
 330         AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
 331         AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
 332
 333         type = RADEON_SURF_GET(surf->flags, TYPE);
 334         mode = RADEON_SURF_GET(surf->flags, MODE);
 335         compressed = surf->blk_w == 4 && surf->blk_h == 4;
 336
 337         /* MSAA and FMASK require 2D tiling. */
 338         if (surf_info->samples > 1 ||
 339             (surf->flags & RADEON_SURF_FMASK))
 340                 mode = RADEON_SURF_MODE_2D;
 341
 342         /* DB doesn't support linear layouts. */
 343         if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
 344             mode < RADEON_SURF_MODE_1D)
 345                 mode = RADEON_SURF_MODE_1D;
 346
 347         /* Set the requested tiling mode. */
 348         switch (mode) {
 349         case RADEON_SURF_MODE_LINEAR_ALIGNED:
 350                 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
 351                 break;
 352         case RADEON_SURF_MODE_1D:
 353                 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
 354                 break;
 355         case RADEON_SURF_MODE_2D:
 356                 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
 357                 break;
 358         default:
 359                 assert(0);
 360         }
 361
 362         /* The format must be set correctly for the allocation of compressed
 363          * textures to work. In other cases, setting the bpp is sufficient. */
 364         if (compressed) {
 365                 switch (surf->bpe) {
 366                 case 8:
 367                         AddrSurfInfoIn.format = ADDR_FMT_BC1;
 368                         break;
 369                 case 16:
 370                         AddrSurfInfoIn.format = ADDR_FMT_BC3;
 371                         break;
 372                 default:
 373                         assert(0);
 374                 }
 375         } else {
 376                 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
 377         }
 378
 379         AddrDccIn.numSamples = AddrSurfInfoIn.numSamples = surf_info->samples;
 380         AddrSurfInfoIn.tileIndex = -1;
 381
 382         /* Set the micro tile type. */
 383         if (surf->flags & RADEON_SURF_SCANOUT)
 384                 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
 385         else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
 386                 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
 387         else
 388                 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
 389
 390         AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
 391         AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
 392         AddrSurfInfoIn.flags.cube = type == RADEON_SURF_TYPE_CUBEMAP;
 393         AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
 394         AddrSurfInfoIn.flags.pow2Pad = last_level > 0;
 395         AddrSurfInfoIn.flags.opt4Space = 1;
 396
 397         /* DCC notes:
 398          * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
 399          *   with samples >= 4.
 400          * - Mipmapped array textures have low performance (discovered by a closed
 401          *   driver team).
 402          */
 403         AddrSurfInfoIn.flags.dccCompatible = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
 404                 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
 405                 !compressed && AddrDccIn.numSamples <= 1 &&
 406                 ((surf_info->array_size == 1 && surf_info->depth == 1) ||
 407                  last_level == 0);
 408
 409         AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
 410         AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
 411
 412         /* noStencil = 0 can result in a depth part that is incompatible with
 413          * mipmapped texturing. So set noStencil = 1 when mipmaps are requested (in
 414          * this case, we may end up setting stencil_adjusted).
 415          *
 416          * TODO: update addrlib to a newer version, remove this, and
 417          * use flags.matchStencilTileCfg = 1 as an alternative fix.
 418          */
 419         if (last_level > 0)
 420                 AddrSurfInfoIn.flags.noStencil = 1;
 421
 422         /* Set preferred macrotile parameters. This is usually required
 423          * for shared resources. This is for 2D tiling only. */
 424         if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
 425             surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) {
 426                 /* If any of these parameters are incorrect, the calculation
 427                  * will fail. */
 428                 AddrTileInfoIn.banks = surf->num_banks;
 429                 AddrTileInfoIn.bankWidth = surf->bankw;
 430                 AddrTileInfoIn.bankHeight = surf->bankh;
 431                 AddrTileInfoIn.macroAspectRatio = surf->mtilea;
 432                 AddrTileInfoIn.tileSplitBytes = surf->tile_split;
 433                 AddrTileInfoIn.pipeConfig = surf->pipe_config + 1; /* +1 compared to GB_TILE_MODE */
 434                 AddrSurfInfoIn.flags.opt4Space = 0;
 435                 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
 436
 437                 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
 438                  * the tile index, because we are expected to know it if
 439                  * we know the other parameters.
 440                  *
 441                  * This is something that can easily be fixed in Addrlib.
 442                  * For now, just figure it out here.
 443                  * Note that only 2D_TILE_THIN1 is handled here.
 444                  */
 445                 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
 446                 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
 447
 448                 if (ws->info.chip_class == SI) {
 449                         if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
 450                                 if (surf->bpe == 2)
 451                                         AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
 452                                 else
 453                                         AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
 454                         } else {
 455                                 if (surf->bpe == 1)
 456                                         AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
 457                                 else if (surf->bpe == 2)
 458                                         AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
 459                                 else if (surf->bpe == 4)
 460                                         AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
 461                                 else
 462                                         AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
 463                         }
 464                 } else {
 465                         if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
 466                                 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
 467                         else
 468                                 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
 469                         AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
 470                 }
 471         }
 472
 473         surf->surf_size = 0;
 474         surf->num_dcc_levels = 0;
 475         surf->dcc_size = 0;
 476         surf->dcc_alignment = 1;
 477         surf->htile_size = surf->htile_slice_size = 0;
 478         surf->htile_alignment = 1;
 479
 480         /* Calculate texture layout information. */
 481         for (level = 0; level <= last_level; level++) {
 482                 r = radv_compute_level(ws->addrlib, surf_info, surf, false, level, type, compressed,
 483                                        &AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut);
 484                 if (r)
 485                         break;
 486
 487                 if (level == 0) {
 488                         surf->surf_alignment = AddrSurfInfoOut.baseAlign;
 489                         surf->pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
 490                         radv_set_micro_tile_mode(surf, &ws->info);
 491
 492                         /* For 2D modes only. */
 493                         if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
 494                                 surf->bankw = AddrSurfInfoOut.pTileInfo->bankWidth;
 495                                 surf->bankh = AddrSurfInfoOut.pTileInfo->bankHeight;
 496                                 surf->mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio;
 497                                 surf->tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
 498                                 surf->num_banks = AddrSurfInfoOut.pTileInfo->banks;
 499                                 surf->macro_tile_index = AddrSurfInfoOut.macroModeIndex;
 500                         } else {
 501                                 surf->macro_tile_index = 0;
 502                         }
 503                 }
 504         }
 505
 506         /* Calculate texture layout information for stencil. */
 507         if (surf->flags & RADEON_SURF_SBUFFER) {
 508                 AddrSurfInfoIn.bpp = 8;
 509                 AddrSurfInfoIn.flags.depth = 0;
 510                 AddrSurfInfoIn.flags.stencil = 1;
 511                 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
 512                 AddrTileInfoIn.tileSplitBytes = surf->stencil_tile_split;
 513
 514                 for (level = 0; level <= last_level; level++) {
 515                         r = radv_compute_level(ws->addrlib, surf_info, surf, true, level, type, compressed,
 516                                                &AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut);
 517                         if (r)
 518                                 return r;
 519
 520                         /* DB uses the depth pitch for both stencil and depth. */
 521                         if (surf->stencil_level[level].nblk_x != surf->level[level].nblk_x)
 522                                 surf->stencil_adjusted = true;
 523
 524                         if (level == 0) {
 525                                 /* For 2D modes only. */
 526                                 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
 527                                         surf->stencil_tile_split =
 528                                                 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
 529                                 }
 530                         }
 531                 }
 532         }
 533
 534         /* Recalculate the whole DCC miptree size including disabled levels.
 535          * This is what addrlib does, but calling addrlib would be a lot more
 536          * complicated.
 537          */
 538 #if 0
 539         if (surf->dcc_size && last_level > 0) {
 540                 surf->dcc_size = align64(surf->bo_size >> 8,
 541                                          ws->info.pipe_interleave_bytes *
 542                                          ws->info.num_tile_pipes);
 543         }
 544 #endif
 545         return 0;
 546 }
 547
 548 static int radv_amdgpu_winsys_surface_best(struct radeon_winsys *rws,
 549                                            struct radeon_surf *surf)
 550 {
 551         return 0;
 552 }
 553
 554 void radv_amdgpu_surface_init_functions(struct radv_amdgpu_winsys *ws)
 555 {
 556         ws->base.surface_init = radv_amdgpu_winsys_surface_init;
 557         ws->base.surface_best = radv_amdgpu_winsys_surface_best;
 558 }