src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based on amdgpu winsys.
   6  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   7  * Copyright © 2015 Advanced Micro Devices, Inc.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  26  * IN THE SOFTWARE.
  27  */
  28
  29 #include <errno.h>
  30
  31 #include "radv_private.h"
  32 #include "addrlib/addrinterface.h"
  33 #include "util/bitset.h"
  34 #include "radv_amdgpu_winsys.h"
  35 #include "radv_amdgpu_surface.h"
  36 #include "sid.h"
  37
  38 #ifndef NO_ENTRIES
  39 #define NO_ENTRIES 32
  40 #endif
  41
  42 #ifndef NO_MACRO_ENTRIES
  43 #define NO_MACRO_ENTRIES 16
  44 #endif
  45
  46 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
  47 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
  48 #endif
  49
  50 static int radv_amdgpu_surface_sanity(const struct radeon_surf *surf)
  51 {
  52         unsigned type = RADEON_SURF_GET(surf->flags, TYPE);
  53
  54         if (!(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))
  55                 return -EINVAL;
  56
  57         /* all dimension must be at least 1 ! */
  58         if (!surf->npix_x || !surf->npix_y || !surf->npix_z ||
  59             !surf->array_size)
  60                 return -EINVAL;
  61
  62         if (!surf->blk_w || !surf->blk_h || !surf->blk_d)
  63                 return -EINVAL;
  64
  65         switch (surf->nsamples) {
  66         case 1:
  67         case 2:
  68         case 4:
  69         case 8:
  70                 break;
  71         default:
  72                 return -EINVAL;
  73         }
  74
  75         switch (type) {
  76         case RADEON_SURF_TYPE_1D:
  77                 if (surf->npix_y > 1)
  78                         return -EINVAL;
  79                 /* fall through */
  80         case RADEON_SURF_TYPE_2D:
  81         case RADEON_SURF_TYPE_CUBEMAP:
  82                 if (surf->npix_z > 1 || surf->array_size > 1)
  83                         return -EINVAL;
  84                 break;
  85         case RADEON_SURF_TYPE_3D:
  86                 if (surf->array_size > 1)
  87                         return -EINVAL;
  88                 break;
  89         case RADEON_SURF_TYPE_1D_ARRAY:
  90                 if (surf->npix_y > 1)
  91                         return -EINVAL;
  92                 /* fall through */
  93         case RADEON_SURF_TYPE_2D_ARRAY:
  94                 if (surf->npix_z > 1)
  95                         return -EINVAL;
  96                 break;
  97         default:
  98                 return -EINVAL;
  99         }
 100         return 0;
 101 }
 102
 103 static void *ADDR_API radv_allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
 104 {
 105         return malloc(pInput->sizeInBytes);
 106 }
 107
 108 static ADDR_E_RETURNCODE ADDR_API radv_freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
 109 {
 110         free(pInput->pVirtAddr);
 111         return ADDR_OK;
 112 }
 113
 114 ADDR_HANDLE radv_amdgpu_addr_create(struct amdgpu_gpu_info *amdinfo, int family, int rev_id,
 115                                     enum chip_class chip_class)
 116 {
 117         ADDR_CREATE_INPUT addrCreateInput = {0};
 118         ADDR_CREATE_OUTPUT addrCreateOutput = {0};
 119         ADDR_REGISTER_VALUE regValue = {0};
 120         ADDR_CREATE_FLAGS createFlags = {{0}};
 121         ADDR_E_RETURNCODE addrRet;
 122
 123         addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
 124         addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
 125
 126         regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
 127         regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
 128         regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
 129
 130         regValue.backendDisables = amdinfo->backend_disable[0];
 131         regValue.pTileConfig = amdinfo->gb_tile_mode;
 132         regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
 133         if (chip_class == SI) {
 134                 regValue.pMacroTileConfig = NULL;
 135                 regValue.noOfMacroEntries = 0;
 136         } else {
 137                 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
 138                 regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
 139         }
 140
 141         createFlags.value = 0;
 142         createFlags.useTileIndex = 1;
 143
 144         addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
 145         addrCreateInput.chipFamily = family;
 146         addrCreateInput.chipRevision = rev_id;
 147         addrCreateInput.createFlags = createFlags;
 148         addrCreateInput.callbacks.allocSysMem = radv_allocSysMem;
 149         addrCreateInput.callbacks.freeSysMem = radv_freeSysMem;
 150         addrCreateInput.callbacks.debugPrint = 0;
 151         addrCreateInput.regValue = regValue;
 152
 153         addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
 154         if (addrRet != ADDR_OK)
 155                 return NULL;
 156
 157         return addrCreateOutput.hLib;
 158 }
 159
 160 static int radv_compute_level(ADDR_HANDLE addrlib,
 161                               struct radeon_surf *surf, bool is_stencil,
 162                               unsigned level, unsigned type, bool compressed,
 163                               ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
 164                               ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
 165                               ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
 166                               ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut)
 167 {
 168         struct radeon_surf_level *surf_level;
 169         ADDR_E_RETURNCODE ret;
 170
 171         AddrSurfInfoIn->mipLevel = level;
 172         AddrSurfInfoIn->width = u_minify(surf->npix_x, level);
 173         AddrSurfInfoIn->height = u_minify(surf->npix_y, level);
 174
 175         if (type == RADEON_SURF_TYPE_3D)
 176                 AddrSurfInfoIn->numSlices = u_minify(surf->npix_z, level);
 177         else if (type == RADEON_SURF_TYPE_CUBEMAP)
 178                 AddrSurfInfoIn->numSlices = 6;
 179         else
 180                 AddrSurfInfoIn->numSlices = surf->array_size;
 181
 182         if (level > 0) {
 183                 /* Set the base level pitch. This is needed for calculation
 184                  * of non-zero levels. */
 185                 if (is_stencil)
 186                         AddrSurfInfoIn->basePitch = surf->stencil_level[0].nblk_x;
 187                 else
 188                         AddrSurfInfoIn->basePitch = surf->level[0].nblk_x;
 189
 190                 /* Convert blocks to pixels for compressed formats. */
 191                 if (compressed)
 192                         AddrSurfInfoIn->basePitch *= surf->blk_w;
 193         }
 194
 195         ret = AddrComputeSurfaceInfo(addrlib,
 196                                      AddrSurfInfoIn,
 197                                      AddrSurfInfoOut);
 198         if (ret != ADDR_OK)
 199                 return ret;
 200
 201         surf_level = is_stencil ? &surf->stencil_level[level] : &surf->level[level];
 202         surf_level->offset = align64(surf->bo_size, AddrSurfInfoOut->baseAlign);
 203         surf_level->slice_size = AddrSurfInfoOut->sliceSize;
 204         surf_level->pitch_bytes = AddrSurfInfoOut->pitch * (is_stencil ? 1 : surf->bpe);
 205         surf_level->npix_x = u_minify(surf->npix_x, level);
 206         surf_level->npix_y = u_minify(surf->npix_y, level);
 207         surf_level->npix_z = u_minify(surf->npix_z, level);
 208         surf_level->nblk_x = AddrSurfInfoOut->pitch;
 209         surf_level->nblk_y = AddrSurfInfoOut->height;
 210         if (type == RADEON_SURF_TYPE_3D)
 211                 surf_level->nblk_z = AddrSurfInfoOut->depth;
 212         else
 213                 surf_level->nblk_z = 1;
 214
 215         switch (AddrSurfInfoOut->tileMode) {
 216         case ADDR_TM_LINEAR_ALIGNED:
 217                 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
 218                 break;
 219         case ADDR_TM_1D_TILED_THIN1:
 220                 surf_level->mode = RADEON_SURF_MODE_1D;
 221                 break;
 222         case ADDR_TM_2D_TILED_THIN1:
 223                 surf_level->mode = RADEON_SURF_MODE_2D;
 224                 break;
 225         default:
 226                 assert(0);
 227         }
 228
 229         if (is_stencil)
 230                 surf->stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
 231         else
 232                 surf->tiling_index[level] = AddrSurfInfoOut->tileIndex;
 233
 234         surf->bo_size = surf_level->offset + AddrSurfInfoOut->surfSize;
 235
 236         /* Clear DCC fields at the beginning. */
 237         surf_level->dcc_offset = 0;
 238         surf_level->dcc_enabled = false;
 239
 240         /* The previous level's flag tells us if we can use DCC for this level. */
 241         if (AddrSurfInfoIn->flags.dccCompatible &&
 242             (level == 0 || AddrDccOut->subLvlCompressible)) {
 243                 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
 244                 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
 245                 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
 246                 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
 247                 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
 248
 249                 ret = AddrComputeDccInfo(addrlib,
 250                                          AddrDccIn,
 251                                          AddrDccOut);
 252
 253                 if (ret == ADDR_OK) {
 254                         surf_level->dcc_offset = surf->dcc_size;
 255                         surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
 256                         surf_level->dcc_enabled = true;
 257                         surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
 258                         surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
 259                 }
 260         }
 261
 262         if (!is_stencil && AddrSurfInfoIn->flags.depth &&
 263             surf_level->mode == RADEON_SURF_MODE_2D && level == 0) {
 264                 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
 265                 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
 266                 AddrHtileIn.flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
 267                 AddrHtileIn.pitch = AddrSurfInfoOut->pitch;
 268                 AddrHtileIn.height = AddrSurfInfoOut->height;
 269                 AddrHtileIn.numSlices = AddrSurfInfoOut->depth;
 270                 AddrHtileIn.blockWidth = ADDR_HTILE_BLOCKSIZE_8;
 271                 AddrHtileIn.blockHeight = ADDR_HTILE_BLOCKSIZE_8;
 272                 AddrHtileIn.pTileInfo = AddrSurfInfoOut->pTileInfo;
 273                 AddrHtileIn.tileIndex = AddrSurfInfoOut->tileIndex;
 274                 AddrHtileIn.macroModeIndex = AddrSurfInfoOut->macroModeIndex;
 275
 276                 ret = AddrComputeHtileInfo(addrlib,
 277                                            &AddrHtileIn,
 278                                            &AddrHtileOut);
 279
 280                 if (ret == ADDR_OK) {
 281                         surf->htile_size = AddrHtileOut.htileBytes;
 282                         surf->htile_slice_size = AddrHtileOut.sliceSize;
 283                         surf->htile_alignment = AddrHtileOut.baseAlign;
 284                 }
 285         }
 286         return 0;
 287 }
 288
 289 static void radv_set_micro_tile_mode(struct radeon_surf *surf,
 290                                      struct radeon_info *info)
 291 {
 292         uint32_t tile_mode = info->si_tile_mode_array[surf->tiling_index[0]];
 293
 294         if (info->chip_class >= CIK)
 295                 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
 296         else
 297                 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
 298 }
 299
 300 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
 301 {
 302         unsigned index, tileb;
 303
 304         tileb = 8 * 8 * surf->bpe;
 305         tileb = MIN2(surf->tile_split, tileb);
 306
 307         for (index = 0; tileb > 64; index++)
 308                 tileb >>= 1;
 309
 310         assert(index < 16);
 311         return index;
 312 }
 313
 314 static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
 315                                            struct radeon_surf *surf)
 316 {
 317         struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
 318         unsigned level, mode, type;
 319         bool compressed;
 320         ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
 321         ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
 322         ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
 323         ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
 324         ADDR_TILEINFO AddrTileInfoIn = {0};
 325         ADDR_TILEINFO AddrTileInfoOut = {0};
 326         int r;
 327
 328         r = radv_amdgpu_surface_sanity(surf);
 329         if (r)
 330                 return r;
 331
 332         AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
 333         AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
 334         AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
 335         AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
 336         AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
 337
 338         type = RADEON_SURF_GET(surf->flags, TYPE);
 339         mode = RADEON_SURF_GET(surf->flags, MODE);
 340         compressed = surf->blk_w == 4 && surf->blk_h == 4;
 341
 342         /* MSAA and FMASK require 2D tiling. */
 343         if (surf->nsamples > 1 ||
 344             (surf->flags & RADEON_SURF_FMASK))
 345                 mode = RADEON_SURF_MODE_2D;
 346
 347         /* DB doesn't support linear layouts. */
 348         if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
 349             mode < RADEON_SURF_MODE_1D)
 350                 mode = RADEON_SURF_MODE_1D;
 351
 352         /* Set the requested tiling mode. */
 353         switch (mode) {
 354         case RADEON_SURF_MODE_LINEAR_ALIGNED:
 355                 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
 356                 break;
 357         case RADEON_SURF_MODE_1D:
 358                 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
 359                 break;
 360         case RADEON_SURF_MODE_2D:
 361                 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
 362                 break;
 363         default:
 364                 assert(0);
 365         }
 366
 367         /* The format must be set correctly for the allocation of compressed
 368          * textures to work. In other cases, setting the bpp is sufficient. */
 369         if (compressed) {
 370                 switch (surf->bpe) {
 371                 case 8:
 372                         AddrSurfInfoIn.format = ADDR_FMT_BC1;
 373                         break;
 374                 case 16:
 375                         AddrSurfInfoIn.format = ADDR_FMT_BC3;
 376                         break;
 377                 default:
 378                         assert(0);
 379                 }
 380         } else {
 381                 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
 382         }
 383
 384         AddrDccIn.numSamples = AddrSurfInfoIn.numSamples = surf->nsamples;
 385         AddrSurfInfoIn.tileIndex = -1;
 386
 387         /* Set the micro tile type. */
 388         if (surf->flags & RADEON_SURF_SCANOUT)
 389                 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
 390         else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
 391                 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
 392         else
 393                 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
 394
 395         AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
 396         AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
 397         AddrSurfInfoIn.flags.cube = type == RADEON_SURF_TYPE_CUBEMAP;
 398         AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
 399         AddrSurfInfoIn.flags.pow2Pad = surf->last_level > 0;
 400         AddrSurfInfoIn.flags.opt4Space = 1;
 401
 402         /* DCC notes:
 403          * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
 404          *   with samples >= 4.
 405          * - Mipmapped array textures have low performance (discovered by a closed
 406          *   driver team).
 407          */
 408         AddrSurfInfoIn.flags.dccCompatible = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
 409                 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
 410                 !compressed && AddrDccIn.numSamples <= 1 &&
 411                 ((surf->array_size == 1 && surf->npix_z == 1) ||
 412                  surf->last_level == 0);
 413
 414         AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
 415         AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
 416
 417         /* noStencil = 0 can result in a depth part that is incompatible with
 418          * mipmapped texturing. So set noStencil = 1 when mipmaps are requested (in
 419          * this case, we may end up setting stencil_adjusted).
 420          *
 421          * TODO: update addrlib to a newer version, remove this, and
 422          * use flags.matchStencilTileCfg = 1 as an alternative fix.
 423          */
 424         if (surf->last_level > 0)
 425                 AddrSurfInfoIn.flags.noStencil = 1;
 426
 427         /* Set preferred macrotile parameters. This is usually required
 428          * for shared resources. This is for 2D tiling only. */
 429         if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
 430             surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) {
 431                 /* If any of these parameters are incorrect, the calculation
 432                  * will fail. */
 433                 AddrTileInfoIn.banks = surf->num_banks;
 434                 AddrTileInfoIn.bankWidth = surf->bankw;
 435                 AddrTileInfoIn.bankHeight = surf->bankh;
 436                 AddrTileInfoIn.macroAspectRatio = surf->mtilea;
 437                 AddrTileInfoIn.tileSplitBytes = surf->tile_split;
 438                 AddrTileInfoIn.pipeConfig = surf->pipe_config + 1; /* +1 compared to GB_TILE_MODE */
 439                 AddrSurfInfoIn.flags.opt4Space = 0;
 440                 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
 441
 442                 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
 443                  * the tile index, because we are expected to know it if
 444                  * we know the other parameters.
 445                  *
 446                  * This is something that can easily be fixed in Addrlib.
 447                  * For now, just figure it out here.
 448                  * Note that only 2D_TILE_THIN1 is handled here.
 449                  */
 450                 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
 451                 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
 452
 453                 if (ws->info.chip_class == SI) {
 454                         if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
 455                                 if (surf->bpe == 2)
 456                                         AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
 457                                 else
 458                                         AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
 459                         } else {
 460                                 if (surf->bpe == 1)
 461                                         AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
 462                                 else if (surf->bpe == 2)
 463                                         AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
 464                                 else if (surf->bpe == 4)
 465                                         AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
 466                                 else
 467                                         AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
 468                         }
 469                 } else {
 470                         if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
 471                                 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
 472                         else
 473                                 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
 474                         AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
 475                 }
 476         }
 477
 478         surf->bo_size = 0;
 479         surf->dcc_size = 0;
 480         surf->dcc_alignment = 1;
 481         surf->htile_size = surf->htile_slice_size = 0;
 482         surf->htile_alignment = 1;
 483
 484         /* Calculate texture layout information. */
 485         for (level = 0; level <= surf->last_level; level++) {
 486                 r = radv_compute_level(ws->addrlib, surf, false, level, type, compressed,
 487                                        &AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut);
 488                 if (r)
 489                         return r;
 490
 491                 if (level == 0) {
 492                         surf->bo_alignment = AddrSurfInfoOut.baseAlign;
 493                         surf->pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
 494                         radv_set_micro_tile_mode(surf, &ws->info);
 495
 496                         /* For 2D modes only. */
 497                         if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
 498                                 surf->bankw = AddrSurfInfoOut.pTileInfo->bankWidth;
 499                                 surf->bankh = AddrSurfInfoOut.pTileInfo->bankHeight;
 500                                 surf->mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio;
 501                                 surf->tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
 502                                 surf->num_banks = AddrSurfInfoOut.pTileInfo->banks;
 503                                 surf->macro_tile_index = AddrSurfInfoOut.macroModeIndex;
 504                         } else {
 505                                 surf->macro_tile_index = 0;
 506                         }
 507                 }
 508         }
 509
 510         /* Calculate texture layout information for stencil. */
 511         if (surf->flags & RADEON_SURF_SBUFFER) {
 512                 AddrSurfInfoIn.bpp = 8;
 513                 AddrSurfInfoIn.flags.depth = 0;
 514                 AddrSurfInfoIn.flags.stencil = 1;
 515                 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
 516                 AddrTileInfoIn.tileSplitBytes = surf->stencil_tile_split;
 517
 518                 for (level = 0; level <= surf->last_level; level++) {
 519                         r = radv_compute_level(ws->addrlib, surf, true, level, type, compressed,
 520                                                &AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut);
 521                         if (r)
 522                                 return r;
 523
 524                         /* DB uses the depth pitch for both stencil and depth. */
 525                         if (surf->stencil_level[level].nblk_x != surf->level[level].nblk_x)
 526                                 surf->stencil_adjusted = true;
 527
 528                         if (level == 0) {
 529                                 /* For 2D modes only. */
 530                                 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
 531                                         surf->stencil_tile_split =
 532                                                 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
 533                                 }
 534                         }
 535                 }
 536         }
 537
 538         /* Recalculate the whole DCC miptree size including disabled levels.
 539          * This is what addrlib does, but calling addrlib would be a lot more
 540          * complicated.
 541          */
 542 #if 0
 543         if (surf->dcc_size && surf->last_level > 0) {
 544                 surf->dcc_size = align64(surf->bo_size >> 8,
 545                                          ws->info.pipe_interleave_bytes *
 546                                          ws->info.num_tile_pipes);
 547         }
 548 #endif
 549         return 0;
 550 }
 551
 552 static int radv_amdgpu_winsys_surface_best(struct radeon_winsys *rws,
 553                                            struct radeon_surf *surf)
 554 {
 555         return 0;
 556 }
 557
 558 void radv_amdgpu_surface_init_functions(struct radv_amdgpu_winsys *ws)
 559 {
 560         ws->base.surface_init = radv_amdgpu_winsys_surface_init;
 561         ws->base.surface_best = radv_amdgpu_winsys_surface_best;
 562 }