src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based on amdgpu winsys.
   6  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   7  * Copyright © 2015 Advanced Micro Devices, Inc.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  26  * IN THE SOFTWARE.
  27  */
  28
  29 #include <errno.h>
  30
  31 #include "radv_private.h"
  32 #include "addrlib/addrinterface.h"
  33 #include "util/bitset.h"
  34 #include "radv_amdgpu_winsys.h"
  35 #include "radv_amdgpu_surface.h"
  36 #include "sid.h"
  37
  38 #ifndef NO_ENTRIES
  39 #define NO_ENTRIES 32
  40 #endif
  41
  42 #ifndef NO_MACRO_ENTRIES
  43 #define NO_MACRO_ENTRIES 16
  44 #endif
  45
  46 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
  47 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
  48 #endif
  49
  50 static int radv_amdgpu_surface_sanity(const struct radeon_surf_info *surf_info,
  51                                       const struct radeon_surf *surf)
  52 {
  53         unsigned type = RADEON_SURF_GET(surf->flags, TYPE);
  54
  55         if (!(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))
  56                 return -EINVAL;
  57
  58         /* all dimension must be at least 1 ! */
  59         if (!surf_info->width || !surf_info->height || !surf_info->depth ||
  60             !surf_info->array_size)
  61                 return -EINVAL;
  62
  63         if (!surf->blk_w || !surf->blk_h)
  64                 return -EINVAL;
  65
  66         switch (surf_info->samples) {
  67         case 1:
  68         case 2:
  69         case 4:
  70         case 8:
  71                 break;
  72         default:
  73                 return -EINVAL;
  74         }
  75
  76         switch (type) {
  77         case RADEON_SURF_TYPE_1D:
  78                 if (surf_info->height > 1)
  79                         return -EINVAL;
  80                 /* fall through */
  81         case RADEON_SURF_TYPE_2D:
  82         case RADEON_SURF_TYPE_CUBEMAP:
  83                 if (surf_info->depth > 1 || surf_info->array_size > 1)
  84                         return -EINVAL;
  85                 break;
  86         case RADEON_SURF_TYPE_3D:
  87                 if (surf_info->array_size > 1)
  88                         return -EINVAL;
  89                 break;
  90         case RADEON_SURF_TYPE_1D_ARRAY:
  91                 if (surf_info->height > 1)
  92                         return -EINVAL;
  93                 /* fall through */
  94         case RADEON_SURF_TYPE_2D_ARRAY:
  95                 if (surf_info->depth > 1)
  96                         return -EINVAL;
  97                 break;
  98         default:
  99                 return -EINVAL;
 100         }
 101         return 0;
 102 }
 103
 104 static void *ADDR_API radv_allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
 105 {
 106         return malloc(pInput->sizeInBytes);
 107 }
 108
 109 static ADDR_E_RETURNCODE ADDR_API radv_freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
 110 {
 111         free(pInput->pVirtAddr);
 112         return ADDR_OK;
 113 }
 114
 115 ADDR_HANDLE radv_amdgpu_addr_create(struct amdgpu_gpu_info *amdinfo, int family, int rev_id,
 116                                     enum chip_class chip_class)
 117 {
 118         ADDR_CREATE_INPUT addrCreateInput = {0};
 119         ADDR_CREATE_OUTPUT addrCreateOutput = {0};
 120         ADDR_REGISTER_VALUE regValue = {0};
 121         ADDR_CREATE_FLAGS createFlags = {{0}};
 122         ADDR_E_RETURNCODE addrRet;
 123
 124         addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
 125         addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
 126
 127         regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
 128         regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
 129         regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
 130
 131         regValue.backendDisables = amdinfo->backend_disable[0];
 132         regValue.pTileConfig = amdinfo->gb_tile_mode;
 133         regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
 134         if (chip_class == SI) {
 135                 regValue.pMacroTileConfig = NULL;
 136                 regValue.noOfMacroEntries = 0;
 137         } else {
 138                 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
 139                 regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
 140         }
 141
 142         createFlags.value = 0;
 143         createFlags.useTileIndex = 1;
 144
 145         addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
 146         addrCreateInput.chipFamily = family;
 147         addrCreateInput.chipRevision = rev_id;
 148         addrCreateInput.createFlags = createFlags;
 149         addrCreateInput.callbacks.allocSysMem = radv_allocSysMem;
 150         addrCreateInput.callbacks.freeSysMem = radv_freeSysMem;
 151         addrCreateInput.callbacks.debugPrint = 0;
 152         addrCreateInput.regValue = regValue;
 153
 154         addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
 155         if (addrRet != ADDR_OK)
 156                 return NULL;
 157
 158         return addrCreateOutput.hLib;
 159 }
 160
 161 static int radv_compute_level(ADDR_HANDLE addrlib,
 162                               const struct radeon_surf_info *surf_info,
 163                               struct radeon_surf *surf, bool is_stencil,
 164                               unsigned level, unsigned type, bool compressed,
 165                               ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
 166                               ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
 167                               ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
 168                               ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut)
 169 {
 170         struct radeon_surf_level *surf_level;
 171         ADDR_E_RETURNCODE ret;
 172
 173         AddrSurfInfoIn->mipLevel = level;
 174         AddrSurfInfoIn->width = u_minify(surf_info->width, level);
 175         AddrSurfInfoIn->height = u_minify(surf_info->height, level);
 176
 177         if (type == RADEON_SURF_TYPE_3D)
 178                 AddrSurfInfoIn->numSlices = u_minify(surf_info->depth, level);
 179         else if (type == RADEON_SURF_TYPE_CUBEMAP)
 180                 AddrSurfInfoIn->numSlices = 6;
 181         else
 182                 AddrSurfInfoIn->numSlices = surf_info->array_size;
 183
 184         if (level > 0) {
 185                 /* Set the base level pitch. This is needed for calculation
 186                  * of non-zero levels. */
 187                 if (is_stencil)
 188                         AddrSurfInfoIn->basePitch = surf->stencil_level[0].nblk_x;
 189                 else
 190                         AddrSurfInfoIn->basePitch = surf->level[0].nblk_x;
 191
 192                 /* Convert blocks to pixels for compressed formats. */
 193                 if (compressed)
 194                         AddrSurfInfoIn->basePitch *= surf->blk_w;
 195         }
 196
 197         ret = AddrComputeSurfaceInfo(addrlib,
 198                                      AddrSurfInfoIn,
 199                                      AddrSurfInfoOut);
 200         if (ret != ADDR_OK)
 201                 return ret;
 202
 203         surf_level = is_stencil ? &surf->stencil_level[level] : &surf->level[level];
 204         surf_level->offset = align64(surf->bo_size, AddrSurfInfoOut->baseAlign);
 205         surf_level->slice_size = AddrSurfInfoOut->sliceSize;
 206         surf_level->pitch_bytes = AddrSurfInfoOut->pitch * (is_stencil ? 1 : surf->bpe);
 207         surf_level->npix_x = u_minify(surf_info->width, level);
 208         surf_level->npix_y = u_minify(surf_info->height, level);
 209         surf_level->npix_z = u_minify(surf_info->depth, level);
 210         surf_level->nblk_x = AddrSurfInfoOut->pitch;
 211         surf_level->nblk_y = AddrSurfInfoOut->height;
 212         if (type == RADEON_SURF_TYPE_3D)
 213                 surf_level->nblk_z = AddrSurfInfoOut->depth;
 214         else
 215                 surf_level->nblk_z = 1;
 216
 217         switch (AddrSurfInfoOut->tileMode) {
 218         case ADDR_TM_LINEAR_ALIGNED:
 219                 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
 220                 break;
 221         case ADDR_TM_1D_TILED_THIN1:
 222                 surf_level->mode = RADEON_SURF_MODE_1D;
 223                 break;
 224         case ADDR_TM_2D_TILED_THIN1:
 225                 surf_level->mode = RADEON_SURF_MODE_2D;
 226                 break;
 227         default:
 228                 assert(0);
 229         }
 230
 231         if (is_stencil)
 232                 surf->stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
 233         else
 234                 surf->tiling_index[level] = AddrSurfInfoOut->tileIndex;
 235
 236         surf->bo_size = surf_level->offset + AddrSurfInfoOut->surfSize;
 237
 238         /* Clear DCC fields at the beginning. */
 239         surf_level->dcc_offset = 0;
 240         surf_level->dcc_enabled = false;
 241
 242         /* The previous level's flag tells us if we can use DCC for this level. */
 243         if (AddrSurfInfoIn->flags.dccCompatible &&
 244             (level == 0 || AddrDccOut->subLvlCompressible)) {
 245                 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
 246                 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
 247                 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
 248                 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
 249                 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
 250
 251                 ret = AddrComputeDccInfo(addrlib,
 252                                          AddrDccIn,
 253                                          AddrDccOut);
 254
 255                 if (ret == ADDR_OK) {
 256                         surf_level->dcc_offset = surf->dcc_size;
 257                         surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
 258                         surf_level->dcc_enabled = true;
 259                         surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
 260                         surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
 261                 }
 262         }
 263
 264         if (!is_stencil && AddrSurfInfoIn->flags.depth &&
 265             surf_level->mode == RADEON_SURF_MODE_2D && level == 0) {
 266                 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
 267                 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
 268                 AddrHtileIn.flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
 269                 AddrHtileIn.pitch = AddrSurfInfoOut->pitch;
 270                 AddrHtileIn.height = AddrSurfInfoOut->height;
 271                 AddrHtileIn.numSlices = AddrSurfInfoOut->depth;
 272                 AddrHtileIn.blockWidth = ADDR_HTILE_BLOCKSIZE_8;
 273                 AddrHtileIn.blockHeight = ADDR_HTILE_BLOCKSIZE_8;
 274                 AddrHtileIn.pTileInfo = AddrSurfInfoOut->pTileInfo;
 275                 AddrHtileIn.tileIndex = AddrSurfInfoOut->tileIndex;
 276                 AddrHtileIn.macroModeIndex = AddrSurfInfoOut->macroModeIndex;
 277
 278                 ret = AddrComputeHtileInfo(addrlib,
 279                                            &AddrHtileIn,
 280                                            &AddrHtileOut);
 281
 282                 if (ret == ADDR_OK) {
 283                         surf->htile_size = AddrHtileOut.htileBytes;
 284                         surf->htile_slice_size = AddrHtileOut.sliceSize;
 285                         surf->htile_alignment = AddrHtileOut.baseAlign;
 286                 }
 287         }
 288         return 0;
 289 }
 290
 291 static void radv_set_micro_tile_mode(struct radeon_surf *surf,
 292                                      struct radeon_info *info)
 293 {
 294         uint32_t tile_mode = info->si_tile_mode_array[surf->tiling_index[0]];
 295
 296         if (info->chip_class >= CIK)
 297                 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
 298         else
 299                 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
 300 }
 301
 302 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
 303 {
 304         unsigned index, tileb;
 305
 306         tileb = 8 * 8 * surf->bpe;
 307         tileb = MIN2(surf->tile_split, tileb);
 308
 309         for (index = 0; tileb > 64; index++)
 310                 tileb >>= 1;
 311
 312         assert(index < 16);
 313         return index;
 314 }
 315
 316 static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
 317                                            const struct radeon_surf_info *surf_info,
 318                                            struct radeon_surf *surf)
 319 {
 320         struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
 321         unsigned level, mode, type;
 322         bool compressed;
 323         ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
 324         ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
 325         ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
 326         ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
 327         ADDR_TILEINFO AddrTileInfoIn = {0};
 328         ADDR_TILEINFO AddrTileInfoOut = {0};
 329         int r;
 330         uint32_t last_level = surf_info->levels - 1;
 331
 332         r = radv_amdgpu_surface_sanity(surf_info, surf);
 333         if (r)
 334                 return r;
 335
 336         AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
 337         AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
 338         AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
 339         AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
 340         AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
 341
 342         type = RADEON_SURF_GET(surf->flags, TYPE);
 343         mode = RADEON_SURF_GET(surf->flags, MODE);
 344         compressed = surf->blk_w == 4 && surf->blk_h == 4;
 345
 346         /* MSAA and FMASK require 2D tiling. */
 347         if (surf_info->samples > 1 ||
 348             (surf->flags & RADEON_SURF_FMASK))
 349                 mode = RADEON_SURF_MODE_2D;
 350
 351         /* DB doesn't support linear layouts. */
 352         if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
 353             mode < RADEON_SURF_MODE_1D)
 354                 mode = RADEON_SURF_MODE_1D;
 355
 356         /* Set the requested tiling mode. */
 357         switch (mode) {
 358         case RADEON_SURF_MODE_LINEAR_ALIGNED:
 359                 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
 360                 break;
 361         case RADEON_SURF_MODE_1D:
 362                 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
 363                 break;
 364         case RADEON_SURF_MODE_2D:
 365                 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
 366                 break;
 367         default:
 368                 assert(0);
 369         }
 370
 371         /* The format must be set correctly for the allocation of compressed
 372          * textures to work. In other cases, setting the bpp is sufficient. */
 373         if (compressed) {
 374                 switch (surf->bpe) {
 375                 case 8:
 376                         AddrSurfInfoIn.format = ADDR_FMT_BC1;
 377                         break;
 378                 case 16:
 379                         AddrSurfInfoIn.format = ADDR_FMT_BC3;
 380                         break;
 381                 default:
 382                         assert(0);
 383                 }
 384         } else {
 385                 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
 386         }
 387
 388         AddrDccIn.numSamples = AddrSurfInfoIn.numSamples = surf_info->samples;
 389         AddrSurfInfoIn.tileIndex = -1;
 390
 391         /* Set the micro tile type. */
 392         if (surf->flags & RADEON_SURF_SCANOUT)
 393                 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
 394         else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
 395                 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
 396         else
 397                 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
 398
 399         AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
 400         AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
 401         AddrSurfInfoIn.flags.cube = type == RADEON_SURF_TYPE_CUBEMAP;
 402         AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
 403         AddrSurfInfoIn.flags.pow2Pad = last_level > 0;
 404         AddrSurfInfoIn.flags.opt4Space = 1;
 405
 406         /* DCC notes:
 407          * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
 408          *   with samples >= 4.
 409          * - Mipmapped array textures have low performance (discovered by a closed
 410          *   driver team).
 411          */
 412         AddrSurfInfoIn.flags.dccCompatible = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
 413                 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
 414                 !compressed && AddrDccIn.numSamples <= 1 &&
 415                 ((surf_info->array_size == 1 && surf_info->depth == 1) ||
 416                  last_level == 0);
 417
 418         AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
 419         AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
 420
 421         /* noStencil = 0 can result in a depth part that is incompatible with
 422          * mipmapped texturing. So set noStencil = 1 when mipmaps are requested (in
 423          * this case, we may end up setting stencil_adjusted).
 424          *
 425          * TODO: update addrlib to a newer version, remove this, and
 426          * use flags.matchStencilTileCfg = 1 as an alternative fix.
 427          */
 428         if (last_level > 0)
 429                 AddrSurfInfoIn.flags.noStencil = 1;
 430
 431         /* Set preferred macrotile parameters. This is usually required
 432          * for shared resources. This is for 2D tiling only. */
 433         if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
 434             surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) {
 435                 /* If any of these parameters are incorrect, the calculation
 436                  * will fail. */
 437                 AddrTileInfoIn.banks = surf->num_banks;
 438                 AddrTileInfoIn.bankWidth = surf->bankw;
 439                 AddrTileInfoIn.bankHeight = surf->bankh;
 440                 AddrTileInfoIn.macroAspectRatio = surf->mtilea;
 441                 AddrTileInfoIn.tileSplitBytes = surf->tile_split;
 442                 AddrTileInfoIn.pipeConfig = surf->pipe_config + 1; /* +1 compared to GB_TILE_MODE */
 443                 AddrSurfInfoIn.flags.opt4Space = 0;
 444                 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
 445
 446                 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
 447                  * the tile index, because we are expected to know it if
 448                  * we know the other parameters.
 449                  *
 450                  * This is something that can easily be fixed in Addrlib.
 451                  * For now, just figure it out here.
 452                  * Note that only 2D_TILE_THIN1 is handled here.
 453                  */
 454                 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
 455                 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
 456
 457                 if (ws->info.chip_class == SI) {
 458                         if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
 459                                 if (surf->bpe == 2)
 460                                         AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
 461                                 else
 462                                         AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
 463                         } else {
 464                                 if (surf->bpe == 1)
 465                                         AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
 466                                 else if (surf->bpe == 2)
 467                                         AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
 468                                 else if (surf->bpe == 4)
 469                                         AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
 470                                 else
 471                                         AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
 472                         }
 473                 } else {
 474                         if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
 475                                 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
 476                         else
 477                                 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
 478                         AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
 479                 }
 480         }
 481
 482         surf->bo_size = 0;
 483         surf->dcc_size = 0;
 484         surf->dcc_alignment = 1;
 485         surf->htile_size = surf->htile_slice_size = 0;
 486         surf->htile_alignment = 1;
 487
 488         /* Calculate texture layout information. */
 489         for (level = 0; level <= last_level; level++) {
 490                 r = radv_compute_level(ws->addrlib, surf_info, surf, false, level, type, compressed,
 491                                        &AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut);
 492                 if (r)
 493                         break;
 494
 495                 if (level == 0) {
 496                         surf->bo_alignment = AddrSurfInfoOut.baseAlign;
 497                         surf->pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
 498                         radv_set_micro_tile_mode(surf, &ws->info);
 499
 500                         /* For 2D modes only. */
 501                         if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
 502                                 surf->bankw = AddrSurfInfoOut.pTileInfo->bankWidth;
 503                                 surf->bankh = AddrSurfInfoOut.pTileInfo->bankHeight;
 504                                 surf->mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio;
 505                                 surf->tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
 506                                 surf->num_banks = AddrSurfInfoOut.pTileInfo->banks;
 507                                 surf->macro_tile_index = AddrSurfInfoOut.macroModeIndex;
 508                         } else {
 509                                 surf->macro_tile_index = 0;
 510                         }
 511                 }
 512         }
 513
 514         /* Calculate texture layout information for stencil. */
 515         if (surf->flags & RADEON_SURF_SBUFFER) {
 516                 AddrSurfInfoIn.bpp = 8;
 517                 AddrSurfInfoIn.flags.depth = 0;
 518                 AddrSurfInfoIn.flags.stencil = 1;
 519                 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
 520                 AddrTileInfoIn.tileSplitBytes = surf->stencil_tile_split;
 521
 522                 for (level = 0; level <= last_level; level++) {
 523                         r = radv_compute_level(ws->addrlib, surf_info, surf, true, level, type, compressed,
 524                                                &AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut);
 525                         if (r)
 526                                 return r;
 527
 528                         /* DB uses the depth pitch for both stencil and depth. */
 529                         if (surf->stencil_level[level].nblk_x != surf->level[level].nblk_x)
 530                                 surf->stencil_adjusted = true;
 531
 532                         if (level == 0) {
 533                                 /* For 2D modes only. */
 534                                 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
 535                                         surf->stencil_tile_split =
 536                                                 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
 537                                 }
 538                         }
 539                 }
 540         }
 541
 542         /* Recalculate the whole DCC miptree size including disabled levels.
 543          * This is what addrlib does, but calling addrlib would be a lot more
 544          * complicated.
 545          */
 546 #if 0
 547         if (surf->dcc_size && last_level > 0) {
 548                 surf->dcc_size = align64(surf->bo_size >> 8,
 549                                          ws->info.pipe_interleave_bytes *
 550                                          ws->info.num_tile_pipes);
 551         }
 552 #endif
 553         return 0;
 554 }
 555
 556 static int radv_amdgpu_winsys_surface_best(struct radeon_winsys *rws,
 557                                            struct radeon_surf *surf)
 558 {
 559         return 0;
 560 }
 561
 562 void radv_amdgpu_surface_init_functions(struct radv_amdgpu_winsys *ws)
 563 {
 564         ws->base.surface_init = radv_amdgpu_winsys_surface_init;
 565         ws->base.surface_best = radv_amdgpu_winsys_surface_best;
 566 }