src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based on amdgpu winsys.
   6  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   7  * Copyright © 2015 Advanced Micro Devices, Inc.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  26  * IN THE SOFTWARE.
  27  */
  28
  29 #include <errno.h>
  30
  31 #include "radv_private.h"
  32 #include "addrlib/addrinterface.h"
  33 #include "util/bitset.h"
  34 #include "radv_amdgpu_winsys.h"
  35 #include "radv_amdgpu_surface.h"
  36 #include "sid.h"
  37
  38 #include "ac_surface.h"
  39
  40 static int radv_amdgpu_surface_sanity(const struct ac_surf_info *surf_info,
  41                                       const struct radeon_surf *surf)
  42 {
  43         unsigned type = RADEON_SURF_GET(surf->flags, TYPE);
  44
  45         if (!(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))
  46                 return -EINVAL;
  47
  48         /* all dimension must be at least 1 ! */
  49         if (!surf_info->width || !surf_info->height || !surf_info->depth ||
  50             !surf_info->array_size)
  51                 return -EINVAL;
  52
  53         if (!surf->blk_w || !surf->blk_h)
  54                 return -EINVAL;
  55
  56         switch (surf_info->samples) {
  57         case 1:
  58         case 2:
  59         case 4:
  60         case 8:
  61                 break;
  62         default:
  63                 return -EINVAL;
  64         }
  65
  66         switch (type) {
  67         case RADEON_SURF_TYPE_1D:
  68                 if (surf_info->height > 1)
  69                         return -EINVAL;
  70                 /* fall through */
  71         case RADEON_SURF_TYPE_2D:
  72         case RADEON_SURF_TYPE_CUBEMAP:
  73                 if (surf_info->depth > 1 || surf_info->array_size > 1)
  74                         return -EINVAL;
  75                 break;
  76         case RADEON_SURF_TYPE_3D:
  77                 if (surf_info->array_size > 1)
  78                         return -EINVAL;
  79                 break;
  80         case RADEON_SURF_TYPE_1D_ARRAY:
  81                 if (surf_info->height > 1)
  82                         return -EINVAL;
  83                 /* fall through */
  84         case RADEON_SURF_TYPE_2D_ARRAY:
  85                 if (surf_info->depth > 1)
  86                         return -EINVAL;
  87                 break;
  88         default:
  89                 return -EINVAL;
  90         }
  91         return 0;
  92 }
  93
  94 static int radv_compute_level(ADDR_HANDLE addrlib,
  95                               const struct ac_surf_info *surf_info,
  96                               struct radeon_surf *surf, bool is_stencil,
  97                               unsigned level, unsigned type, bool compressed,
  98                               ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
  99                               ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
 100                               ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
 101                               ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut)
 102 {
 103         struct legacy_surf_level *surf_level;
 104         ADDR_E_RETURNCODE ret;
 105
 106         AddrSurfInfoIn->mipLevel = level;
 107         AddrSurfInfoIn->width = u_minify(surf_info->width, level);
 108         AddrSurfInfoIn->height = u_minify(surf_info->height, level);
 109
 110         if (type == RADEON_SURF_TYPE_3D)
 111                 AddrSurfInfoIn->numSlices = u_minify(surf_info->depth, level);
 112         else if (type == RADEON_SURF_TYPE_CUBEMAP)
 113                 AddrSurfInfoIn->numSlices = 6;
 114         else
 115                 AddrSurfInfoIn->numSlices = surf_info->array_size;
 116
 117         if (level > 0) {
 118                 /* Set the base level pitch. This is needed for calculation
 119                  * of non-zero levels. */
 120                 if (is_stencil)
 121                         AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
 122                 else
 123                         AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
 124
 125                 /* Convert blocks to pixels for compressed formats. */
 126                 if (compressed)
 127                         AddrSurfInfoIn->basePitch *= surf->blk_w;
 128         }
 129
 130         ret = AddrComputeSurfaceInfo(addrlib,
 131                                      AddrSurfInfoIn,
 132                                      AddrSurfInfoOut);
 133         if (ret != ADDR_OK)
 134                 return ret;
 135
 136         surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
 137         surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
 138         surf_level->slice_size = AddrSurfInfoOut->sliceSize;
 139         surf_level->nblk_x = AddrSurfInfoOut->pitch;
 140         surf_level->nblk_y = AddrSurfInfoOut->height;
 141
 142         switch (AddrSurfInfoOut->tileMode) {
 143         case ADDR_TM_LINEAR_ALIGNED:
 144                 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
 145                 break;
 146         case ADDR_TM_1D_TILED_THIN1:
 147                 surf_level->mode = RADEON_SURF_MODE_1D;
 148                 break;
 149         case ADDR_TM_2D_TILED_THIN1:
 150                 surf_level->mode = RADEON_SURF_MODE_2D;
 151                 break;
 152         default:
 153                 assert(0);
 154         }
 155
 156         if (is_stencil)
 157                 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
 158         else
 159                 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
 160
 161         surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
 162
 163         /* Clear DCC fields at the beginning. */
 164         surf_level->dcc_offset = 0;
 165
 166         /* The previous level's flag tells us if we can use DCC for this level. */
 167         if (AddrSurfInfoIn->flags.dccCompatible &&
 168             (level == 0 || AddrDccOut->subLvlCompressible)) {
 169                 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
 170                 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
 171                 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
 172                 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
 173                 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
 174
 175                 ret = AddrComputeDccInfo(addrlib,
 176                                          AddrDccIn,
 177                                          AddrDccOut);
 178
 179                 if (ret == ADDR_OK) {
 180                         surf_level->dcc_offset = surf->dcc_size;
 181                         surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
 182                         surf->num_dcc_levels = level + 1;
 183                         surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
 184                         surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
 185                 }
 186         }
 187
 188         if (!is_stencil && AddrSurfInfoIn->flags.depth &&
 189             surf_level->mode == RADEON_SURF_MODE_2D && level == 0) {
 190                 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
 191                 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
 192                 AddrHtileIn.flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
 193                 AddrHtileIn.pitch = AddrSurfInfoOut->pitch;
 194                 AddrHtileIn.height = AddrSurfInfoOut->height;
 195                 AddrHtileIn.numSlices = AddrSurfInfoOut->depth;
 196                 AddrHtileIn.blockWidth = ADDR_HTILE_BLOCKSIZE_8;
 197                 AddrHtileIn.blockHeight = ADDR_HTILE_BLOCKSIZE_8;
 198                 AddrHtileIn.pTileInfo = AddrSurfInfoOut->pTileInfo;
 199                 AddrHtileIn.tileIndex = AddrSurfInfoOut->tileIndex;
 200                 AddrHtileIn.macroModeIndex = AddrSurfInfoOut->macroModeIndex;
 201
 202                 ret = AddrComputeHtileInfo(addrlib,
 203                                            &AddrHtileIn,
 204                                            &AddrHtileOut);
 205
 206                 if (ret == ADDR_OK) {
 207                         surf->htile_size = AddrHtileOut.htileBytes;
 208                         surf->htile_slice_size = AddrHtileOut.sliceSize;
 209                         surf->htile_alignment = AddrHtileOut.baseAlign;
 210                 }
 211         }
 212         return 0;
 213 }
 214
 215 static void radv_set_micro_tile_mode(struct radeon_surf *surf,
 216                                      struct radeon_info *info)
 217 {
 218         uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
 219
 220         if (info->chip_class >= CIK)
 221                 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
 222         else
 223                 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
 224 }
 225
 226 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
 227 {
 228         unsigned index, tileb;
 229
 230         tileb = 8 * 8 * surf->bpe;
 231         tileb = MIN2(surf->u.legacy.tile_split, tileb);
 232
 233         for (index = 0; tileb > 64; index++)
 234                 tileb >>= 1;
 235
 236         assert(index < 16);
 237         return index;
 238 }
 239
 240 static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
 241                                            const struct ac_surf_info *surf_info,
 242                                            struct radeon_surf *surf)
 243 {
 244         struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
 245         unsigned level, mode, type;
 246         bool compressed;
 247         ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
 248         ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
 249         ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
 250         ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
 251         ADDR_TILEINFO AddrTileInfoIn = {0};
 252         ADDR_TILEINFO AddrTileInfoOut = {0};
 253         int r;
 254         uint32_t last_level = surf_info->levels - 1;
 255
 256         r = radv_amdgpu_surface_sanity(surf_info, surf);
 257         if (r)
 258                 return r;
 259
 260         AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
 261         AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
 262         AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
 263         AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
 264         AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
 265
 266         type = RADEON_SURF_GET(surf->flags, TYPE);
 267         mode = RADEON_SURF_GET(surf->flags, MODE);
 268         compressed = surf->blk_w == 4 && surf->blk_h == 4;
 269
 270         /* MSAA and FMASK require 2D tiling. */
 271         if (surf_info->samples > 1 ||
 272             (surf->flags & RADEON_SURF_FMASK))
 273                 mode = RADEON_SURF_MODE_2D;
 274
 275         /* DB doesn't support linear layouts. */
 276         if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
 277             mode < RADEON_SURF_MODE_1D)
 278                 mode = RADEON_SURF_MODE_1D;
 279
 280         /* Set the requested tiling mode. */
 281         switch (mode) {
 282         case RADEON_SURF_MODE_LINEAR_ALIGNED:
 283                 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
 284                 break;
 285         case RADEON_SURF_MODE_1D:
 286                 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
 287                 break;
 288         case RADEON_SURF_MODE_2D:
 289                 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
 290                 break;
 291         default:
 292                 assert(0);
 293         }
 294
 295         /* The format must be set correctly for the allocation of compressed
 296          * textures to work. In other cases, setting the bpp is sufficient. */
 297         if (compressed) {
 298                 switch (surf->bpe) {
 299                 case 8:
 300                         AddrSurfInfoIn.format = ADDR_FMT_BC1;
 301                         break;
 302                 case 16:
 303                         AddrSurfInfoIn.format = ADDR_FMT_BC3;
 304                         break;
 305                 default:
 306                         assert(0);
 307                 }
 308         } else {
 309                 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
 310         }
 311
 312         AddrDccIn.numSamples = AddrSurfInfoIn.numSamples = surf_info->samples;
 313         AddrSurfInfoIn.tileIndex = -1;
 314
 315         /* Set the micro tile type. */
 316         if (surf->flags & RADEON_SURF_SCANOUT)
 317                 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
 318         else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
 319                 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
 320         else
 321                 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
 322
 323         AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
 324         AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
 325         AddrSurfInfoIn.flags.cube = type == RADEON_SURF_TYPE_CUBEMAP;
 326         AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
 327         AddrSurfInfoIn.flags.pow2Pad = last_level > 0;
 328         AddrSurfInfoIn.flags.opt4Space = 1;
 329
 330         /* DCC notes:
 331          * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
 332          *   with samples >= 4.
 333          * - Mipmapped array textures have low performance (discovered by a closed
 334          *   driver team).
 335          */
 336         AddrSurfInfoIn.flags.dccCompatible = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
 337                 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
 338                 !compressed && AddrDccIn.numSamples <= 1 &&
 339                 ((surf_info->array_size == 1 && surf_info->depth == 1) ||
 340                  last_level == 0);
 341
 342         AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
 343         AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
 344
 345         /* noStencil = 0 can result in a depth part that is incompatible with
 346          * mipmapped texturing. So set noStencil = 1 when mipmaps are requested (in
 347          * this case, we may end up setting stencil_adjusted).
 348          *
 349          * TODO: update addrlib to a newer version, remove this, and
 350          * use flags.matchStencilTileCfg = 1 as an alternative fix.
 351          */
 352         if (last_level > 0)
 353                 AddrSurfInfoIn.flags.noStencil = 1;
 354
 355         /* Set preferred macrotile parameters. This is usually required
 356          * for shared resources. This is for 2D tiling only. */
 357         if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
 358             surf->u.legacy.bankw && surf->u.legacy.bankh && surf->u.legacy.mtilea &&
 359             surf->u.legacy.tile_split) {
 360                 /* If any of these parameters are incorrect, the calculation
 361                  * will fail. */
 362                 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
 363                 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
 364                 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
 365                 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
 366                 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
 367                 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
 368                 AddrSurfInfoIn.flags.opt4Space = 0;
 369                 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
 370
 371                 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
 372                  * the tile index, because we are expected to know it if
 373                  * we know the other parameters.
 374                  *
 375                  * This is something that can easily be fixed in Addrlib.
 376                  * For now, just figure it out here.
 377                  * Note that only 2D_TILE_THIN1 is handled here.
 378                  */
 379                 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
 380                 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
 381
 382                 if (ws->info.chip_class == SI) {
 383                         if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
 384                                 if (surf->bpe == 2)
 385                                         AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
 386                                 else
 387                                         AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
 388                         } else {
 389                                 if (surf->bpe == 1)
 390                                         AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
 391                                 else if (surf->bpe == 2)
 392                                         AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
 393                                 else if (surf->bpe == 4)
 394                                         AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
 395                                 else
 396                                         AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
 397                         }
 398                 } else {
 399                         if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
 400                                 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
 401                         else
 402                                 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
 403                         AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
 404                 }
 405         }
 406
 407         surf->surf_size = 0;
 408         surf->num_dcc_levels = 0;
 409         surf->dcc_size = 0;
 410         surf->dcc_alignment = 1;
 411         surf->htile_size = surf->htile_slice_size = 0;
 412         surf->htile_alignment = 1;
 413
 414         /* Calculate texture layout information. */
 415         for (level = 0; level <= last_level; level++) {
 416                 r = radv_compute_level(ws->addrlib, surf_info, surf, false, level, type, compressed,
 417                                        &AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut);
 418                 if (r)
 419                         break;
 420
 421                 if (level == 0) {
 422                         surf->surf_alignment = AddrSurfInfoOut.baseAlign;
 423                         surf->u.legacy.pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
 424                         radv_set_micro_tile_mode(surf, &ws->info);
 425
 426                         /* For 2D modes only. */
 427                         if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
 428                                 surf->u.legacy.bankw = AddrSurfInfoOut.pTileInfo->bankWidth;
 429                                 surf->u.legacy.bankh = AddrSurfInfoOut.pTileInfo->bankHeight;
 430                                 surf->u.legacy.mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio;
 431                                 surf->u.legacy.tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
 432                                 surf->u.legacy.num_banks = AddrSurfInfoOut.pTileInfo->banks;
 433                                 surf->u.legacy.macro_tile_index = AddrSurfInfoOut.macroModeIndex;
 434                         } else {
 435                                 surf->u.legacy.macro_tile_index = 0;
 436                         }
 437                 }
 438         }
 439
 440         /* Calculate texture layout information for stencil. */
 441         if (surf->flags & RADEON_SURF_SBUFFER) {
 442                 AddrSurfInfoIn.bpp = 8;
 443                 AddrSurfInfoIn.flags.depth = 0;
 444                 AddrSurfInfoIn.flags.stencil = 1;
 445                 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
 446                 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
 447
 448                 for (level = 0; level <= last_level; level++) {
 449                         r = radv_compute_level(ws->addrlib, surf_info, surf, true, level, type, compressed,
 450                                                &AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut);
 451                         if (r)
 452                                 return r;
 453
 454                         /* DB uses the depth pitch for both stencil and depth. */
 455                         if (surf->u.legacy.stencil_level[level].nblk_x != surf->u.legacy.level[level].nblk_x)
 456                                 surf->u.legacy.stencil_adjusted = true;
 457
 458                         if (level == 0) {
 459                                 /* For 2D modes only. */
 460                                 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
 461                                         surf->u.legacy.stencil_tile_split =
 462                                                 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
 463                                 }
 464                         }
 465                 }
 466         }
 467
 468         /* Recalculate the whole DCC miptree size including disabled levels.
 469          * This is what addrlib does, but calling addrlib would be a lot more
 470          * complicated.
 471          */
 472 #if 0
 473         if (surf->dcc_size && last_level > 0) {
 474                 surf->dcc_size = align64(surf->bo_size >> 8,
 475                                          ws->info.pipe_interleave_bytes *
 476                                          ws->info.num_tile_pipes);
 477         }
 478 #endif
 479         return 0;
 480 }
 481
 482 static int radv_amdgpu_winsys_surface_best(struct radeon_winsys *rws,
 483                                            struct radeon_surf *surf)
 484 {
 485         return 0;
 486 }
 487
 488 void radv_amdgpu_surface_init_functions(struct radv_amdgpu_winsys *ws)
 489 {
 490         ws->base.surface_init = radv_amdgpu_winsys_surface_init;
 491         ws->base.surface_best = radv_amdgpu_winsys_surface_best;
 492 }