src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  * based on amdgpu winsys.
   5  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   6  * Copyright © 2015 Advanced Micro Devices, Inc.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27 #include "radv_amdgpu_winsys.h"
  28 #include "radv_amdgpu_winsys_public.h"
  29 #include "radv_amdgpu_surface.h"
  30 #include "radv_debug.h"
  31 #include "ac_surface.h"
  32 #include "xf86drm.h"
  33 #include <stdio.h>
  34 #include <stdlib.h>
  35 #include <string.h>
  36 #include <amdgpu_drm.h>
  37 #include <assert.h>
  38 #include "radv_amdgpu_cs.h"
  39 #include "radv_amdgpu_bo.h"
  40 #include "radv_amdgpu_surface.h"
  41
  42 static bool
  43 do_winsys_init(struct radv_amdgpu_winsys *ws, int fd)
  44 {
  45         if (!ac_query_gpu_info(fd, ws->dev, &ws->info, &ws->amdinfo))
  46                 return false;
  47
  48         /* temporary */
  49         ws->info.use_display_dcc_unaligned = false;
  50         ws->info.use_display_dcc_with_retile_blit = false;
  51
  52         ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo, &ws->info.max_alignment);
  53         if (!ws->addrlib) {
  54                 fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
  55                 return false;
  56         }
  57
  58         ws->info.num_sdma_rings = MIN2(ws->info.num_sdma_rings, MAX_RINGS_PER_TYPE);
  59         ws->info.num_compute_rings = MIN2(ws->info.num_compute_rings, MAX_RINGS_PER_TYPE);
  60
  61         ws->use_ib_bos = ws->info.chip_class >= CIK;
  62         return true;
  63 }
  64
  65 static void radv_amdgpu_winsys_query_info(struct radeon_winsys *rws,
  66                                      struct radeon_info *info)
  67 {
  68         *info = ((struct radv_amdgpu_winsys *)rws)->info;
  69 }
  70
  71 static uint64_t radv_amdgpu_winsys_query_value(struct radeon_winsys *rws,
  72                                                enum radeon_value_id value)
  73 {
  74         struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys *)rws;
  75         struct amdgpu_heap_info heap;
  76         uint64_t retval = 0;
  77
  78         switch (value) {
  79         case RADEON_ALLOCATED_VRAM:
  80                 return ws->allocated_vram;
  81         case RADEON_ALLOCATED_VRAM_VIS:
  82                 return ws->allocated_vram_vis;
  83         case RADEON_ALLOCATED_GTT:
  84                 return ws->allocated_gtt;
  85         case RADEON_TIMESTAMP:
  86                 amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
  87                 return retval;
  88         case RADEON_NUM_BYTES_MOVED:
  89                 amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED,
  90                                   8, &retval);
  91                 return retval;
  92         case RADEON_NUM_EVICTIONS:
  93                 amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_EVICTIONS,
  94                                   8, &retval);
  95                 return retval;
  96         case RADEON_NUM_VRAM_CPU_PAGE_FAULTS:
  97                 amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS,
  98                                   8, &retval);
  99                 return retval;
 100         case RADEON_VRAM_USAGE:
 101                 amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
 102                                        0, &heap);
 103                 return heap.heap_usage;
 104         case RADEON_VRAM_VIS_USAGE:
 105                 amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
 106                                        AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 107                                        &heap);
 108                 return heap.heap_usage;
 109         case RADEON_GTT_USAGE:
 110                 amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT,
 111                                        0, &heap);
 112                 return heap.heap_usage;
 113         case RADEON_GPU_TEMPERATURE:
 114                 amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GPU_TEMP,
 115                                          4, &retval);
 116                 return retval;
 117         case RADEON_CURRENT_SCLK:
 118                 amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_SCLK,
 119                                          4, &retval);
 120                 return retval;
 121         case RADEON_CURRENT_MCLK:
 122                 amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_MCLK,
 123                                          4, &retval);
 124                 return retval;
 125         default:
 126                 unreachable("invalid query value");
 127         }
 128
 129         return 0;
 130 }
 131
 132 static bool radv_amdgpu_winsys_read_registers(struct radeon_winsys *rws,
 133                                               unsigned reg_offset,
 134                                               unsigned num_registers, uint32_t *out)
 135 {
 136         struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys*)rws;
 137
 138         return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
 139                                         0xffffffff, 0, out) == 0;
 140 }
 141
 142 static const char *radv_amdgpu_winsys_get_chip_name(struct radeon_winsys *rws)
 143 {
 144         amdgpu_device_handle dev = ((struct radv_amdgpu_winsys *)rws)->dev;
 145
 146         return amdgpu_get_marketing_name(dev);
 147 }
 148
 149 static void radv_amdgpu_winsys_destroy(struct radeon_winsys *rws)
 150 {
 151         struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys*)rws;
 152
 153         AddrDestroy(ws->addrlib);
 154         amdgpu_device_deinitialize(ws->dev);
 155         FREE(rws);
 156 }
 157
 158 struct radeon_winsys *
 159 radv_amdgpu_winsys_create(int fd, uint64_t debug_flags, uint64_t perftest_flags)
 160 {
 161         uint32_t drm_major, drm_minor, r;
 162         amdgpu_device_handle dev;
 163         struct radv_amdgpu_winsys *ws;
 164
 165         r = amdgpu_device_initialize(fd, &drm_major, &drm_minor, &dev);
 166         if (r)
 167                 return NULL;
 168
 169         ws = calloc(1, sizeof(struct radv_amdgpu_winsys));
 170         if (!ws)
 171                 goto fail;
 172
 173         ws->dev = dev;
 174         ws->info.drm_major = drm_major;
 175         ws->info.drm_minor = drm_minor;
 176         if (!do_winsys_init(ws, fd))
 177                 goto winsys_fail;
 178
 179         ws->debug_all_bos = !!(debug_flags & RADV_DEBUG_ALL_BOS);
 180         if (debug_flags & RADV_DEBUG_NO_IBS)
 181                 ws->use_ib_bos = false;
 182
 183         ws->use_local_bos = perftest_flags & RADV_PERFTEST_LOCAL_BOS;
 184         ws->zero_all_vram_allocs = debug_flags & RADV_DEBUG_ZERO_VRAM;
 185         ws->batchchain = !(perftest_flags & RADV_PERFTEST_NO_BATCHCHAIN);
 186         LIST_INITHEAD(&ws->global_bo_list);
 187         pthread_mutex_init(&ws->global_bo_list_lock, NULL);
 188         ws->base.query_info = radv_amdgpu_winsys_query_info;
 189         ws->base.query_value = radv_amdgpu_winsys_query_value;
 190         ws->base.read_registers = radv_amdgpu_winsys_read_registers;
 191         ws->base.get_chip_name = radv_amdgpu_winsys_get_chip_name;
 192         ws->base.destroy = radv_amdgpu_winsys_destroy;
 193         radv_amdgpu_bo_init_functions(ws);
 194         radv_amdgpu_cs_init_functions(ws);
 195         radv_amdgpu_surface_init_functions(ws);
 196
 197         return &ws->base;
 198
 199 winsys_fail:
 200         free(ws);
 201 fail:
 202         amdgpu_device_deinitialize(dev);
 203         return NULL;
 204 }