src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  * based on amdgpu winsys.
   5  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   6  * Copyright © 2015 Advanced Micro Devices, Inc.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27 #include "radv_amdgpu_winsys.h"
  28 #include "radv_amdgpu_winsys_public.h"
  29 #include "radv_amdgpu_surface.h"
  30 #include "radv_debug.h"
  31 #include "ac_surface.h"
  32 #include "xf86drm.h"
  33 #include <stdio.h>
  34 #include <stdlib.h>
  35 #include <string.h>
  36 #include <amdgpu_drm.h>
  37 #include <assert.h>
  38 #include "radv_amdgpu_cs.h"
  39 #include "radv_amdgpu_bo.h"
  40 #include "radv_amdgpu_surface.h"
  41
  42 static bool
  43 do_winsys_init(struct radv_amdgpu_winsys *ws, int fd)
  44 {
  45         if (!ac_query_gpu_info(fd, ws->dev, &ws->info, &ws->amdinfo))
  46                 return false;
  47
  48         /* LLVM 5.0 is required for GFX9. */
  49         if (ws->info.chip_class >= GFX9 && HAVE_LLVM < 0x0500) {
  50                 fprintf(stderr, "amdgpu: LLVM 5.0 is required, got LLVM %i.%i\n",
  51                         HAVE_LLVM >> 8, HAVE_LLVM & 255);
  52                 return false;
  53         }
  54
  55         ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo, &ws->info.max_alignment);
  56         if (!ws->addrlib) {
  57                 fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
  58                 return false;
  59         }
  60
  61         ws->info.num_sdma_rings = MIN2(ws->info.num_sdma_rings, MAX_RINGS_PER_TYPE);
  62         ws->info.num_compute_rings = MIN2(ws->info.num_compute_rings, MAX_RINGS_PER_TYPE);
  63
  64         ws->use_ib_bos = ws->info.chip_class >= CIK;
  65         return true;
  66 }
  67
  68 static void radv_amdgpu_winsys_query_info(struct radeon_winsys *rws,
  69                                      struct radeon_info *info)
  70 {
  71         *info = ((struct radv_amdgpu_winsys *)rws)->info;
  72 }
  73
  74 static uint64_t radv_amdgpu_winsys_query_value(struct radeon_winsys *rws,
  75                                                enum radeon_value_id value)
  76 {
  77         struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys *)rws;
  78         struct amdgpu_heap_info heap;
  79         uint64_t retval = 0;
  80
  81         switch (value) {
  82         case RADEON_TIMESTAMP:
  83                 amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
  84                 return retval;
  85         case RADEON_NUM_BYTES_MOVED:
  86                 amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED,
  87                                   8, &retval);
  88                 return retval;
  89         case RADEON_NUM_EVICTIONS:
  90                 amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_EVICTIONS,
  91                                   8, &retval);
  92                 return retval;
  93         case RADEON_NUM_VRAM_CPU_PAGE_FAULTS:
  94                 amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS,
  95                                   8, &retval);
  96                 return retval;
  97         case RADEON_VRAM_USAGE:
  98                 amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
  99                                        0, &heap);
 100                 return heap.heap_usage;
 101         case RADEON_VRAM_VIS_USAGE:
 102                 amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
 103                                        AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 104                                        &heap);
 105                 return heap.heap_usage;
 106         case RADEON_GTT_USAGE:
 107                 amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT,
 108                                        0, &heap);
 109                 return heap.heap_usage;
 110         case RADEON_GPU_TEMPERATURE:
 111                 amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GPU_TEMP,
 112                                          4, &retval);
 113                 return retval;
 114         case RADEON_CURRENT_SCLK:
 115                 amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_SCLK,
 116                                          4, &retval);
 117                 return retval;
 118         case RADEON_CURRENT_MCLK:
 119                 amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_MCLK,
 120                                          4, &retval);
 121                 return retval;
 122         default:
 123                 unreachable("invalid query value");
 124         }
 125
 126         return 0;
 127 }
 128
 129 static bool radv_amdgpu_winsys_read_registers(struct radeon_winsys *rws,
 130                                               unsigned reg_offset,
 131                                               unsigned num_registers, uint32_t *out)
 132 {
 133         struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys*)rws;
 134
 135         return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
 136                                         0xffffffff, 0, out) == 0;
 137 }
 138
 139 static const char *radv_amdgpu_winsys_get_chip_name(struct radeon_winsys *rws)
 140 {
 141         amdgpu_device_handle dev = ((struct radv_amdgpu_winsys *)rws)->dev;
 142
 143         return amdgpu_get_marketing_name(dev);
 144 }
 145
 146 static void radv_amdgpu_winsys_destroy(struct radeon_winsys *rws)
 147 {
 148         struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys*)rws;
 149
 150         AddrDestroy(ws->addrlib);
 151         amdgpu_device_deinitialize(ws->dev);
 152         FREE(rws);
 153 }
 154
 155 struct radeon_winsys *
 156 radv_amdgpu_winsys_create(int fd, uint64_t debug_flags, uint64_t perftest_flags)
 157 {
 158         uint32_t drm_major, drm_minor, r;
 159         amdgpu_device_handle dev;
 160         struct radv_amdgpu_winsys *ws;
 161
 162         r = amdgpu_device_initialize(fd, &drm_major, &drm_minor, &dev);
 163         if (r)
 164                 return NULL;
 165
 166         ws = calloc(1, sizeof(struct radv_amdgpu_winsys));
 167         if (!ws)
 168                 goto fail;
 169
 170         ws->dev = dev;
 171         ws->info.drm_major = drm_major;
 172         ws->info.drm_minor = drm_minor;
 173         if (!do_winsys_init(ws, fd))
 174                 goto winsys_fail;
 175
 176         ws->debug_all_bos = !!(debug_flags & RADV_DEBUG_ALL_BOS);
 177         if (debug_flags & RADV_DEBUG_NO_IBS)
 178                 ws->use_ib_bos = false;
 179
 180         ws->use_local_bos = perftest_flags & RADV_PERFTEST_LOCAL_BOS;
 181         ws->zero_all_vram_allocs = debug_flags & RADV_DEBUG_ZERO_VRAM;
 182         ws->batchchain = !(perftest_flags & RADV_PERFTEST_NO_BATCHCHAIN);
 183         LIST_INITHEAD(&ws->global_bo_list);
 184         pthread_mutex_init(&ws->global_bo_list_lock, NULL);
 185         ws->base.query_info = radv_amdgpu_winsys_query_info;
 186         ws->base.query_value = radv_amdgpu_winsys_query_value;
 187         ws->base.read_registers = radv_amdgpu_winsys_read_registers;
 188         ws->base.get_chip_name = radv_amdgpu_winsys_get_chip_name;
 189         ws->base.destroy = radv_amdgpu_winsys_destroy;
 190         radv_amdgpu_bo_init_functions(ws);
 191         radv_amdgpu_cs_init_functions(ws);
 192         radv_amdgpu_surface_init_functions(ws);
 193
 194         return &ws->base;
 195
 196 winsys_fail:
 197         free(ws);
 198 fail:
 199         amdgpu_device_deinitialize(dev);
 200         return NULL;
 201 }