src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  * based on amdgpu winsys.
   5  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   6  * Copyright © 2015 Advanced Micro Devices, Inc.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27 #include "radv_amdgpu_winsys.h"
  28 #include "radv_amdgpu_winsys_public.h"
  29 #include "radv_amdgpu_surface.h"
  30 #include "radv_debug.h"
  31 #include "ac_surface.h"
  32 #include "xf86drm.h"
  33 #include <stdio.h>
  34 #include <stdlib.h>
  35 #include <string.h>
  36 #include <amdgpu_drm.h>
  37 #include <assert.h>
  38 #include "radv_amdgpu_cs.h"
  39 #include "radv_amdgpu_bo.h"
  40 #include "radv_amdgpu_surface.h"
  41
  42 static bool
  43 do_winsys_init(struct radv_amdgpu_winsys *ws, int fd)
  44 {
  45         if (!ac_query_gpu_info(fd, ws->dev, &ws->info, &ws->amdinfo))
  46                 return false;
  47
  48         /* LLVM 9.0 is required for GFX10. */
  49         if (ws->info.chip_class == GFX10 && HAVE_LLVM < 0x0900) {
  50                 fprintf(stderr, "radv: Navi family support requires LLVM 9 or higher\n");
  51                 return false;
  52         }
  53
  54         if (ws->info.chip_class > GFX9)
  55                 return false;
  56
  57         /* temporary */
  58         ws->info.use_display_dcc_unaligned = false;
  59         ws->info.use_display_dcc_with_retile_blit = false;
  60
  61         ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo, &ws->info.max_alignment);
  62         if (!ws->addrlib) {
  63                 fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
  64                 return false;
  65         }
  66
  67         ws->info.num_sdma_rings = MIN2(ws->info.num_sdma_rings, MAX_RINGS_PER_TYPE);
  68         ws->info.num_compute_rings = MIN2(ws->info.num_compute_rings, MAX_RINGS_PER_TYPE);
  69
  70         ws->use_ib_bos = ws->info.chip_class >= GFX7;
  71         return true;
  72 }
  73
  74 static void radv_amdgpu_winsys_query_info(struct radeon_winsys *rws,
  75                                      struct radeon_info *info)
  76 {
  77         *info = ((struct radv_amdgpu_winsys *)rws)->info;
  78 }
  79
  80 static uint64_t radv_amdgpu_winsys_query_value(struct radeon_winsys *rws,
  81                                                enum radeon_value_id value)
  82 {
  83         struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys *)rws;
  84         struct amdgpu_heap_info heap;
  85         uint64_t retval = 0;
  86
  87         switch (value) {
  88         case RADEON_ALLOCATED_VRAM:
  89                 return ws->allocated_vram;
  90         case RADEON_ALLOCATED_VRAM_VIS:
  91                 return ws->allocated_vram_vis;
  92         case RADEON_ALLOCATED_GTT:
  93                 return ws->allocated_gtt;
  94         case RADEON_TIMESTAMP:
  95                 amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
  96                 return retval;
  97         case RADEON_NUM_BYTES_MOVED:
  98                 amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED,
  99                                   8, &retval);
 100                 return retval;
 101         case RADEON_NUM_EVICTIONS:
 102                 amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_EVICTIONS,
 103                                   8, &retval);
 104                 return retval;
 105         case RADEON_NUM_VRAM_CPU_PAGE_FAULTS:
 106                 amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS,
 107                                   8, &retval);
 108                 return retval;
 109         case RADEON_VRAM_USAGE:
 110                 amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
 111                                        0, &heap);
 112                 return heap.heap_usage;
 113         case RADEON_VRAM_VIS_USAGE:
 114                 amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
 115                                        AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 116                                        &heap);
 117                 return heap.heap_usage;
 118         case RADEON_GTT_USAGE:
 119                 amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT,
 120                                        0, &heap);
 121                 return heap.heap_usage;
 122         case RADEON_GPU_TEMPERATURE:
 123                 amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GPU_TEMP,
 124                                          4, &retval);
 125                 return retval;
 126         case RADEON_CURRENT_SCLK:
 127                 amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_SCLK,
 128                                          4, &retval);
 129                 return retval;
 130         case RADEON_CURRENT_MCLK:
 131                 amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_MCLK,
 132                                          4, &retval);
 133                 return retval;
 134         default:
 135                 unreachable("invalid query value");
 136         }
 137
 138         return 0;
 139 }
 140
 141 static bool radv_amdgpu_winsys_read_registers(struct radeon_winsys *rws,
 142                                               unsigned reg_offset,
 143                                               unsigned num_registers, uint32_t *out)
 144 {
 145         struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys*)rws;
 146
 147         return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
 148                                         0xffffffff, 0, out) == 0;
 149 }
 150
 151 static const char *radv_amdgpu_winsys_get_chip_name(struct radeon_winsys *rws)
 152 {
 153         amdgpu_device_handle dev = ((struct radv_amdgpu_winsys *)rws)->dev;
 154
 155         return amdgpu_get_marketing_name(dev);
 156 }
 157
 158 static void radv_amdgpu_winsys_destroy(struct radeon_winsys *rws)
 159 {
 160         struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys*)rws;
 161
 162         AddrDestroy(ws->addrlib);
 163         amdgpu_device_deinitialize(ws->dev);
 164         FREE(rws);
 165 }
 166
 167 struct radeon_winsys *
 168 radv_amdgpu_winsys_create(int fd, uint64_t debug_flags, uint64_t perftest_flags)
 169 {
 170         uint32_t drm_major, drm_minor, r;
 171         amdgpu_device_handle dev;
 172         struct radv_amdgpu_winsys *ws;
 173
 174         r = amdgpu_device_initialize(fd, &drm_major, &drm_minor, &dev);
 175         if (r)
 176                 return NULL;
 177
 178         ws = calloc(1, sizeof(struct radv_amdgpu_winsys));
 179         if (!ws)
 180                 goto fail;
 181
 182         ws->dev = dev;
 183         ws->info.drm_major = drm_major;
 184         ws->info.drm_minor = drm_minor;
 185         if (!do_winsys_init(ws, fd))
 186                 goto winsys_fail;
 187
 188         ws->debug_all_bos = !!(debug_flags & RADV_DEBUG_ALL_BOS);
 189         if (debug_flags & RADV_DEBUG_NO_IBS)
 190                 ws->use_ib_bos = false;
 191
 192         ws->use_local_bos = perftest_flags & RADV_PERFTEST_LOCAL_BOS;
 193         ws->zero_all_vram_allocs = debug_flags & RADV_DEBUG_ZERO_VRAM;
 194         ws->batchchain = !(perftest_flags & RADV_PERFTEST_NO_BATCHCHAIN);
 195         LIST_INITHEAD(&ws->global_bo_list);
 196         pthread_mutex_init(&ws->global_bo_list_lock, NULL);
 197         ws->base.query_info = radv_amdgpu_winsys_query_info;
 198         ws->base.query_value = radv_amdgpu_winsys_query_value;
 199         ws->base.read_registers = radv_amdgpu_winsys_read_registers;
 200         ws->base.get_chip_name = radv_amdgpu_winsys_get_chip_name;
 201         ws->base.destroy = radv_amdgpu_winsys_destroy;
 202         radv_amdgpu_bo_init_functions(ws);
 203         radv_amdgpu_cs_init_functions(ws);
 204         radv_amdgpu_surface_init_functions(ws);
 205
 206         return &ws->base;
 207
 208 winsys_fail:
 209         free(ws);
 210 fail:
 211         amdgpu_device_deinitialize(dev);
 212         return NULL;
 213 }