src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  * based on amdgpu winsys.
   5  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   6  * Copyright © 2015 Advanced Micro Devices, Inc.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27 #include "radv_amdgpu_winsys.h"
  28 #include "radv_amdgpu_winsys_public.h"
  29 #include "radv_amdgpu_surface.h"
  30 #include "radv_debug.h"
  31 #include "ac_surface.h"
  32 #include "xf86drm.h"
  33 #include <stdio.h>
  34 #include <stdlib.h>
  35 #include <string.h>
  36 #include <llvm/Config/llvm-config.h>
  37 #include <amdgpu_drm.h>
  38 #include <assert.h>
  39 #include "radv_amdgpu_cs.h"
  40 #include "radv_amdgpu_bo.h"
  41 #include "radv_amdgpu_surface.h"
  42
  43 static bool
  44 do_winsys_init(struct radv_amdgpu_winsys *ws, int fd)
  45 {
  46         if (!ac_query_gpu_info(fd, ws->dev, &ws->info, &ws->amdinfo))
  47                 return false;
  48
  49         /* LLVM 9.0 is required for GFX10. */
  50         if (ws->info.chip_class == GFX10 && LLVM_VERSION_MAJOR < 9) {
  51                 fprintf(stderr, "radv: Navi family support requires LLVM 9 or higher\n");
  52                 return false;
  53         }
  54
  55         /* temporary */
  56         ws->info.use_display_dcc_unaligned = false;
  57         ws->info.use_display_dcc_with_retile_blit = false;
  58
  59         ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo, &ws->info.max_alignment);
  60         if (!ws->addrlib) {
  61                 fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
  62                 return false;
  63         }
  64
  65         ws->info.num_sdma_rings = MIN2(ws->info.num_sdma_rings, MAX_RINGS_PER_TYPE);
  66         ws->info.num_compute_rings = MIN2(ws->info.num_compute_rings, MAX_RINGS_PER_TYPE);
  67
  68         ws->use_ib_bos = ws->info.chip_class >= GFX7;
  69         return true;
  70 }
  71
  72 static void radv_amdgpu_winsys_query_info(struct radeon_winsys *rws,
  73                                      struct radeon_info *info)
  74 {
  75         *info = ((struct radv_amdgpu_winsys *)rws)->info;
  76 }
  77
  78 static uint64_t radv_amdgpu_winsys_query_value(struct radeon_winsys *rws,
  79                                                enum radeon_value_id value)
  80 {
  81         struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys *)rws;
  82         struct amdgpu_heap_info heap;
  83         uint64_t retval = 0;
  84
  85         switch (value) {
  86         case RADEON_ALLOCATED_VRAM:
  87                 return ws->allocated_vram;
  88         case RADEON_ALLOCATED_VRAM_VIS:
  89                 return ws->allocated_vram_vis;
  90         case RADEON_ALLOCATED_GTT:
  91                 return ws->allocated_gtt;
  92         case RADEON_TIMESTAMP:
  93                 amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
  94                 return retval;
  95         case RADEON_NUM_BYTES_MOVED:
  96                 amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED,
  97                                   8, &retval);
  98                 return retval;
  99         case RADEON_NUM_EVICTIONS:
 100                 amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_EVICTIONS,
 101                                   8, &retval);
 102                 return retval;
 103         case RADEON_NUM_VRAM_CPU_PAGE_FAULTS:
 104                 amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS,
 105                                   8, &retval);
 106                 return retval;
 107         case RADEON_VRAM_USAGE:
 108                 amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
 109                                        0, &heap);
 110                 return heap.heap_usage;
 111         case RADEON_VRAM_VIS_USAGE:
 112                 amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
 113                                        AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 114                                        &heap);
 115                 return heap.heap_usage;
 116         case RADEON_GTT_USAGE:
 117                 amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT,
 118                                        0, &heap);
 119                 return heap.heap_usage;
 120         case RADEON_GPU_TEMPERATURE:
 121                 amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GPU_TEMP,
 122                                          4, &retval);
 123                 return retval;
 124         case RADEON_CURRENT_SCLK:
 125                 amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_SCLK,
 126                                          4, &retval);
 127                 return retval;
 128         case RADEON_CURRENT_MCLK:
 129                 amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_MCLK,
 130                                          4, &retval);
 131                 return retval;
 132         default:
 133                 unreachable("invalid query value");
 134         }
 135
 136         return 0;
 137 }
 138
 139 static bool radv_amdgpu_winsys_read_registers(struct radeon_winsys *rws,
 140                                               unsigned reg_offset,
 141                                               unsigned num_registers, uint32_t *out)
 142 {
 143         struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys*)rws;
 144
 145         return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
 146                                         0xffffffff, 0, out) == 0;
 147 }
 148
 149 static const char *radv_amdgpu_winsys_get_chip_name(struct radeon_winsys *rws)
 150 {
 151         amdgpu_device_handle dev = ((struct radv_amdgpu_winsys *)rws)->dev;
 152
 153         return amdgpu_get_marketing_name(dev);
 154 }
 155
 156 static void radv_amdgpu_winsys_destroy(struct radeon_winsys *rws)
 157 {
 158         struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys*)rws;
 159
 160         AddrDestroy(ws->addrlib);
 161         amdgpu_device_deinitialize(ws->dev);
 162         FREE(rws);
 163 }
 164
 165 struct radeon_winsys *
 166 radv_amdgpu_winsys_create(int fd, uint64_t debug_flags, uint64_t perftest_flags)
 167 {
 168         uint32_t drm_major, drm_minor, r;
 169         amdgpu_device_handle dev;
 170         struct radv_amdgpu_winsys *ws;
 171
 172         r = amdgpu_device_initialize(fd, &drm_major, &drm_minor, &dev);
 173         if (r)
 174                 return NULL;
 175
 176         ws = calloc(1, sizeof(struct radv_amdgpu_winsys));
 177         if (!ws)
 178                 goto fail;
 179
 180         ws->dev = dev;
 181         ws->info.drm_major = drm_major;
 182         ws->info.drm_minor = drm_minor;
 183         if (!do_winsys_init(ws, fd))
 184                 goto winsys_fail;
 185
 186         ws->debug_all_bos = !!(debug_flags & RADV_DEBUG_ALL_BOS);
 187         if (debug_flags & RADV_DEBUG_NO_IBS)
 188                 ws->use_ib_bos = false;
 189
 190         ws->use_local_bos = perftest_flags & RADV_PERFTEST_LOCAL_BOS;
 191         ws->zero_all_vram_allocs = debug_flags & RADV_DEBUG_ZERO_VRAM;
 192         ws->batchchain = !(perftest_flags & RADV_PERFTEST_NO_BATCHCHAIN);
 193         LIST_INITHEAD(&ws->global_bo_list);
 194         pthread_mutex_init(&ws->global_bo_list_lock, NULL);
 195         ws->base.query_info = radv_amdgpu_winsys_query_info;
 196         ws->base.query_value = radv_amdgpu_winsys_query_value;
 197         ws->base.read_registers = radv_amdgpu_winsys_read_registers;
 198         ws->base.get_chip_name = radv_amdgpu_winsys_get_chip_name;
 199         ws->base.destroy = radv_amdgpu_winsys_destroy;
 200         radv_amdgpu_bo_init_functions(ws);
 201         radv_amdgpu_cs_init_functions(ws);
 202         radv_amdgpu_surface_init_functions(ws);
 203
 204         return &ws->base;
 205
 206 winsys_fail:
 207         free(ws);
 208 fail:
 209         amdgpu_device_deinitialize(dev);
 210         return NULL;
 211 }