3 # Copyright (c) 2016 ARM Limited
6 # The license below extends only to copyright in the software and shall
7 # not be construed as granting a license to any other intellectual
8 # property including but not limited to intellectual property relating
9 # to a hardware implementation of the functionality of the software
10 # licensed hereunder. You may use the software subject to the license
11 # terms below provided that you ensure that this notice is replicated
12 # unmodified and in its entirety in all distributions of the software,
13 # modified or unmodified, in source code or in binary form.
15 # Copyright (c) 2006 The Regents of The University of Michigan
16 # All rights reserved.
18 # Redistribution and use in source and binary forms, with or without
19 # modification, are permitted provided that the following conditions are
20 # met: redistributions of source code must retain the above copyright
21 # notice, this list of conditions and the following disclaimer;
22 # redistributions in binary form must reproduce the above copyright
23 # notice, this list of conditions and the following disclaimer in the
24 # documentation and/or other materials provided with the distribution;
25 # neither the name of the copyright holders nor the names of its
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27 # this software without specific prior written permission.
29 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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35 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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39 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 # Authors: Steve Reinhardt
47 from gem5_scons import Transform
51 #################################################################
53 # ISA "switch header" generation.
55 # Auto-generate arch headers that include the right ISA-specific
56 # header based on the setting of THE_ISA preprocessor variable.
58 #################################################################
80 env.subst('${TARGET_ISA}'))
89 env.subst('${TARGET_GPU_ISA}'))
91 #################################################################
93 # Include architecture-specific files.
95 #################################################################
98 # Build a SCons scanner for ISA files
103 scanner = SCons.Scanner.Classic("ISAScan",
106 r'^\s*##include\s+"([\w/.-]*)"')
108 env.Append(SCANNERS=scanner)
110 # Tell scons that when it sees a cc.inc file, it should scan it for includes.
111 SCons.Tool.SourceFileScanner.add_scanner('.cc.inc', SCons.Tool.CScanner)
114 # Now create a Builder object that uses isa_parser.py to generate C++
115 # output from the ISA description (*.isa) files.
118 parser_py = File('isa_parser.py')
119 micro_asm_py = File('micro_asm.py')
121 # import ply here because SCons screws with sys.path when performing actions.
124 def run_parser(target, source, env):
125 # Add the current directory to the system path so we can import files.
126 sys.path[0:0] = [ parser_py.dir.abspath ]
129 parser = isa_parser.ISAParser(target[0].dir.abspath)
130 parser.parse_isa_desc(source[0].abspath)
132 desc_action = MakeAction(run_parser, Transform("ISA DESC", 1))
134 IsaDescBuilder = Builder(action=desc_action)
137 # ISAs should use this function to set up an IsaDescBuilder and not try to
138 # set one up manually.
139 def ISADesc(desc, decoder_splits=1, exec_splits=1):
140 '''Set up a builder for an ISA description.
142 The decoder_splits and exec_splits parameters let us determine what
143 files the isa parser is actually going to generate. This needs to match
144 what files are actually generated, and there's no specific check for that
147 If the parser itself is responsible for generating a list of its products
148 and their dependencies, then using that output to set up the right
149 dependencies. This is what we used to do. The problem is that scons
150 fundamentally doesn't support using a build product to affect its graph
151 of possible products, dependencies, builders, etc. There are a couple ways
152 to work around that limitation.
154 One option is to compute dependencies while the build phase of scons is
155 running. That method can be quite complicated and cumbersome, because we
156 have to make sure our modifications are made before scons tries to
157 consume them. There's also no guarantee that this mechanism will work since
158 it subverts scons expectations and changes things behind its back. This
159 was implemented previously and constrained the builds parallelism
162 Another option would be to recursively call scons to have it update the
163 list of products/dependencies during the setup phase of this invocation of
164 scons. The problem with that is that it would be very difficult to make
165 the sub-invocation of scons observe the options passed to the primary one
166 in all possible cases, or to even determine conclusively what the name of
167 the scons executable is in the first place.
169 Possible future changes to the isa parser might make it easier to
170 determine what files it would generate, perhaps because there was a more
171 direct correspondence between input files and output files. Or, if the
172 parser could run quickly and determine what its output files would be
173 without having do actually generate those files, then it could be run
174 unconditionally without slowing down all builds or touching the output
177 generated_dir = File(desc).dir.up().Dir('generated')
179 return generated_dir.File(name)
183 gen.append(gen_file(name))
185 # Tell scons about the various files the ISA parser will generate.
186 add_gen('decoder-g.cc.inc')
187 add_gen('decoder-ns.cc.inc')
188 add_gen('decode-method.cc.inc')
190 add_gen('decoder.hh')
191 add_gen('decoder-g.hh.inc')
192 add_gen('decoder-ns.hh.inc')
194 add_gen('exec-g.cc.inc')
195 add_gen('exec-ns.cc.inc')
197 add_gen('max_inst_regs.hh')
200 # These generated files are also top level sources.
201 def source_gen(name):
203 Source(gen_file(name))
205 source_gen('decoder.cc')
207 if decoder_splits == 1:
208 source_gen('inst-constrs.cc')
210 for i in range(1, decoder_splits + 1):
211 source_gen('inst-constrs-%d.cc' % i)
214 source_gen('generic_cpu_exec.cc')
216 for i in range(1, exec_splits + 1):
217 source_gen('generic_cpu_exec_%d.cc' % i)
219 # Actually create the builder.
220 sources = [desc, parser_py, micro_asm_py]
221 IsaDescBuilder(target=gen, source=sources, env=env)
227 DebugFlag('FloatRegs')
230 DebugFlag('MiscRegs')
231 CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'CCRegs', 'MiscRegs' ])