src/arch/SConscript

   1 # -*- mode:python -*-
   2
   3 # Copyright (c) 2006 The Regents of The University of Michigan
   4 # All rights reserved.
   5 #
   6 # Redistribution and use in source and binary forms, with or without
   7 # modification, are permitted provided that the following conditions are
   8 # met: redistributions of source code must retain the above copyright
   9 # notice, this list of conditions and the following disclaimer;
  10 # redistributions in binary form must reproduce the above copyright
  11 # notice, this list of conditions and the following disclaimer in the
  12 # documentation and/or other materials provided with the distribution;
  13 # neither the name of the copyright holders nor the names of its
  14 # contributors may be used to endorse or promote products derived from
  15 # this software without specific prior written permission.
  16 #
  17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28 #
  29 # Authors: Steve Reinhardt
  30
  31 import sys
  32
  33 Import('*')
  34
  35 #################################################################
  36 #
  37 # ISA "switch header" generation.
  38 #
  39 # Auto-generate arch headers that include the right ISA-specific
  40 # header based on the setting of THE_ISA preprocessor variable.
  41 #
  42 #################################################################
  43
  44 # List of headers to generate
  45 isa_switch_hdrs = Split('''
  46         arguments.hh
  47         faults.hh
  48         interrupts.hh
  49         isa.hh
  50         isa_traits.hh
  51         kernel_stats.hh
  52         locked_mem.hh
  53         microcode_rom.hh
  54         mmaped_ipr.hh
  55         mt.hh
  56         process.hh
  57         predecoder.hh
  58         registers.hh
  59         remote_gdb.hh
  60         stacktrace.hh
  61         tlb.hh
  62         types.hh
  63         utility.hh
  64         vtophys.hh
  65         ''')
  66
  67 # Set up this directory to support switching headers
  68 make_switching_dir('arch', isa_switch_hdrs, env)
  69
  70 #################################################################
  71 #
  72 # Include architecture-specific files.
  73 #
  74 #################################################################
  75
  76 #
  77 # Build a SCons scanner for ISA files
  78 #
  79 import SCons.Scanner
  80
  81 isa_scanner = SCons.Scanner.Classic("ISAScan",
  82                                     [".isa", ".ISA"],
  83                                     "SRCDIR",
  84                                     r'^\s*##include\s+"([\w/.-]*)"')
  85
  86 env.Append(SCANNERS = isa_scanner)
  87
  88 #
  89 # Now create a Builder object that uses isa_parser.py to generate C++
  90 # output from the ISA description (*.isa) files.
  91 #
  92
  93 # Convert to File node to fix path
  94 isa_parser = File('isa_parser.py')
  95 cpu_models_file = File('../cpu/cpu_models.py')
  96
  97 # This sucks in the defintions of the CpuModel objects.
  98 execfile(cpu_models_file.srcnode().abspath)
  99
 100 # Several files are generated from the ISA description.
 101 # We always get the basic decoder and header file.
 102 isa_desc_gen_files = [ 'decoder.cc', 'decoder.hh', 'max_inst_regs.hh' ]
 103 # We also get an execute file for each selected CPU model.
 104 isa_desc_gen_files += [CpuModel.dict[cpu].filename
 105                        for cpu in env['CPU_MODELS']]
 106
 107 # Also include the CheckerCPU as one of the models if it is being
 108 # enabled via command line.
 109 if env['USE_CHECKER']:
 110     isa_desc_gen_files += [CpuModel.dict['CheckerCPU'].filename]
 111
 112 # The emitter patches up the sources & targets to include the
 113 # autogenerated files as targets and isa parser itself as a source.
 114 def isa_desc_emitter(target, source, env):
 115     return (isa_desc_gen_files, [isa_parser, cpu_models_file] + source)
 116
 117 # Pieces are in place, so create the builder.
 118 python = sys.executable  # use same Python binary used to run scons
 119
 120 # Also include the CheckerCPU as one of the models if it is being
 121 # enabled via command line.
 122 if env['USE_CHECKER']:
 123     isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS CheckerCPU',
 124                                emitter = isa_desc_emitter)
 125 else:
 126     isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS',
 127                                emitter = isa_desc_emitter)
 128
 129 env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
 130
 131 TraceFlag('IntRegs')
 132 TraceFlag('FloatRegs')
 133 TraceFlag('MiscRegs')
 134 CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ])