arch-power: Add doubleword modulo instructions
[gem5.git] / src / arch / SConscript
1 # -*- mode:python -*-
2
3 # Copyright (c) 2016-2017 ARM Limited
4 # All rights reserved.
5 #
6 # The license below extends only to copyright in the software and shall
7 # not be construed as granting a license to any other intellectual
8 # property including but not limited to intellectual property relating
9 # to a hardware implementation of the functionality of the software
10 # licensed hereunder. You may use the software subject to the license
11 # terms below provided that you ensure that this notice is replicated
12 # unmodified and in its entirety in all distributions of the software,
13 # modified or unmodified, in source code or in binary form.
14 #
15 # Copyright (c) 2006 The Regents of The University of Michigan
16 # All rights reserved.
17 #
18 # Redistribution and use in source and binary forms, with or without
19 # modification, are permitted provided that the following conditions are
20 # met: redistributions of source code must retain the above copyright
21 # notice, this list of conditions and the following disclaimer;
22 # redistributions in binary form must reproduce the above copyright
23 # notice, this list of conditions and the following disclaimer in the
24 # documentation and/or other materials provided with the distribution;
25 # neither the name of the copyright holders nor the names of its
26 # contributors may be used to endorse or promote products derived from
27 # this software without specific prior written permission.
28 #
29 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40
41 import sys
42 import os
43 import re
44
45 from gem5_scons import Transform
46
47 Import('*')
48
49 #################################################################
50 #
51 # ISA "switch header" generation.
52 #
53 # Auto-generate arch headers that include the right ISA-specific
54 # header based on the setting of THE_ISA preprocessor variable.
55 #
56 #################################################################
57
58 env.SwitchingHeaders(
59 Split('''
60 decoder.hh
61 isa.hh
62 isa_traits.hh
63 locked_mem.hh
64 registers.hh
65 remote_gdb.hh
66 types.hh
67 utility.hh
68 '''),
69 env.subst('${TARGET_ISA}'))
70
71 if env['BUILD_GPU']:
72 env.SwitchingHeaders(
73 Split('''
74 gpu_decoder.hh
75 gpu_isa.hh
76 gpu_types.hh
77 '''),
78 env.subst('${TARGET_GPU_ISA}'))
79
80 #################################################################
81 #
82 # Include architecture-specific files.
83 #
84 #################################################################
85
86 #
87 # Build a SCons scanner for ISA files
88 #
89 import SCons.Scanner
90 import SCons.Tool
91
92 scanner = SCons.Scanner.Classic("ISAScan",
93 [".isa", ".ISA"],
94 "SRCDIR",
95 r'^\s*##include\s+"([\w/.-]*)"')
96
97 env.Append(SCANNERS=scanner)
98
99 # Tell scons that when it sees a cc.inc file, it should scan it for includes.
100 SCons.Tool.SourceFileScanner.add_scanner('.cc.inc', SCons.Tool.CScanner)
101
102 #
103 # Now create a Builder object that uses isa_parser.py to generate C++
104 # output from the ISA description (*.isa) files.
105 #
106
107 parser_files = Glob('isa_parser/*.py')
108 micro_asm_py = File('micro_asm.py')
109
110 # import ply here because SCons screws with sys.path when performing actions.
111 import ply
112
113 arch_dir = Dir('.')
114
115 def run_parser(target, source, env):
116 # Add the current directory to the system path so we can import files.
117 sys.path[0:0] = [ arch_dir.abspath ]
118 import isa_parser
119
120 parser = isa_parser.ISAParser(target[0].dir.abspath)
121 parser.parse_isa_desc(source[0].abspath)
122
123 desc_action = MakeAction(run_parser, Transform("ISA DESC", 1))
124
125 IsaDescBuilder = Builder(action=desc_action)
126
127
128 # ISAs should use this function to set up an IsaDescBuilder and not try to
129 # set one up manually.
130 def ISADesc(desc, decoder_splits=1, exec_splits=1):
131 '''Set up a builder for an ISA description.
132
133 The decoder_splits and exec_splits parameters let us determine what
134 files the isa parser is actually going to generate. This needs to match
135 what files are actually generated, and there's no specific check for that
136 right now.
137
138 If the parser itself is responsible for generating a list of its products
139 and their dependencies, then using that output to set up the right
140 dependencies. This is what we used to do. The problem is that scons
141 fundamentally doesn't support using a build product to affect its graph
142 of possible products, dependencies, builders, etc. There are a couple ways
143 to work around that limitation.
144
145 One option is to compute dependencies while the build phase of scons is
146 running. That method can be quite complicated and cumbersome, because we
147 have to make sure our modifications are made before scons tries to
148 consume them. There's also no guarantee that this mechanism will work since
149 it subverts scons expectations and changes things behind its back. This
150 was implemented previously and constrained the builds parallelism
151 significantly.
152
153 Another option would be to recursively call scons to have it update the
154 list of products/dependencies during the setup phase of this invocation of
155 scons. The problem with that is that it would be very difficult to make
156 the sub-invocation of scons observe the options passed to the primary one
157 in all possible cases, or to even determine conclusively what the name of
158 the scons executable is in the first place.
159
160 Possible future changes to the isa parser might make it easier to
161 determine what files it would generate, perhaps because there was a more
162 direct correspondence between input files and output files. Or, if the
163 parser could run quickly and determine what its output files would be
164 without having do actually generate those files, then it could be run
165 unconditionally without slowing down all builds or touching the output
166 files unnecessarily.
167 '''
168 generated_dir = File(desc).dir.up().Dir('generated')
169 def gen_file(name):
170 return generated_dir.File(name)
171
172 gen = []
173 def add_gen(name):
174 gen.append(gen_file(name))
175
176 # Tell scons about the various files the ISA parser will generate.
177 add_gen('decoder-g.cc.inc')
178 add_gen('decoder-ns.cc.inc')
179 add_gen('decode-method.cc.inc')
180
181 add_gen('decoder.hh')
182 add_gen('decoder-g.hh.inc')
183 add_gen('decoder-ns.hh.inc')
184
185 add_gen('exec-g.cc.inc')
186 add_gen('exec-ns.cc.inc')
187
188 add_gen('max_inst_regs.hh')
189
190
191 # These generated files are also top level sources.
192 def source_gen(name):
193 add_gen(name)
194 Source(gen_file(name))
195
196 source_gen('decoder.cc')
197
198 if decoder_splits == 1:
199 source_gen('inst-constrs.cc')
200 else:
201 for i in range(1, decoder_splits + 1):
202 source_gen('inst-constrs-%d.cc' % i)
203
204 if exec_splits == 1:
205 source_gen('generic_cpu_exec.cc')
206 else:
207 for i in range(1, exec_splits + 1):
208 source_gen('generic_cpu_exec_%d.cc' % i)
209
210 # Actually create the builder.
211 sources = [desc, micro_asm_py] + parser_files
212 IsaDescBuilder(target=gen, source=sources, env=env)
213 return gen
214
215 Export('ISADesc')
216
217 DebugFlag('IntRegs')
218 DebugFlag('FloatRegs')
219 DebugFlag('VecRegs')
220 DebugFlag('VecPredRegs')
221 DebugFlag('CCRegs')
222 DebugFlag('MiscRegs')
223 CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'VecRegs', 'VecPredRegs',
224 'CCRegs', 'MiscRegs' ])