2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
32 #include "arch/alpha/faults.hh"
33 #include "arch/alpha/isa_traits.hh"
34 #include "arch/alpha/kernel_stats.hh"
35 #include "arch/alpha/osfpal.hh"
36 #include "arch/alpha/tlb.hh"
37 #include "base/cp_annotate.hh"
38 #include "base/debug.hh"
39 #include "config/full_system.hh"
40 #include "cpu/base.hh"
41 #include "cpu/simple_thread.hh"
42 #include "cpu/thread_context.hh"
43 #include "sim/sim_exit.hh"
49 ////////////////////////////////////////////////////////////////////////
51 // Machine dependent functions
54 initCPU(ThreadContext
*tc
, int cpuId
)
58 tc
->setIntReg(16, cpuId
);
59 tc
->setIntReg(0, cpuId
);
61 AlphaFault
*reset
= new ResetFault
;
63 tc
->setPC(tc
->readMiscRegNoEffect(IPR_PAL_BASE
) + reset
->vect());
64 tc
->setNextPC(tc
->readPC() + sizeof(MachInst
));
71 zeroRegisters(CPU
*cpu
)
73 // Insure ISA semantics
74 // (no longer very clean due to the change in setIntReg() in the
75 // cpu model. Consider changing later.)
76 cpu
->thread
->setIntReg(ZeroReg
, 0);
77 cpu
->thread
->setFloatReg(ZeroReg
, 0.0);
82 ////////////////////////////////////////////////////////////////////////
87 initIPRs(ThreadContext
*tc
, int cpuId
)
89 for (int i
= 0; i
< NumInternalProcRegs
; ++i
) {
90 tc
->setMiscRegNoEffect(i
, 0);
93 tc
->setMiscRegNoEffect(IPR_PAL_BASE
, PalBase
);
94 tc
->setMiscRegNoEffect(IPR_MCSR
, 0x6);
95 tc
->setMiscRegNoEffect(IPR_PALtemp16
, cpuId
);
99 ISA::readIpr(int idx
, ThreadContext
*tc
)
101 uint64_t retval
= 0; // return value, default 0
135 case IPR_IC_PERR_STAT
:
136 case IPR_DC_PERR_STAT
:
152 retval
|= ipr
[idx
] & ULL(0xffffffff00000000);
153 retval
|= tc
->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff);
162 case IPR_IFAULT_VA_FORM
:
171 = tc
->getDTBPtr()->index(!tc
->misspeculating());
173 retval
|= ((uint64_t)entry
.ppn
& ULL(0x7ffffff)) << 32;
174 retval
|= ((uint64_t)entry
.xre
& ULL(0xf)) << 8;
175 retval
|= ((uint64_t)entry
.xwe
& ULL(0xf)) << 12;
176 retval
|= ((uint64_t)entry
.fonr
& ULL(0x1)) << 1;
177 retval
|= ((uint64_t)entry
.fonw
& ULL(0x1))<< 2;
178 retval
|= ((uint64_t)entry
.asma
& ULL(0x1)) << 4;
179 retval
|= ((uint64_t)entry
.asn
& ULL(0x7f)) << 57;
183 // write only registers
193 panic("Tried to read write only register %d\n", idx
);
198 panic("Tried to read from invalid ipr %d\n", idx
);
206 // Cause the simulator to break when changing to the following IPL
211 ISA::setIpr(int idx
, uint64_t val
, ThreadContext
*tc
)
215 if (tc
->misspeculating())
243 case IPR_IC_PERR_STAT
:
244 case IPR_DC_PERR_STAT
:
246 // write entire quad w/ no side-effect
251 // This IPR resets the cycle counter. We assume this only
252 // happens once... let's verify that.
253 assert(ipr
[idx
] == 0);
258 // This IPR only writes the upper 64 bits. It's ok to write
259 // all 64 here since we mask out the lower 32 in rpcc (see
265 // write entire quad w/ no side-effect
269 if (tc
->getKernelStats())
270 tc
->getKernelStats()->context(old
, val
, tc
);
275 // write entire quad w/ no side-effect, tag is forthcoming
280 // second least significant bit in PC is always zero
286 // only write least significant four bits - privilege mask
287 ipr
[idx
] = val
& 0xf;
292 if (break_ipl
!= -1 && break_ipl
== (int)(val
& 0x1f))
296 // only write least significant five bits - interrupt level
297 ipr
[idx
] = val
& 0x1f;
299 if (tc
->getKernelStats())
300 tc
->getKernelStats()->swpipl(ipr
[idx
]);
307 if (tc
->getKernelStats())
308 tc
->getKernelStats()->mode(Kernel::user
, tc
);
310 if (tc
->getKernelStats())
311 tc
->getKernelStats()->mode(Kernel::kernel
, tc
);
316 // only write two mode bits - processor mode
317 ipr
[idx
] = val
& 0x18;
321 // only write two mode bits - processor mode
322 ipr
[idx
] = val
& 0x18;
326 // more here after optimization...
331 // only write software interrupt mask
332 ipr
[idx
] = val
& 0x7fff0;
336 ipr
[idx
] = val
& ULL(0xffffff0300);
341 ipr
[idx
] = val
& ULL(0xffffffffc0000000);
344 case IPR_DC_TEST_CTL
:
345 ipr
[idx
] = val
& 0x1ffb;
350 ipr
[idx
] = val
& 0x3f;
354 ipr
[idx
] = val
& 0x7f0;
358 ipr
[idx
] = val
& ULL(0xfe00000000000000);
363 // any write to this register clears it
370 case IPR_ITB_PTE_TEMP
:
371 case IPR_DTB_PTE_TEMP
:
372 // read-only registers
373 panic("Tried to write read only ipr %d\n", idx
);
379 // the following are write only
384 // really a control write
387 tc
->getDTBPtr()->flushAll();
391 // really a control write
394 tc
->getDTBPtr()->flushProcesses();
398 // really a control write
401 tc
->getDTBPtr()->flushAddr(val
, DTB_ASN_ASN(ipr
[IPR_DTB_ASN
]));
405 struct TlbEntry entry
;
407 // FIXME: granularity hints NYI...
408 if (DTB_PTE_GH(ipr
[IPR_DTB_PTE
]) != 0)
409 panic("PTE GH field != 0");
414 // construct PTE for new entry
415 entry
.ppn
= DTB_PTE_PPN(ipr
[IPR_DTB_PTE
]);
416 entry
.xre
= DTB_PTE_XRE(ipr
[IPR_DTB_PTE
]);
417 entry
.xwe
= DTB_PTE_XWE(ipr
[IPR_DTB_PTE
]);
418 entry
.fonr
= DTB_PTE_FONR(ipr
[IPR_DTB_PTE
]);
419 entry
.fonw
= DTB_PTE_FONW(ipr
[IPR_DTB_PTE
]);
420 entry
.asma
= DTB_PTE_ASMA(ipr
[IPR_DTB_PTE
]);
421 entry
.asn
= DTB_ASN_ASN(ipr
[IPR_DTB_ASN
]);
423 // insert new TAG/PTE value into data TLB
424 tc
->getDTBPtr()->insert(val
, entry
);
429 struct TlbEntry entry
;
431 // FIXME: granularity hints NYI...
432 if (ITB_PTE_GH(val
) != 0)
433 panic("PTE GH field != 0");
438 // construct PTE for new entry
439 entry
.ppn
= ITB_PTE_PPN(val
);
440 entry
.xre
= ITB_PTE_XRE(val
);
442 entry
.fonr
= ITB_PTE_FONR(val
);
443 entry
.fonw
= ITB_PTE_FONW(val
);
444 entry
.asma
= ITB_PTE_ASMA(val
);
445 entry
.asn
= ITB_ASN_ASN(ipr
[IPR_ITB_ASN
]);
447 // insert new TAG/PTE value into data TLB
448 tc
->getITBPtr()->insert(ipr
[IPR_ITB_TAG
], entry
);
453 // really a control write
456 tc
->getITBPtr()->flushAll();
460 // really a control write
463 tc
->getITBPtr()->flushProcesses();
467 // really a control write
470 tc
->getITBPtr()->flushAddr(val
, ITB_ASN_ASN(ipr
[IPR_ITB_ASN
]));
475 panic("Tried to write to invalid ipr %d\n", idx
);
482 copyIprs(ThreadContext
*src
, ThreadContext
*dest
)
484 for (int i
= 0; i
< NumInternalProcRegs
; ++i
)
485 dest
->setMiscRegNoEffect(i
, src
->readMiscRegNoEffect(i
));
488 } // namespace AlphaISA
492 using namespace AlphaISA
;
495 SimpleThread::hwrei()
497 if (!(readPC() & 0x3))
498 return new UnimplementedOpcodeFault
;
500 setNextPC(readMiscRegNoEffect(IPR_EXC_ADDR
));
502 CPA::cpa()->swAutoBegin(tc
, readNextPC());
504 if (!misspeculating()) {
506 kernelStats
->hwrei();
509 // FIXME: XXX check for interrupts? XXX
514 * Check for special simulator handling of specific PAL calls.
515 * If return value is false, actual PAL call will be suppressed.
518 SimpleThread::simPalCheck(int palFunc
)
521 kernelStats
->callpal(palFunc
, tc
);
526 if (--System::numSystemsRunning
== 0)
527 exitSimLoop("all cpus halted");
532 if (system
->breakpoint())
540 #endif // FULL_SYSTEM