src/arch/alpha/ev5.cc

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Nathan Binkert
  30  */
  31
  32 #include "arch/alpha/faults.hh"
  33 #include "arch/alpha/isa_traits.hh"
  34 #include "arch/alpha/kernel_stats.hh"
  35 #include "arch/alpha/osfpal.hh"
  36 #include "arch/alpha/tlb.hh"
  37 #include "base/cp_annotate.hh"
  38 #include "base/debug.hh"
  39 #include "cpu/base.hh"
  40 #include "cpu/simple_thread.hh"
  41 #include "cpu/thread_context.hh"
  42 #include "sim/sim_exit.hh"
  43
  44 namespace AlphaISA {
  45
  46 template<typename T>
  47 TLB *
  48 getITBPtr(T *tc)
  49 {
  50     auto tlb = dynamic_cast<TLB *>(tc->getITBPtr());
  51     assert(tlb);
  52     return tlb;
  53 }
  54
  55 template<typename T>
  56 TLB *
  57 getDTBPtr(T *tc)
  58 {
  59     auto tlb = dynamic_cast<TLB *>(tc->getDTBPtr());
  60     assert(tlb);
  61     return tlb;
  62 }
  63
  64 ////////////////////////////////////////////////////////////////////////
  65 //
  66 //
  67 //
  68 void
  69 initIPRs(ThreadContext *tc, int cpuId)
  70 {
  71     for (int i = 0; i < NumInternalProcRegs; ++i) {
  72         tc->setMiscRegNoEffect(i, 0);
  73     }
  74
  75     tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase);
  76     tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
  77     tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
  78 }
  79
  80 RegVal
  81 ISA::readIpr(int idx, ThreadContext *tc)
  82 {
  83     uint64_t retval = 0;        // return value, default 0
  84
  85     switch (idx) {
  86       case IPR_PALtemp0:
  87       case IPR_PALtemp1:
  88       case IPR_PALtemp2:
  89       case IPR_PALtemp3:
  90       case IPR_PALtemp4:
  91       case IPR_PALtemp5:
  92       case IPR_PALtemp6:
  93       case IPR_PALtemp7:
  94       case IPR_PALtemp8:
  95       case IPR_PALtemp9:
  96       case IPR_PALtemp10:
  97       case IPR_PALtemp11:
  98       case IPR_PALtemp12:
  99       case IPR_PALtemp13:
 100       case IPR_PALtemp14:
 101       case IPR_PALtemp15:
 102       case IPR_PALtemp16:
 103       case IPR_PALtemp17:
 104       case IPR_PALtemp18:
 105       case IPR_PALtemp19:
 106       case IPR_PALtemp20:
 107       case IPR_PALtemp21:
 108       case IPR_PALtemp22:
 109       case IPR_PALtemp23:
 110       case IPR_PAL_BASE:
 111
 112       case IPR_IVPTBR:
 113       case IPR_DC_MODE:
 114       case IPR_MAF_MODE:
 115       case IPR_ISR:
 116       case IPR_EXC_ADDR:
 117       case IPR_IC_PERR_STAT:
 118       case IPR_DC_PERR_STAT:
 119       case IPR_MCSR:
 120       case IPR_ASTRR:
 121       case IPR_ASTER:
 122       case IPR_SIRR:
 123       case IPR_ICSR:
 124       case IPR_ICM:
 125       case IPR_DTB_CM:
 126       case IPR_IPLR:
 127       case IPR_INTID:
 128       case IPR_PMCTR:
 129         // no side-effect
 130         retval = ipr[idx];
 131         break;
 132
 133       case IPR_CC:
 134         retval |= ipr[idx] & ULL(0xffffffff00000000);
 135         retval |= tc->getCpuPtr()->curCycle()  & ULL(0x00000000ffffffff);
 136         break;
 137
 138       case IPR_VA:
 139         retval = ipr[idx];
 140         break;
 141
 142       case IPR_VA_FORM:
 143       case IPR_MM_STAT:
 144       case IPR_IFAULT_VA_FORM:
 145       case IPR_EXC_MASK:
 146       case IPR_EXC_SUM:
 147         retval = ipr[idx];
 148         break;
 149
 150       case IPR_DTB_PTE:
 151         {
 152             TlbEntry &entry = getDTBPtr(tc)->index(1);
 153
 154             retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32;
 155             retval |= ((uint64_t)entry.xre & ULL(0xf)) << 8;
 156             retval |= ((uint64_t)entry.xwe & ULL(0xf)) << 12;
 157             retval |= ((uint64_t)entry.fonr & ULL(0x1)) << 1;
 158             retval |= ((uint64_t)entry.fonw & ULL(0x1))<< 2;
 159             retval |= ((uint64_t)entry.asma & ULL(0x1)) << 4;
 160             retval |= ((uint64_t)entry.asn & ULL(0x7f)) << 57;
 161         }
 162         break;
 163
 164         // write only registers
 165       case IPR_HWINT_CLR:
 166       case IPR_SL_XMIT:
 167       case IPR_DC_FLUSH:
 168       case IPR_IC_FLUSH:
 169       case IPR_ALT_MODE:
 170       case IPR_DTB_IA:
 171       case IPR_DTB_IAP:
 172       case IPR_ITB_IA:
 173       case IPR_ITB_IAP:
 174         panic("Tried to read write only register %d\n", idx);
 175         break;
 176
 177       default:
 178         // invalid IPR
 179         panic("Tried to read from invalid ipr %d\n", idx);
 180         break;
 181     }
 182
 183     return retval;
 184 }
 185
 186 // Cause the simulator to break when changing to the following IPL
 187 int break_ipl = -1;
 188
 189 void
 190 ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
 191 {
 192     auto *stats = dynamic_cast<AlphaISA::Kernel::Statistics *>(
 193             tc->getKernelStats());
 194     assert(stats || !tc->getKernelStats());
 195     switch (idx) {
 196       case IPR_PALtemp0:
 197       case IPR_PALtemp1:
 198       case IPR_PALtemp2:
 199       case IPR_PALtemp3:
 200       case IPR_PALtemp4:
 201       case IPR_PALtemp5:
 202       case IPR_PALtemp6:
 203       case IPR_PALtemp7:
 204       case IPR_PALtemp8:
 205       case IPR_PALtemp9:
 206       case IPR_PALtemp10:
 207       case IPR_PALtemp11:
 208       case IPR_PALtemp12:
 209       case IPR_PALtemp13:
 210       case IPR_PALtemp14:
 211       case IPR_PALtemp15:
 212       case IPR_PALtemp16:
 213       case IPR_PALtemp17:
 214       case IPR_PALtemp18:
 215       case IPR_PALtemp19:
 216       case IPR_PALtemp20:
 217       case IPR_PALtemp21:
 218       case IPR_PALtemp22:
 219       case IPR_PAL_BASE:
 220       case IPR_IC_PERR_STAT:
 221       case IPR_DC_PERR_STAT:
 222       case IPR_PMCTR:
 223         // write entire quad w/ no side-effect
 224         ipr[idx] = val;
 225         break;
 226
 227       case IPR_CC_CTL:
 228         // This IPR resets the cycle counter.  We assume this only
 229         // happens once... let's verify that.
 230         assert(ipr[idx] == 0);
 231         ipr[idx] = 1;
 232         break;
 233
 234       case IPR_CC:
 235         // This IPR only writes the upper 64 bits.  It's ok to write
 236         // all 64 here since we mask out the lower 32 in rpcc (see
 237         // isa_desc).
 238         ipr[idx] = val;
 239         break;
 240
 241       case IPR_PALtemp23:
 242         // write entire quad w/ no side-effect
 243         if (stats)
 244             stats->context(ipr[idx], val, tc);
 245         ipr[idx] = val;
 246         break;
 247
 248       case IPR_DTB_PTE:
 249         // write entire quad w/ no side-effect, tag is forthcoming
 250         ipr[idx] = val;
 251         break;
 252
 253       case IPR_EXC_ADDR:
 254         // second least significant bit in PC is always zero
 255         ipr[idx] = val & ~2;
 256         break;
 257
 258       case IPR_ASTRR:
 259       case IPR_ASTER:
 260         // only write least significant four bits - privilege mask
 261         ipr[idx] = val & 0xf;
 262         break;
 263
 264       case IPR_IPLR:
 265         // only write least significant five bits - interrupt level
 266         ipr[idx] = val & 0x1f;
 267         if (stats)
 268             stats->swpipl(ipr[idx]);
 269         break;
 270
 271       case IPR_DTB_CM:
 272         if (val & 0x18) {
 273             if (stats)
 274                 stats->mode(Kernel::user, tc);
 275         } else {
 276             if (stats)
 277                 stats->mode(Kernel::kernel, tc);
 278         }
 279         M5_FALLTHROUGH;
 280
 281       case IPR_ICM:
 282         // only write two mode bits - processor mode
 283         ipr[idx] = val & 0x18;
 284         break;
 285
 286       case IPR_ALT_MODE:
 287         // only write two mode bits - processor mode
 288         ipr[idx] = val & 0x18;
 289         break;
 290
 291       case IPR_MCSR:
 292         // more here after optimization...
 293         ipr[idx] = val;
 294         break;
 295
 296       case IPR_SIRR:
 297         // only write software interrupt mask
 298         ipr[idx] = val & 0x7fff0;
 299         break;
 300
 301       case IPR_ICSR:
 302         ipr[idx] = val & ULL(0xffffff0300);
 303         break;
 304
 305       case IPR_IVPTBR:
 306       case IPR_MVPTBR:
 307         ipr[idx] = val & ULL(0xffffffffc0000000);
 308         break;
 309
 310       case IPR_DC_TEST_CTL:
 311         ipr[idx] = val & 0x1ffb;
 312         break;
 313
 314       case IPR_DC_MODE:
 315       case IPR_MAF_MODE:
 316         ipr[idx] = val & 0x3f;
 317         break;
 318
 319       case IPR_ITB_ASN:
 320         ipr[idx] = val & 0x7f0;
 321         break;
 322
 323       case IPR_DTB_ASN:
 324         ipr[idx] = val & ULL(0xfe00000000000000);
 325         break;
 326
 327       case IPR_EXC_SUM:
 328       case IPR_EXC_MASK:
 329         // any write to this register clears it
 330         ipr[idx] = 0;
 331         break;
 332
 333       case IPR_INTID:
 334       case IPR_SL_RCV:
 335       case IPR_MM_STAT:
 336       case IPR_ITB_PTE_TEMP:
 337       case IPR_DTB_PTE_TEMP:
 338         // read-only registers
 339         panic("Tried to write read only ipr %d\n", idx);
 340
 341       case IPR_HWINT_CLR:
 342       case IPR_SL_XMIT:
 343       case IPR_DC_FLUSH:
 344       case IPR_IC_FLUSH:
 345         // the following are write only
 346         ipr[idx] = val;
 347         break;
 348
 349       case IPR_DTB_IA:
 350         // really a control write
 351         ipr[idx] = 0;
 352
 353         getDTBPtr(tc)->flushAll();
 354         break;
 355
 356       case IPR_DTB_IAP:
 357         // really a control write
 358         ipr[idx] = 0;
 359
 360         getDTBPtr(tc)->flushProcesses();
 361         break;
 362
 363       case IPR_DTB_IS:
 364         // really a control write
 365         ipr[idx] = val;
 366
 367         getDTBPtr(tc)->flushAddr(val, DTB_ASN_ASN(ipr[IPR_DTB_ASN]));
 368         break;
 369
 370       case IPR_DTB_TAG: {
 371           struct TlbEntry entry;
 372
 373           // FIXME: granularity hints NYI...
 374           if (DTB_PTE_GH(ipr[IPR_DTB_PTE]) != 0)
 375               panic("PTE GH field != 0");
 376
 377           // write entire quad
 378           ipr[idx] = val;
 379
 380           // construct PTE for new entry
 381           entry.ppn = DTB_PTE_PPN(ipr[IPR_DTB_PTE]);
 382           entry.xre = DTB_PTE_XRE(ipr[IPR_DTB_PTE]);
 383           entry.xwe = DTB_PTE_XWE(ipr[IPR_DTB_PTE]);
 384           entry.fonr = DTB_PTE_FONR(ipr[IPR_DTB_PTE]);
 385           entry.fonw = DTB_PTE_FONW(ipr[IPR_DTB_PTE]);
 386           entry.asma = DTB_PTE_ASMA(ipr[IPR_DTB_PTE]);
 387           entry.asn = DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
 388
 389           // insert new TAG/PTE value into data TLB
 390           getDTBPtr(tc)->insert(val, entry);
 391       }
 392         break;
 393
 394       case IPR_ITB_PTE: {
 395           struct TlbEntry entry;
 396
 397           // FIXME: granularity hints NYI...
 398           if (ITB_PTE_GH(val) != 0)
 399               panic("PTE GH field != 0");
 400
 401           // write entire quad
 402           ipr[idx] = val;
 403
 404           // construct PTE for new entry
 405           entry.ppn = ITB_PTE_PPN(val);
 406           entry.xre = ITB_PTE_XRE(val);
 407           entry.xwe = 0;
 408           entry.fonr = ITB_PTE_FONR(val);
 409           entry.fonw = ITB_PTE_FONW(val);
 410           entry.asma = ITB_PTE_ASMA(val);
 411           entry.asn = ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
 412
 413           // insert new TAG/PTE value into data TLB
 414           getITBPtr(tc)->insert(ipr[IPR_ITB_TAG], entry);
 415       }
 416         break;
 417
 418       case IPR_ITB_IA:
 419         // really a control write
 420         ipr[idx] = 0;
 421
 422         getITBPtr(tc)->flushAll();
 423         break;
 424
 425       case IPR_ITB_IAP:
 426         // really a control write
 427         ipr[idx] = 0;
 428
 429         getITBPtr(tc)->flushProcesses();
 430         break;
 431
 432       case IPR_ITB_IS:
 433         // really a control write
 434         ipr[idx] = val;
 435
 436         getITBPtr(tc)->flushAddr(val, ITB_ASN_ASN(ipr[IPR_ITB_ASN]));
 437         break;
 438
 439       default:
 440         // invalid IPR
 441         panic("Tried to write to invalid ipr %d\n", idx);
 442     }
 443
 444     // no error...
 445 }
 446
 447 void
 448 copyIprs(ThreadContext *src, ThreadContext *dest)
 449 {
 450     for (int i = 0; i < NumInternalProcRegs; ++i)
 451         dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
 452 }
 453
 454 } // namespace AlphaISA