2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
32 #include "arch/alpha/faults.hh"
33 #include "arch/alpha/isa_traits.hh"
34 #include "arch/alpha/kernel_stats.hh"
35 #include "arch/alpha/osfpal.hh"
36 #include "arch/alpha/tlb.hh"
37 #include "arch/alpha/kgdb.h"
38 #include "base/remote_gdb.hh"
39 #include "base/stats/events.hh"
40 #include "config/full_system.hh"
41 #include "cpu/base.hh"
42 #include "cpu/simple_thread.hh"
43 #include "cpu/thread_context.hh"
44 #include "sim/debug.hh"
45 #include "sim/sim_exit.hh"
51 ////////////////////////////////////////////////////////////////////////
53 // Machine dependent functions
56 initCPU(ThreadContext
*tc
, int cpuId
)
60 tc
->setIntReg(16, cpuId
);
61 tc
->setIntReg(0, cpuId
);
63 AlphaFault
*reset
= new ResetFault
;
65 tc
->setPC(tc
->readMiscRegNoEffect(IPR_PAL_BASE
) + reset
->vect());
66 tc
->setNextPC(tc
->readPC() + sizeof(MachInst
));
74 processInterrupts(CPU
*cpu
)
76 //Check if there are any outstanding interrupts
77 //Handle the interrupts
81 if (cpu
->readMiscRegNoEffect(IPR_ASTRR
))
82 panic("asynchronous traps not implemented\n");
84 if (cpu
->readMiscRegNoEffect(IPR_SIRR
)) {
85 for (int i
= INTLEVEL_SOFTWARE_MIN
;
86 i
< INTLEVEL_SOFTWARE_MAX
; i
++) {
87 if (cpu
->readMiscRegNoEffect(IPR_SIRR
) & (ULL(1) << i
)) {
88 // See table 4-19 of the 21164 hardware reference
89 ipl
= (i
- INTLEVEL_SOFTWARE_MIN
) + 1;
90 summary
|= (ULL(1) << i
);
95 uint64_t interrupts
= cpu
->intr_status();
98 for (int i
= INTLEVEL_EXTERNAL_MIN
;
99 i
< INTLEVEL_EXTERNAL_MAX
; i
++) {
100 if (interrupts
& (ULL(1) << i
)) {
101 // See table 4-19 of the 21164 hardware reference
103 summary
|= (ULL(1) << i
);
108 if (ipl
&& ipl
> cpu
->readMiscRegNoEffect(IPR_IPLR
)) {
109 cpu
->setMiscRegNoEffect(IPR_ISR
, summary
);
110 cpu
->setMiscRegNoEffect(IPR_INTID
, ipl
);
111 cpu
->trap(new InterruptFault
);
112 DPRINTF(Flow
, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
113 cpu
->readMiscRegNoEffect(IPR_IPLR
), ipl
, summary
);
120 zeroRegisters(CPU
*cpu
)
122 // Insure ISA semantics
123 // (no longer very clean due to the change in setIntReg() in the
124 // cpu model. Consider changing later.)
125 cpu
->thread
->setIntReg(ZeroReg
, 0);
126 cpu
->thread
->setFloatReg(ZeroReg
, 0.0);
130 MiscRegFile::getInstAsid()
132 return ITB_ASN_ASN(ipr
[IPR_ITB_ASN
]);
136 MiscRegFile::getDataAsid()
138 return DTB_ASN_ASN(ipr
[IPR_DTB_ASN
]);
143 ////////////////////////////////////////////////////////////////////////
148 initIPRs(ThreadContext
*tc
, int cpuId
)
150 for (int i
= 0; i
< NumInternalProcRegs
; ++i
) {
151 tc
->setMiscRegNoEffect(i
, 0);
154 tc
->setMiscRegNoEffect(IPR_PAL_BASE
, PalBase
);
155 tc
->setMiscRegNoEffect(IPR_MCSR
, 0x6);
156 tc
->setMiscRegNoEffect(IPR_PALtemp16
, cpuId
);
160 MiscRegFile::readIpr(int idx
, ThreadContext
*tc
)
162 uint64_t retval
= 0; // return value, default 0
196 case IPR_IC_PERR_STAT
:
197 case IPR_DC_PERR_STAT
:
213 retval
|= ipr
[idx
] & ULL(0xffffffff00000000);
214 retval
|= tc
->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff);
223 case IPR_IFAULT_VA_FORM
:
232 = tc
->getDTBPtr()->index(!tc
->misspeculating());
234 retval
|= ((uint64_t)entry
.ppn
& ULL(0x7ffffff)) << 32;
235 retval
|= ((uint64_t)entry
.xre
& ULL(0xf)) << 8;
236 retval
|= ((uint64_t)entry
.xwe
& ULL(0xf)) << 12;
237 retval
|= ((uint64_t)entry
.fonr
& ULL(0x1)) << 1;
238 retval
|= ((uint64_t)entry
.fonw
& ULL(0x1))<< 2;
239 retval
|= ((uint64_t)entry
.asma
& ULL(0x1)) << 4;
240 retval
|= ((uint64_t)entry
.asn
& ULL(0x7f)) << 57;
244 // write only registers
254 panic("Tried to read write only register %d\n", idx
);
259 panic("Tried to read from invalid ipr %d\n", idx
);
267 // Cause the simulator to break when changing to the following IPL
272 MiscRegFile::setIpr(int idx
, uint64_t val
, ThreadContext
*tc
)
276 if (tc
->misspeculating())
304 case IPR_IC_PERR_STAT
:
305 case IPR_DC_PERR_STAT
:
307 // write entire quad w/ no side-effect
312 // This IPR resets the cycle counter. We assume this only
313 // happens once... let's verify that.
314 assert(ipr
[idx
] == 0);
319 // This IPR only writes the upper 64 bits. It's ok to write
320 // all 64 here since we mask out the lower 32 in rpcc (see
326 // write entire quad w/ no side-effect
330 if (tc
->getKernelStats())
331 tc
->getKernelStats()->context(old
, val
, tc
);
336 // write entire quad w/ no side-effect, tag is forthcoming
341 // second least significant bit in PC is always zero
347 // only write least significant four bits - privilege mask
348 ipr
[idx
] = val
& 0xf;
353 if (break_ipl
!= -1 && break_ipl
== (val
& 0x1f))
357 // only write least significant five bits - interrupt level
358 ipr
[idx
] = val
& 0x1f;
360 if (tc
->getKernelStats())
361 tc
->getKernelStats()->swpipl(ipr
[idx
]);
368 if (tc
->getKernelStats())
369 tc
->getKernelStats()->mode(Kernel::user
, tc
);
371 if (tc
->getKernelStats())
372 tc
->getKernelStats()->mode(Kernel::kernel
, tc
);
377 // only write two mode bits - processor mode
378 ipr
[idx
] = val
& 0x18;
382 // only write two mode bits - processor mode
383 ipr
[idx
] = val
& 0x18;
387 // more here after optimization...
392 // only write software interrupt mask
393 ipr
[idx
] = val
& 0x7fff0;
397 ipr
[idx
] = val
& ULL(0xffffff0300);
402 ipr
[idx
] = val
& ULL(0xffffffffc0000000);
405 case IPR_DC_TEST_CTL
:
406 ipr
[idx
] = val
& 0x1ffb;
411 ipr
[idx
] = val
& 0x3f;
415 ipr
[idx
] = val
& 0x7f0;
419 ipr
[idx
] = val
& ULL(0xfe00000000000000);
424 // any write to this register clears it
431 case IPR_ITB_PTE_TEMP
:
432 case IPR_DTB_PTE_TEMP
:
433 // read-only registers
434 panic("Tried to write read only ipr %d\n", idx
);
440 // the following are write only
445 // really a control write
448 tc
->getDTBPtr()->flushAll();
452 // really a control write
455 tc
->getDTBPtr()->flushProcesses();
459 // really a control write
462 tc
->getDTBPtr()->flushAddr(val
, DTB_ASN_ASN(ipr
[IPR_DTB_ASN
]));
466 struct TlbEntry entry
;
468 // FIXME: granularity hints NYI...
469 if (DTB_PTE_GH(ipr
[IPR_DTB_PTE
]) != 0)
470 panic("PTE GH field != 0");
475 // construct PTE for new entry
476 entry
.ppn
= DTB_PTE_PPN(ipr
[IPR_DTB_PTE
]);
477 entry
.xre
= DTB_PTE_XRE(ipr
[IPR_DTB_PTE
]);
478 entry
.xwe
= DTB_PTE_XWE(ipr
[IPR_DTB_PTE
]);
479 entry
.fonr
= DTB_PTE_FONR(ipr
[IPR_DTB_PTE
]);
480 entry
.fonw
= DTB_PTE_FONW(ipr
[IPR_DTB_PTE
]);
481 entry
.asma
= DTB_PTE_ASMA(ipr
[IPR_DTB_PTE
]);
482 entry
.asn
= DTB_ASN_ASN(ipr
[IPR_DTB_ASN
]);
484 // insert new TAG/PTE value into data TLB
485 tc
->getDTBPtr()->insert(val
, entry
);
490 struct TlbEntry entry
;
492 // FIXME: granularity hints NYI...
493 if (ITB_PTE_GH(val
) != 0)
494 panic("PTE GH field != 0");
499 // construct PTE for new entry
500 entry
.ppn
= ITB_PTE_PPN(val
);
501 entry
.xre
= ITB_PTE_XRE(val
);
503 entry
.fonr
= ITB_PTE_FONR(val
);
504 entry
.fonw
= ITB_PTE_FONW(val
);
505 entry
.asma
= ITB_PTE_ASMA(val
);
506 entry
.asn
= ITB_ASN_ASN(ipr
[IPR_ITB_ASN
]);
508 // insert new TAG/PTE value into data TLB
509 tc
->getITBPtr()->insert(ipr
[IPR_ITB_TAG
], entry
);
514 // really a control write
517 tc
->getITBPtr()->flushAll();
521 // really a control write
524 tc
->getITBPtr()->flushProcesses();
528 // really a control write
531 tc
->getITBPtr()->flushAddr(val
, ITB_ASN_ASN(ipr
[IPR_ITB_ASN
]));
536 panic("Tried to write to invalid ipr %d\n", idx
);
543 copyIprs(ThreadContext
*src
, ThreadContext
*dest
)
545 for (int i
= 0; i
< NumInternalProcRegs
; ++i
)
546 dest
->setMiscRegNoEffect(i
, src
->readMiscRegNoEffect(i
));
549 } // namespace AlphaISA
553 using namespace AlphaISA
;
556 SimpleThread::hwrei()
558 if (!(readPC() & 0x3))
559 return new UnimplementedOpcodeFault
;
561 setNextPC(readMiscRegNoEffect(IPR_EXC_ADDR
));
563 if (!misspeculating()) {
565 kernelStats
->hwrei();
568 // FIXME: XXX check for interrupts? XXX
573 * Check for special simulator handling of specific PAL calls.
574 * If return value is false, actual PAL call will be suppressed.
577 SimpleThread::simPalCheck(int palFunc
)
580 kernelStats
->callpal(palFunc
, tc
);
585 if (--System::numSystemsRunning
== 0)
586 exitSimLoop("all cpus halted");
591 if (system
->breakpoint())
599 #endif // FULL_SYSTEM