2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
32 #include "arch/alpha/faults.hh"
33 #include "arch/alpha/isa_traits.hh"
34 #include "arch/alpha/kernel_stats.hh"
35 #include "arch/alpha/osfpal.hh"
36 #include "arch/alpha/tlb.hh"
37 #include "arch/alpha/kgdb.h"
38 #include "base/cp_annotate.hh"
39 #include "base/debug.hh"
40 #include "base/remote_gdb.hh"
41 #include "base/stats/events.hh"
42 #include "config/full_system.hh"
43 #include "cpu/base.hh"
44 #include "cpu/simple_thread.hh"
45 #include "cpu/thread_context.hh"
46 #include "sim/sim_exit.hh"
52 ////////////////////////////////////////////////////////////////////////
54 // Machine dependent functions
57 initCPU(ThreadContext
*tc
, int cpuId
)
61 tc
->setIntReg(16, cpuId
);
62 tc
->setIntReg(0, cpuId
);
64 AlphaFault
*reset
= new ResetFault
;
66 tc
->setPC(tc
->readMiscRegNoEffect(IPR_PAL_BASE
) + reset
->vect());
67 tc
->setNextPC(tc
->readPC() + sizeof(MachInst
));
75 processInterrupts(CPU
*cpu
)
77 //Check if there are any outstanding interrupts
78 //Handle the interrupts
82 if (cpu
->readMiscRegNoEffect(IPR_ASTRR
))
83 panic("asynchronous traps not implemented\n");
85 if (cpu
->readMiscRegNoEffect(IPR_SIRR
)) {
86 for (int i
= INTLEVEL_SOFTWARE_MIN
;
87 i
< INTLEVEL_SOFTWARE_MAX
; i
++) {
88 if (cpu
->readMiscRegNoEffect(IPR_SIRR
) & (ULL(1) << i
)) {
89 // See table 4-19 of the 21164 hardware reference
90 ipl
= (i
- INTLEVEL_SOFTWARE_MIN
) + 1;
91 summary
|= (ULL(1) << i
);
96 uint64_t interrupts
= cpu
->intr_status();
99 for (int i
= INTLEVEL_EXTERNAL_MIN
;
100 i
< INTLEVEL_EXTERNAL_MAX
; i
++) {
101 if (interrupts
& (ULL(1) << i
)) {
102 // See table 4-19 of the 21164 hardware reference
104 summary
|= (ULL(1) << i
);
109 if (ipl
&& ipl
> cpu
->readMiscRegNoEffect(IPR_IPLR
)) {
110 cpu
->setMiscRegNoEffect(IPR_ISR
, summary
);
111 cpu
->setMiscRegNoEffect(IPR_INTID
, ipl
);
112 cpu
->trap(new InterruptFault
);
113 DPRINTF(Flow
, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
114 cpu
->readMiscRegNoEffect(IPR_IPLR
), ipl
, summary
);
121 zeroRegisters(CPU
*cpu
)
123 // Insure ISA semantics
124 // (no longer very clean due to the change in setIntReg() in the
125 // cpu model. Consider changing later.)
126 cpu
->thread
->setIntReg(ZeroReg
, 0);
127 cpu
->thread
->setFloatReg(ZeroReg
, 0.0);
131 MiscRegFile::getInstAsid()
133 return ITB_ASN_ASN(ipr
[IPR_ITB_ASN
]);
137 MiscRegFile::getDataAsid()
139 return DTB_ASN_ASN(ipr
[IPR_DTB_ASN
]);
144 ////////////////////////////////////////////////////////////////////////
149 initIPRs(ThreadContext
*tc
, int cpuId
)
151 for (int i
= 0; i
< NumInternalProcRegs
; ++i
) {
152 tc
->setMiscRegNoEffect(i
, 0);
155 tc
->setMiscRegNoEffect(IPR_PAL_BASE
, PalBase
);
156 tc
->setMiscRegNoEffect(IPR_MCSR
, 0x6);
157 tc
->setMiscRegNoEffect(IPR_PALtemp16
, cpuId
);
161 MiscRegFile::readIpr(int idx
, ThreadContext
*tc
)
163 uint64_t retval
= 0; // return value, default 0
197 case IPR_IC_PERR_STAT
:
198 case IPR_DC_PERR_STAT
:
214 retval
|= ipr
[idx
] & ULL(0xffffffff00000000);
215 retval
|= tc
->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff);
224 case IPR_IFAULT_VA_FORM
:
233 = tc
->getDTBPtr()->index(!tc
->misspeculating());
235 retval
|= ((uint64_t)entry
.ppn
& ULL(0x7ffffff)) << 32;
236 retval
|= ((uint64_t)entry
.xre
& ULL(0xf)) << 8;
237 retval
|= ((uint64_t)entry
.xwe
& ULL(0xf)) << 12;
238 retval
|= ((uint64_t)entry
.fonr
& ULL(0x1)) << 1;
239 retval
|= ((uint64_t)entry
.fonw
& ULL(0x1))<< 2;
240 retval
|= ((uint64_t)entry
.asma
& ULL(0x1)) << 4;
241 retval
|= ((uint64_t)entry
.asn
& ULL(0x7f)) << 57;
245 // write only registers
255 panic("Tried to read write only register %d\n", idx
);
260 panic("Tried to read from invalid ipr %d\n", idx
);
268 // Cause the simulator to break when changing to the following IPL
273 MiscRegFile::setIpr(int idx
, uint64_t val
, ThreadContext
*tc
)
277 if (tc
->misspeculating())
305 case IPR_IC_PERR_STAT
:
306 case IPR_DC_PERR_STAT
:
308 // write entire quad w/ no side-effect
313 // This IPR resets the cycle counter. We assume this only
314 // happens once... let's verify that.
315 assert(ipr
[idx
] == 0);
320 // This IPR only writes the upper 64 bits. It's ok to write
321 // all 64 here since we mask out the lower 32 in rpcc (see
327 // write entire quad w/ no side-effect
331 if (tc
->getKernelStats())
332 tc
->getKernelStats()->context(old
, val
, tc
);
337 // write entire quad w/ no side-effect, tag is forthcoming
342 // second least significant bit in PC is always zero
348 // only write least significant four bits - privilege mask
349 ipr
[idx
] = val
& 0xf;
354 if (break_ipl
!= -1 && break_ipl
== (int)(val
& 0x1f))
358 // only write least significant five bits - interrupt level
359 ipr
[idx
] = val
& 0x1f;
361 if (tc
->getKernelStats())
362 tc
->getKernelStats()->swpipl(ipr
[idx
]);
369 if (tc
->getKernelStats())
370 tc
->getKernelStats()->mode(Kernel::user
, tc
);
372 if (tc
->getKernelStats())
373 tc
->getKernelStats()->mode(Kernel::kernel
, tc
);
378 // only write two mode bits - processor mode
379 ipr
[idx
] = val
& 0x18;
383 // only write two mode bits - processor mode
384 ipr
[idx
] = val
& 0x18;
388 // more here after optimization...
393 // only write software interrupt mask
394 ipr
[idx
] = val
& 0x7fff0;
398 ipr
[idx
] = val
& ULL(0xffffff0300);
403 ipr
[idx
] = val
& ULL(0xffffffffc0000000);
406 case IPR_DC_TEST_CTL
:
407 ipr
[idx
] = val
& 0x1ffb;
412 ipr
[idx
] = val
& 0x3f;
416 ipr
[idx
] = val
& 0x7f0;
420 ipr
[idx
] = val
& ULL(0xfe00000000000000);
425 // any write to this register clears it
432 case IPR_ITB_PTE_TEMP
:
433 case IPR_DTB_PTE_TEMP
:
434 // read-only registers
435 panic("Tried to write read only ipr %d\n", idx
);
441 // the following are write only
446 // really a control write
449 tc
->getDTBPtr()->flushAll();
453 // really a control write
456 tc
->getDTBPtr()->flushProcesses();
460 // really a control write
463 tc
->getDTBPtr()->flushAddr(val
, DTB_ASN_ASN(ipr
[IPR_DTB_ASN
]));
467 struct TlbEntry entry
;
469 // FIXME: granularity hints NYI...
470 if (DTB_PTE_GH(ipr
[IPR_DTB_PTE
]) != 0)
471 panic("PTE GH field != 0");
476 // construct PTE for new entry
477 entry
.ppn
= DTB_PTE_PPN(ipr
[IPR_DTB_PTE
]);
478 entry
.xre
= DTB_PTE_XRE(ipr
[IPR_DTB_PTE
]);
479 entry
.xwe
= DTB_PTE_XWE(ipr
[IPR_DTB_PTE
]);
480 entry
.fonr
= DTB_PTE_FONR(ipr
[IPR_DTB_PTE
]);
481 entry
.fonw
= DTB_PTE_FONW(ipr
[IPR_DTB_PTE
]);
482 entry
.asma
= DTB_PTE_ASMA(ipr
[IPR_DTB_PTE
]);
483 entry
.asn
= DTB_ASN_ASN(ipr
[IPR_DTB_ASN
]);
485 // insert new TAG/PTE value into data TLB
486 tc
->getDTBPtr()->insert(val
, entry
);
491 struct TlbEntry entry
;
493 // FIXME: granularity hints NYI...
494 if (ITB_PTE_GH(val
) != 0)
495 panic("PTE GH field != 0");
500 // construct PTE for new entry
501 entry
.ppn
= ITB_PTE_PPN(val
);
502 entry
.xre
= ITB_PTE_XRE(val
);
504 entry
.fonr
= ITB_PTE_FONR(val
);
505 entry
.fonw
= ITB_PTE_FONW(val
);
506 entry
.asma
= ITB_PTE_ASMA(val
);
507 entry
.asn
= ITB_ASN_ASN(ipr
[IPR_ITB_ASN
]);
509 // insert new TAG/PTE value into data TLB
510 tc
->getITBPtr()->insert(ipr
[IPR_ITB_TAG
], entry
);
515 // really a control write
518 tc
->getITBPtr()->flushAll();
522 // really a control write
525 tc
->getITBPtr()->flushProcesses();
529 // really a control write
532 tc
->getITBPtr()->flushAddr(val
, ITB_ASN_ASN(ipr
[IPR_ITB_ASN
]));
537 panic("Tried to write to invalid ipr %d\n", idx
);
544 copyIprs(ThreadContext
*src
, ThreadContext
*dest
)
546 for (int i
= 0; i
< NumInternalProcRegs
; ++i
)
547 dest
->setMiscRegNoEffect(i
, src
->readMiscRegNoEffect(i
));
550 } // namespace AlphaISA
554 using namespace AlphaISA
;
557 SimpleThread::hwrei()
559 if (!(readPC() & 0x3))
560 return new UnimplementedOpcodeFault
;
562 setNextPC(readMiscRegNoEffect(IPR_EXC_ADDR
));
564 CPA::cpa()->swAutoBegin(tc
, readNextPC());
566 if (!misspeculating()) {
568 kernelStats
->hwrei();
571 // FIXME: XXX check for interrupts? XXX
576 * Check for special simulator handling of specific PAL calls.
577 * If return value is false, actual PAL call will be suppressed.
580 SimpleThread::simPalCheck(int palFunc
)
583 kernelStats
->callpal(palFunc
, tc
);
588 if (--System::numSystemsRunning
== 0)
589 exitSimLoop("all cpus halted");
594 if (system
->breakpoint())
602 #endif // FULL_SYSTEM