2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
32 #include "arch/alpha/faults.hh"
33 #include "arch/alpha/isa_traits.hh"
34 #include "arch/alpha/kernel_stats.hh"
35 #include "arch/alpha/osfpal.hh"
36 #include "arch/alpha/tlb.hh"
37 #include "arch/alpha/kgdb.h"
38 #include "base/cp_annotate.hh"
39 #include "base/debug.hh"
40 #include "base/remote_gdb.hh"
41 #include "base/stats/events.hh"
42 #include "config/full_system.hh"
43 #include "cpu/base.hh"
44 #include "cpu/simple_thread.hh"
45 #include "cpu/thread_context.hh"
46 #include "sim/sim_exit.hh"
52 ////////////////////////////////////////////////////////////////////////
54 // Machine dependent functions
57 initCPU(ThreadContext
*tc
, int cpuId
)
61 tc
->setIntReg(16, cpuId
);
62 tc
->setIntReg(0, cpuId
);
64 AlphaFault
*reset
= new ResetFault
;
66 tc
->setPC(tc
->readMiscRegNoEffect(IPR_PAL_BASE
) + reset
->vect());
67 tc
->setNextPC(tc
->readPC() + sizeof(MachInst
));
75 processInterrupts(CPU
*cpu
)
77 //Check if there are any outstanding interrupts
78 //Handle the interrupts
82 if (cpu
->readMiscRegNoEffect(IPR_ASTRR
))
83 panic("asynchronous traps not implemented\n");
85 if (cpu
->readMiscRegNoEffect(IPR_SIRR
)) {
86 for (int i
= INTLEVEL_SOFTWARE_MIN
;
87 i
< INTLEVEL_SOFTWARE_MAX
; i
++) {
88 if (cpu
->readMiscRegNoEffect(IPR_SIRR
) & (ULL(1) << i
)) {
89 // See table 4-19 of the 21164 hardware reference
90 ipl
= (i
- INTLEVEL_SOFTWARE_MIN
) + 1;
91 summary
|= (ULL(1) << i
);
96 uint64_t interrupts
= cpu
->intr_status();
99 for (int i
= INTLEVEL_EXTERNAL_MIN
;
100 i
< INTLEVEL_EXTERNAL_MAX
; i
++) {
101 if (interrupts
& (ULL(1) << i
)) {
102 // See table 4-19 of the 21164 hardware reference
104 summary
|= (ULL(1) << i
);
109 if (ipl
&& ipl
> cpu
->readMiscRegNoEffect(IPR_IPLR
)) {
110 cpu
->setMiscRegNoEffect(IPR_ISR
, summary
);
111 cpu
->setMiscRegNoEffect(IPR_INTID
, ipl
);
112 cpu
->trap(new InterruptFault
);
113 DPRINTF(Flow
, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
114 cpu
->readMiscRegNoEffect(IPR_IPLR
), ipl
, summary
);
121 zeroRegisters(CPU
*cpu
)
123 // Insure ISA semantics
124 // (no longer very clean due to the change in setIntReg() in the
125 // cpu model. Consider changing later.)
126 cpu
->thread
->setIntReg(ZeroReg
, 0);
127 cpu
->thread
->setFloatReg(ZeroReg
, 0.0);
132 ////////////////////////////////////////////////////////////////////////
137 initIPRs(ThreadContext
*tc
, int cpuId
)
139 for (int i
= 0; i
< NumInternalProcRegs
; ++i
) {
140 tc
->setMiscRegNoEffect(i
, 0);
143 tc
->setMiscRegNoEffect(IPR_PAL_BASE
, PalBase
);
144 tc
->setMiscRegNoEffect(IPR_MCSR
, 0x6);
145 tc
->setMiscRegNoEffect(IPR_PALtemp16
, cpuId
);
149 ISA::readIpr(int idx
, ThreadContext
*tc
)
151 uint64_t retval
= 0; // return value, default 0
185 case IPR_IC_PERR_STAT
:
186 case IPR_DC_PERR_STAT
:
202 retval
|= ipr
[idx
] & ULL(0xffffffff00000000);
203 retval
|= tc
->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff);
212 case IPR_IFAULT_VA_FORM
:
221 = tc
->getDTBPtr()->index(!tc
->misspeculating());
223 retval
|= ((uint64_t)entry
.ppn
& ULL(0x7ffffff)) << 32;
224 retval
|= ((uint64_t)entry
.xre
& ULL(0xf)) << 8;
225 retval
|= ((uint64_t)entry
.xwe
& ULL(0xf)) << 12;
226 retval
|= ((uint64_t)entry
.fonr
& ULL(0x1)) << 1;
227 retval
|= ((uint64_t)entry
.fonw
& ULL(0x1))<< 2;
228 retval
|= ((uint64_t)entry
.asma
& ULL(0x1)) << 4;
229 retval
|= ((uint64_t)entry
.asn
& ULL(0x7f)) << 57;
233 // write only registers
243 panic("Tried to read write only register %d\n", idx
);
248 panic("Tried to read from invalid ipr %d\n", idx
);
256 // Cause the simulator to break when changing to the following IPL
261 ISA::setIpr(int idx
, uint64_t val
, ThreadContext
*tc
)
265 if (tc
->misspeculating())
293 case IPR_IC_PERR_STAT
:
294 case IPR_DC_PERR_STAT
:
296 // write entire quad w/ no side-effect
301 // This IPR resets the cycle counter. We assume this only
302 // happens once... let's verify that.
303 assert(ipr
[idx
] == 0);
308 // This IPR only writes the upper 64 bits. It's ok to write
309 // all 64 here since we mask out the lower 32 in rpcc (see
315 // write entire quad w/ no side-effect
319 if (tc
->getKernelStats())
320 tc
->getKernelStats()->context(old
, val
, tc
);
325 // write entire quad w/ no side-effect, tag is forthcoming
330 // second least significant bit in PC is always zero
336 // only write least significant four bits - privilege mask
337 ipr
[idx
] = val
& 0xf;
342 if (break_ipl
!= -1 && break_ipl
== (int)(val
& 0x1f))
346 // only write least significant five bits - interrupt level
347 ipr
[idx
] = val
& 0x1f;
349 if (tc
->getKernelStats())
350 tc
->getKernelStats()->swpipl(ipr
[idx
]);
357 if (tc
->getKernelStats())
358 tc
->getKernelStats()->mode(Kernel::user
, tc
);
360 if (tc
->getKernelStats())
361 tc
->getKernelStats()->mode(Kernel::kernel
, tc
);
366 // only write two mode bits - processor mode
367 ipr
[idx
] = val
& 0x18;
371 // only write two mode bits - processor mode
372 ipr
[idx
] = val
& 0x18;
376 // more here after optimization...
381 // only write software interrupt mask
382 ipr
[idx
] = val
& 0x7fff0;
386 ipr
[idx
] = val
& ULL(0xffffff0300);
391 ipr
[idx
] = val
& ULL(0xffffffffc0000000);
394 case IPR_DC_TEST_CTL
:
395 ipr
[idx
] = val
& 0x1ffb;
400 ipr
[idx
] = val
& 0x3f;
404 ipr
[idx
] = val
& 0x7f0;
408 ipr
[idx
] = val
& ULL(0xfe00000000000000);
413 // any write to this register clears it
420 case IPR_ITB_PTE_TEMP
:
421 case IPR_DTB_PTE_TEMP
:
422 // read-only registers
423 panic("Tried to write read only ipr %d\n", idx
);
429 // the following are write only
434 // really a control write
437 tc
->getDTBPtr()->flushAll();
441 // really a control write
444 tc
->getDTBPtr()->flushProcesses();
448 // really a control write
451 tc
->getDTBPtr()->flushAddr(val
, DTB_ASN_ASN(ipr
[IPR_DTB_ASN
]));
455 struct TlbEntry entry
;
457 // FIXME: granularity hints NYI...
458 if (DTB_PTE_GH(ipr
[IPR_DTB_PTE
]) != 0)
459 panic("PTE GH field != 0");
464 // construct PTE for new entry
465 entry
.ppn
= DTB_PTE_PPN(ipr
[IPR_DTB_PTE
]);
466 entry
.xre
= DTB_PTE_XRE(ipr
[IPR_DTB_PTE
]);
467 entry
.xwe
= DTB_PTE_XWE(ipr
[IPR_DTB_PTE
]);
468 entry
.fonr
= DTB_PTE_FONR(ipr
[IPR_DTB_PTE
]);
469 entry
.fonw
= DTB_PTE_FONW(ipr
[IPR_DTB_PTE
]);
470 entry
.asma
= DTB_PTE_ASMA(ipr
[IPR_DTB_PTE
]);
471 entry
.asn
= DTB_ASN_ASN(ipr
[IPR_DTB_ASN
]);
473 // insert new TAG/PTE value into data TLB
474 tc
->getDTBPtr()->insert(val
, entry
);
479 struct TlbEntry entry
;
481 // FIXME: granularity hints NYI...
482 if (ITB_PTE_GH(val
) != 0)
483 panic("PTE GH field != 0");
488 // construct PTE for new entry
489 entry
.ppn
= ITB_PTE_PPN(val
);
490 entry
.xre
= ITB_PTE_XRE(val
);
492 entry
.fonr
= ITB_PTE_FONR(val
);
493 entry
.fonw
= ITB_PTE_FONW(val
);
494 entry
.asma
= ITB_PTE_ASMA(val
);
495 entry
.asn
= ITB_ASN_ASN(ipr
[IPR_ITB_ASN
]);
497 // insert new TAG/PTE value into data TLB
498 tc
->getITBPtr()->insert(ipr
[IPR_ITB_TAG
], entry
);
503 // really a control write
506 tc
->getITBPtr()->flushAll();
510 // really a control write
513 tc
->getITBPtr()->flushProcesses();
517 // really a control write
520 tc
->getITBPtr()->flushAddr(val
, ITB_ASN_ASN(ipr
[IPR_ITB_ASN
]));
525 panic("Tried to write to invalid ipr %d\n", idx
);
532 copyIprs(ThreadContext
*src
, ThreadContext
*dest
)
534 for (int i
= 0; i
< NumInternalProcRegs
; ++i
)
535 dest
->setMiscRegNoEffect(i
, src
->readMiscRegNoEffect(i
));
538 } // namespace AlphaISA
542 using namespace AlphaISA
;
545 SimpleThread::hwrei()
547 if (!(readPC() & 0x3))
548 return new UnimplementedOpcodeFault
;
550 setNextPC(readMiscRegNoEffect(IPR_EXC_ADDR
));
552 CPA::cpa()->swAutoBegin(tc
, readNextPC());
554 if (!misspeculating()) {
556 kernelStats
->hwrei();
559 // FIXME: XXX check for interrupts? XXX
564 * Check for special simulator handling of specific PAL calls.
565 * If return value is false, actual PAL call will be suppressed.
568 SimpleThread::simPalCheck(int palFunc
)
571 kernelStats
->callpal(palFunc
, tc
);
576 if (--System::numSystemsRunning
== 0)
577 exitSimLoop("all cpus halted");
582 if (system
->breakpoint())
590 #endif // FULL_SYSTEM