2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
32 #include "arch/alpha/tlb.hh"
33 #include "arch/alpha/isa_traits.hh"
34 #include "arch/alpha/osfpal.hh"
35 #include "base/kgdb.h"
36 #include "base/remote_gdb.hh"
37 #include "base/stats/events.hh"
38 #include "config/full_system.hh"
39 #include "cpu/base.hh"
40 #include "cpu/cpu_exec_context.hh"
41 #include "cpu/exec_context.hh"
42 #include "kern/kernel_stats.hh"
43 #include "sim/debug.hh"
44 #include "sim/sim_events.hh"
50 ////////////////////////////////////////////////////////////////////////
52 // Machine dependent functions
55 AlphaISA::initCPU(ExecContext
*xc
, int cpuId
)
59 xc
->setIntReg(16, cpuId
);
60 xc
->setIntReg(0, cpuId
);
62 xc
->setPC(xc
->readMiscReg(IPR_PAL_BASE
) + (new ResetFault
)->vect());
63 xc
->setNextPC(xc
->readPC() + sizeof(MachInst
));
66 ////////////////////////////////////////////////////////////////////////
71 AlphaISA::initIPRs(ExecContext
*xc
, int cpuId
)
73 for (int i
= 0; i
< NumInternalProcRegs
; ++i
) {
77 xc
->setMiscReg(IPR_PAL_BASE
, PalBase
);
78 xc
->setMiscReg(IPR_MCSR
, 0x6);
79 xc
->setMiscReg(IPR_PALtemp16
, cpuId
);
85 AlphaISA::processInterrupts(CPU
*cpu
)
87 //Check if there are any outstanding interrupts
88 //Handle the interrupts
92 cpu
->checkInterrupts
= false;
94 if (cpu
->readMiscReg(IPR_ASTRR
))
95 panic("asynchronous traps not implemented\n");
97 if (cpu
->readMiscReg(IPR_SIRR
)) {
98 for (int i
= INTLEVEL_SOFTWARE_MIN
;
99 i
< INTLEVEL_SOFTWARE_MAX
; i
++) {
100 if (cpu
->readMiscReg(IPR_SIRR
) & (ULL(1) << i
)) {
101 // See table 4-19 of the 21164 hardware reference
102 ipl
= (i
- INTLEVEL_SOFTWARE_MIN
) + 1;
103 summary
|= (ULL(1) << i
);
108 uint64_t interrupts
= cpu
->intr_status();
111 for (int i
= INTLEVEL_EXTERNAL_MIN
;
112 i
< INTLEVEL_EXTERNAL_MAX
; i
++) {
113 if (interrupts
& (ULL(1) << i
)) {
114 // See table 4-19 of the 21164 hardware reference
116 summary
|= (ULL(1) << i
);
121 if (ipl
&& ipl
> cpu
->readMiscReg(IPR_IPLR
)) {
122 cpu
->setMiscReg(IPR_ISR
, summary
);
123 cpu
->setMiscReg(IPR_INTID
, ipl
);
124 cpu
->trap(new InterruptFault
);
125 DPRINTF(Flow
, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
126 cpu
->readMiscReg(IPR_IPLR
), ipl
, summary
);
133 AlphaISA::zeroRegisters(CPU
*cpu
)
135 // Insure ISA semantics
136 // (no longer very clean due to the change in setIntReg() in the
137 // cpu model. Consider changing later.)
138 cpu
->cpuXC
->setIntReg(ZeroReg
, 0);
139 cpu
->cpuXC
->setFloatReg(ZeroReg
, 0.0);
143 CPUExecContext::hwrei()
146 return new UnimplementedOpcodeFault
;
148 setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR
));
150 if (!misspeculating()) {
151 cpu
->kernelStats
->hwrei();
153 cpu
->checkInterrupts
= true;
156 // FIXME: XXX check for interrupts? XXX
161 AlphaISA::MiscRegFile::getInstAsid()
163 return EV5::ITB_ASN_ASN(ipr
[IPR_ITB_ASN
]);
167 AlphaISA::MiscRegFile::getDataAsid()
169 return EV5::DTB_ASN_ASN(ipr
[IPR_DTB_ASN
]);
173 AlphaISA::MiscRegFile::readIpr(int idx
, Fault
&fault
, ExecContext
*xc
)
175 uint64_t retval
= 0; // return value, default 0
178 case AlphaISA::IPR_PALtemp0
:
179 case AlphaISA::IPR_PALtemp1
:
180 case AlphaISA::IPR_PALtemp2
:
181 case AlphaISA::IPR_PALtemp3
:
182 case AlphaISA::IPR_PALtemp4
:
183 case AlphaISA::IPR_PALtemp5
:
184 case AlphaISA::IPR_PALtemp6
:
185 case AlphaISA::IPR_PALtemp7
:
186 case AlphaISA::IPR_PALtemp8
:
187 case AlphaISA::IPR_PALtemp9
:
188 case AlphaISA::IPR_PALtemp10
:
189 case AlphaISA::IPR_PALtemp11
:
190 case AlphaISA::IPR_PALtemp12
:
191 case AlphaISA::IPR_PALtemp13
:
192 case AlphaISA::IPR_PALtemp14
:
193 case AlphaISA::IPR_PALtemp15
:
194 case AlphaISA::IPR_PALtemp16
:
195 case AlphaISA::IPR_PALtemp17
:
196 case AlphaISA::IPR_PALtemp18
:
197 case AlphaISA::IPR_PALtemp19
:
198 case AlphaISA::IPR_PALtemp20
:
199 case AlphaISA::IPR_PALtemp21
:
200 case AlphaISA::IPR_PALtemp22
:
201 case AlphaISA::IPR_PALtemp23
:
202 case AlphaISA::IPR_PAL_BASE
:
204 case AlphaISA::IPR_IVPTBR
:
205 case AlphaISA::IPR_DC_MODE
:
206 case AlphaISA::IPR_MAF_MODE
:
207 case AlphaISA::IPR_ISR
:
208 case AlphaISA::IPR_EXC_ADDR
:
209 case AlphaISA::IPR_IC_PERR_STAT
:
210 case AlphaISA::IPR_DC_PERR_STAT
:
211 case AlphaISA::IPR_MCSR
:
212 case AlphaISA::IPR_ASTRR
:
213 case AlphaISA::IPR_ASTER
:
214 case AlphaISA::IPR_SIRR
:
215 case AlphaISA::IPR_ICSR
:
216 case AlphaISA::IPR_ICM
:
217 case AlphaISA::IPR_DTB_CM
:
218 case AlphaISA::IPR_IPLR
:
219 case AlphaISA::IPR_INTID
:
220 case AlphaISA::IPR_PMCTR
:
225 case AlphaISA::IPR_CC
:
226 retval
|= ipr
[idx
] & ULL(0xffffffff00000000);
227 retval
|= xc
->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff);
230 case AlphaISA::IPR_VA
:
234 case AlphaISA::IPR_VA_FORM
:
235 case AlphaISA::IPR_MM_STAT
:
236 case AlphaISA::IPR_IFAULT_VA_FORM
:
237 case AlphaISA::IPR_EXC_MASK
:
238 case AlphaISA::IPR_EXC_SUM
:
242 case AlphaISA::IPR_DTB_PTE
:
244 AlphaISA::PTE
&pte
= xc
->getDTBPtr()->index(!xc
->misspeculating());
246 retval
|= ((u_int64_t
)pte
.ppn
& ULL(0x7ffffff)) << 32;
247 retval
|= ((u_int64_t
)pte
.xre
& ULL(0xf)) << 8;
248 retval
|= ((u_int64_t
)pte
.xwe
& ULL(0xf)) << 12;
249 retval
|= ((u_int64_t
)pte
.fonr
& ULL(0x1)) << 1;
250 retval
|= ((u_int64_t
)pte
.fonw
& ULL(0x1))<< 2;
251 retval
|= ((u_int64_t
)pte
.asma
& ULL(0x1)) << 4;
252 retval
|= ((u_int64_t
)pte
.asn
& ULL(0x7f)) << 57;
256 // write only registers
257 case AlphaISA::IPR_HWINT_CLR
:
258 case AlphaISA::IPR_SL_XMIT
:
259 case AlphaISA::IPR_DC_FLUSH
:
260 case AlphaISA::IPR_IC_FLUSH
:
261 case AlphaISA::IPR_ALT_MODE
:
262 case AlphaISA::IPR_DTB_IA
:
263 case AlphaISA::IPR_DTB_IAP
:
264 case AlphaISA::IPR_ITB_IA
:
265 case AlphaISA::IPR_ITB_IAP
:
266 fault
= new UnimplementedOpcodeFault
;
271 fault
= new UnimplementedOpcodeFault
;
279 // Cause the simulator to break when changing to the following IPL
284 AlphaISA::MiscRegFile::setIpr(int idx
, uint64_t val
, ExecContext
*xc
)
288 if (xc
->misspeculating())
292 case AlphaISA::IPR_PALtemp0
:
293 case AlphaISA::IPR_PALtemp1
:
294 case AlphaISA::IPR_PALtemp2
:
295 case AlphaISA::IPR_PALtemp3
:
296 case AlphaISA::IPR_PALtemp4
:
297 case AlphaISA::IPR_PALtemp5
:
298 case AlphaISA::IPR_PALtemp6
:
299 case AlphaISA::IPR_PALtemp7
:
300 case AlphaISA::IPR_PALtemp8
:
301 case AlphaISA::IPR_PALtemp9
:
302 case AlphaISA::IPR_PALtemp10
:
303 case AlphaISA::IPR_PALtemp11
:
304 case AlphaISA::IPR_PALtemp12
:
305 case AlphaISA::IPR_PALtemp13
:
306 case AlphaISA::IPR_PALtemp14
:
307 case AlphaISA::IPR_PALtemp15
:
308 case AlphaISA::IPR_PALtemp16
:
309 case AlphaISA::IPR_PALtemp17
:
310 case AlphaISA::IPR_PALtemp18
:
311 case AlphaISA::IPR_PALtemp19
:
312 case AlphaISA::IPR_PALtemp20
:
313 case AlphaISA::IPR_PALtemp21
:
314 case AlphaISA::IPR_PALtemp22
:
315 case AlphaISA::IPR_PAL_BASE
:
316 case AlphaISA::IPR_IC_PERR_STAT
:
317 case AlphaISA::IPR_DC_PERR_STAT
:
318 case AlphaISA::IPR_PMCTR
:
319 // write entire quad w/ no side-effect
323 case AlphaISA::IPR_CC_CTL
:
324 // This IPR resets the cycle counter. We assume this only
325 // happens once... let's verify that.
326 assert(ipr
[idx
] == 0);
330 case AlphaISA::IPR_CC
:
331 // This IPR only writes the upper 64 bits. It's ok to write
332 // all 64 here since we mask out the lower 32 in rpcc (see
337 case AlphaISA::IPR_PALtemp23
:
338 // write entire quad w/ no side-effect
341 xc
->getCpuPtr()->kernelStats
->context(old
, val
, xc
);
344 case AlphaISA::IPR_DTB_PTE
:
345 // write entire quad w/ no side-effect, tag is forthcoming
349 case AlphaISA::IPR_EXC_ADDR
:
350 // second least significant bit in PC is always zero
354 case AlphaISA::IPR_ASTRR
:
355 case AlphaISA::IPR_ASTER
:
356 // only write least significant four bits - privilege mask
357 ipr
[idx
] = val
& 0xf;
360 case AlphaISA::IPR_IPLR
:
362 if (break_ipl
!= -1 && break_ipl
== (val
& 0x1f))
366 // only write least significant five bits - interrupt level
367 ipr
[idx
] = val
& 0x1f;
368 xc
->getCpuPtr()->kernelStats
->swpipl(ipr
[idx
]);
371 case AlphaISA::IPR_DTB_CM
:
373 xc
->getCpuPtr()->kernelStats
->mode(Kernel::user
, xc
);
375 xc
->getCpuPtr()->kernelStats
->mode(Kernel::kernel
, xc
);
377 case AlphaISA::IPR_ICM
:
378 // only write two mode bits - processor mode
379 ipr
[idx
] = val
& 0x18;
382 case AlphaISA::IPR_ALT_MODE
:
383 // only write two mode bits - processor mode
384 ipr
[idx
] = val
& 0x18;
387 case AlphaISA::IPR_MCSR
:
388 // more here after optimization...
392 case AlphaISA::IPR_SIRR
:
393 // only write software interrupt mask
394 ipr
[idx
] = val
& 0x7fff0;
397 case AlphaISA::IPR_ICSR
:
398 ipr
[idx
] = val
& ULL(0xffffff0300);
401 case AlphaISA::IPR_IVPTBR
:
402 case AlphaISA::IPR_MVPTBR
:
403 ipr
[idx
] = val
& ULL(0xffffffffc0000000);
406 case AlphaISA::IPR_DC_TEST_CTL
:
407 ipr
[idx
] = val
& 0x1ffb;
410 case AlphaISA::IPR_DC_MODE
:
411 case AlphaISA::IPR_MAF_MODE
:
412 ipr
[idx
] = val
& 0x3f;
415 case AlphaISA::IPR_ITB_ASN
:
416 ipr
[idx
] = val
& 0x7f0;
419 case AlphaISA::IPR_DTB_ASN
:
420 ipr
[idx
] = val
& ULL(0xfe00000000000000);
423 case AlphaISA::IPR_EXC_SUM
:
424 case AlphaISA::IPR_EXC_MASK
:
425 // any write to this register clears it
429 case AlphaISA::IPR_INTID
:
430 case AlphaISA::IPR_SL_RCV
:
431 case AlphaISA::IPR_MM_STAT
:
432 case AlphaISA::IPR_ITB_PTE_TEMP
:
433 case AlphaISA::IPR_DTB_PTE_TEMP
:
434 // read-only registers
435 return new UnimplementedOpcodeFault
;
437 case AlphaISA::IPR_HWINT_CLR
:
438 case AlphaISA::IPR_SL_XMIT
:
439 case AlphaISA::IPR_DC_FLUSH
:
440 case AlphaISA::IPR_IC_FLUSH
:
441 // the following are write only
445 case AlphaISA::IPR_DTB_IA
:
446 // really a control write
449 xc
->getDTBPtr()->flushAll();
452 case AlphaISA::IPR_DTB_IAP
:
453 // really a control write
456 xc
->getDTBPtr()->flushProcesses();
459 case AlphaISA::IPR_DTB_IS
:
460 // really a control write
463 xc
->getDTBPtr()->flushAddr(val
,
464 DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]));
467 case AlphaISA::IPR_DTB_TAG
: {
468 struct AlphaISA::PTE pte
;
470 // FIXME: granularity hints NYI...
471 if (DTB_PTE_GH(ipr
[AlphaISA::IPR_DTB_PTE
]) != 0)
472 panic("PTE GH field != 0");
477 // construct PTE for new entry
478 pte
.ppn
= DTB_PTE_PPN(ipr
[AlphaISA::IPR_DTB_PTE
]);
479 pte
.xre
= DTB_PTE_XRE(ipr
[AlphaISA::IPR_DTB_PTE
]);
480 pte
.xwe
= DTB_PTE_XWE(ipr
[AlphaISA::IPR_DTB_PTE
]);
481 pte
.fonr
= DTB_PTE_FONR(ipr
[AlphaISA::IPR_DTB_PTE
]);
482 pte
.fonw
= DTB_PTE_FONW(ipr
[AlphaISA::IPR_DTB_PTE
]);
483 pte
.asma
= DTB_PTE_ASMA(ipr
[AlphaISA::IPR_DTB_PTE
]);
484 pte
.asn
= DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]);
486 // insert new TAG/PTE value into data TLB
487 xc
->getDTBPtr()->insert(val
, pte
);
491 case AlphaISA::IPR_ITB_PTE
: {
492 struct AlphaISA::PTE pte
;
494 // FIXME: granularity hints NYI...
495 if (ITB_PTE_GH(val
) != 0)
496 panic("PTE GH field != 0");
501 // construct PTE for new entry
502 pte
.ppn
= ITB_PTE_PPN(val
);
503 pte
.xre
= ITB_PTE_XRE(val
);
505 pte
.fonr
= ITB_PTE_FONR(val
);
506 pte
.fonw
= ITB_PTE_FONW(val
);
507 pte
.asma
= ITB_PTE_ASMA(val
);
508 pte
.asn
= ITB_ASN_ASN(ipr
[AlphaISA::IPR_ITB_ASN
]);
510 // insert new TAG/PTE value into data TLB
511 xc
->getITBPtr()->insert(ipr
[AlphaISA::IPR_ITB_TAG
], pte
);
515 case AlphaISA::IPR_ITB_IA
:
516 // really a control write
519 xc
->getITBPtr()->flushAll();
522 case AlphaISA::IPR_ITB_IAP
:
523 // really a control write
526 xc
->getITBPtr()->flushProcesses();
529 case AlphaISA::IPR_ITB_IS
:
530 // really a control write
533 xc
->getITBPtr()->flushAddr(val
,
534 ITB_ASN_ASN(ipr
[AlphaISA::IPR_ITB_ASN
]));
539 return new UnimplementedOpcodeFault
;
547 AlphaISA::copyIprs(ExecContext
*src
, ExecContext
*dest
)
549 for (int i
= IPR_Base_DepTag
; i
< NumInternalProcRegs
; ++i
) {
550 dest
->setMiscReg(i
, src
->readMiscReg(i
));
555 * Check for special simulator handling of specific PAL calls.
556 * If return value is false, actual PAL call will be suppressed.
559 CPUExecContext::simPalCheck(int palFunc
)
561 cpu
->kernelStats
->callpal(palFunc
, proxy
);
566 if (--System::numSystemsRunning
== 0)
567 new SimExitEvent("all cpus halted");
572 if (system
->breakpoint())
580 #endif // FULL_SYSTEM