src/arch/alpha/ev5.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Nathan Binkert
  30  *          Ali Saidi
  31  */
  32
  33 #ifndef __ARCH_ALPHA_EV5_HH__
  34 #define __ARCH_ALPHA_EV5_HH__
  35
  36 #include "arch/alpha/isa_traits.hh"
  37
  38 class ThreadContext;
  39
  40 namespace AlphaISA {
  41
  42 const uint64_t AsnMask = ULL(0xff);
  43 const int VAddrImplBits = 43;
  44 const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1;
  45 const Addr VAddrUnImplMask = ~VAddrImplMask;
  46 inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
  47 inline Addr VAddrVPN(Addr a) { return a >> PageShift; }
  48 inline Addr VAddrOffset(Addr a) { return a & PageOffset; }
  49 inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; }
  50 inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; }
  51
  52 inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); }
  53 const int PAddrImplBits = 44; // for Tsunami
  54 const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1;
  55 const Addr PAddrUncachedBit39 = ULL(0x8000000000);
  56 const Addr PAddrUncachedBit40 = ULL(0x10000000000);
  57 const Addr PAddrUncachedBit43 = ULL(0x80000000000);
  58 const Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35>
  59
  60 inline Addr
  61 Phys2K0Seg(Addr addr)
  62 {
  63     if (addr & PAddrUncachedBit43) {
  64         addr &= PAddrUncachedMask;
  65         addr |= PAddrUncachedBit40;
  66     }
  67     return addr | K0SegBase;
  68 }
  69
  70 inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; }
  71 inline Addr DTB_PTE_PPN(uint64_t reg)
  72 { return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); }
  73 inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
  74 inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; }
  75 inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
  76 inline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
  77 inline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
  78 inline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
  79
  80 inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; }
  81 inline Addr ITB_PTE_PPN(uint64_t reg)
  82 { return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); }
  83 inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
  84 inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
  85 inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
  86 inline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
  87 inline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
  88
  89 inline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; }
  90
  91 inline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; }
  92 inline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; }
  93 inline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; }
  94
  95 inline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; }
  96 inline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
  97 inline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
  98
  99 const uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020);
 100 const uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010);
 101 const uint64_t MM_STAT_FONW_MASK = ULL(0x0008);
 102 const uint64_t MM_STAT_FONR_MASK = ULL(0x0004);
 103 const uint64_t MM_STAT_ACV_MASK = ULL(0x0002);
 104 const uint64_t MM_STAT_WR_MASK = ULL(0x0001);
 105 inline int Opcode(MachInst inst) { return inst >> 26 & 0x3f; }
 106 inline int Ra(MachInst inst) { return inst >> 21 & 0x1f; }
 107
 108 const Addr PalBase = 0x4000;
 109 const Addr PalMax = 0x10000;
 110
 111 void copyIprs(ThreadContext *src, ThreadContext *dest);
 112
 113 } // namespace AlphaISA
 114
 115 #endif // __ARCH_ALPHA_EV5_HH__