src/arch/alpha/faults.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Kevin Lim
  30  */
  31
  32 #include "arch/alpha/ev5.hh"
  33 #include "arch/alpha/faults.hh"
  34 #include "arch/alpha/tlb.hh"
  35 #include "base/trace.hh"
  36 #include "cpu/base.hh"
  37 #include "cpu/thread_context.hh"
  38 #include "mem/page_table.hh"
  39 #include "sim/process.hh"
  40 #include "sim/full_system.hh"
  41
  42 namespace AlphaISA {
  43
  44 FaultName MachineCheckFault::_name = "mchk";
  45 FaultVect MachineCheckFault::_vect = 0x0401;
  46 FaultStat MachineCheckFault::_count;
  47
  48 FaultName AlignmentFault::_name = "unalign";
  49 FaultVect AlignmentFault::_vect = 0x0301;
  50 FaultStat AlignmentFault::_count;
  51
  52 FaultName ResetFault::_name = "reset";
  53 FaultVect ResetFault::_vect = 0x0001;
  54 FaultStat ResetFault::_count;
  55
  56 FaultName ArithmeticFault::_name = "arith";
  57 FaultVect ArithmeticFault::_vect = 0x0501;
  58 FaultStat ArithmeticFault::_count;
  59
  60 FaultName InterruptFault::_name = "interrupt";
  61 FaultVect InterruptFault::_vect = 0x0101;
  62 FaultStat InterruptFault::_count;
  63
  64 FaultName NDtbMissFault::_name = "dtb_miss_single";
  65 FaultVect NDtbMissFault::_vect = 0x0201;
  66 FaultStat NDtbMissFault::_count;
  67
  68 FaultName PDtbMissFault::_name = "dtb_miss_double";
  69 FaultVect PDtbMissFault::_vect = 0x0281;
  70 FaultStat PDtbMissFault::_count;
  71
  72 FaultName DtbPageFault::_name = "dtb_page_fault";
  73 FaultVect DtbPageFault::_vect = 0x0381;
  74 FaultStat DtbPageFault::_count;
  75
  76 FaultName DtbAcvFault::_name = "dtb_acv_fault";
  77 FaultVect DtbAcvFault::_vect = 0x0381;
  78 FaultStat DtbAcvFault::_count;
  79
  80 FaultName DtbAlignmentFault::_name = "unalign";
  81 FaultVect DtbAlignmentFault::_vect = 0x0301;
  82 FaultStat DtbAlignmentFault::_count;
  83
  84 FaultName ItbPageFault::_name = "itbmiss";
  85 FaultVect ItbPageFault::_vect = 0x0181;
  86 FaultStat ItbPageFault::_count;
  87
  88 FaultName ItbAcvFault::_name = "iaccvio";
  89 FaultVect ItbAcvFault::_vect = 0x0081;
  90 FaultStat ItbAcvFault::_count;
  91
  92 FaultName UnimplementedOpcodeFault::_name = "opdec";
  93 FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
  94 FaultStat UnimplementedOpcodeFault::_count;
  95
  96 FaultName FloatEnableFault::_name = "fen";
  97 FaultVect FloatEnableFault::_vect = 0x0581;
  98 FaultStat FloatEnableFault::_count;
  99
 100 FaultName PalFault::_name = "pal";
 101 FaultVect PalFault::_vect = 0x2001;
 102 FaultStat PalFault::_count;
 103
 104 FaultName IntegerOverflowFault::_name = "intover";
 105 FaultVect IntegerOverflowFault::_vect = 0x0501;
 106 FaultStat IntegerOverflowFault::_count;
 107
 108 void
 109 AlphaFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
 110 {
 111     FaultBase::invoke(tc);
 112     if (!FullSystem)
 113         return;
 114     countStat()++;
 115
 116     PCState pc = tc->pcState();
 117
 118     // exception restart address
 119     if (setRestartAddress() || !(pc.pc() & 0x3))
 120         tc->setMiscRegNoEffect(IPR_EXC_ADDR, pc.pc());
 121
 122     if (skipFaultingInstruction()) {
 123         // traps...  skip faulting instruction.
 124         tc->setMiscRegNoEffect(IPR_EXC_ADDR,
 125                    tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4);
 126     }
 127
 128     pc.set(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect());
 129     tc->pcState(pc);
 130 }
 131
 132 void
 133 ArithmeticFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
 134 {
 135     FaultBase::invoke(tc);
 136     if (!FullSystem)
 137         return;
 138     panic("Arithmetic traps are unimplemented!");
 139 }
 140
 141 void
 142 DtbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
 143 {
 144     if (FullSystem) {
 145         // Set fault address and flags.  Even though we're modeling an
 146         // EV5, we use the EV6 technique of not latching fault registers
 147         // on VPTE loads (instead of locking the registers until IPR_VA is
 148         // read, like the EV5).  The EV6 approach is cleaner and seems to
 149         // work with EV5 PAL code, but not the other way around.
 150         if (!tc->misspeculating() &&
 151             reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
 152             // set VA register with faulting address
 153             tc->setMiscRegNoEffect(IPR_VA, vaddr);
 154
 155             // set MM_STAT register flags
 156             MachInst machInst = inst->machInst;
 157             tc->setMiscRegNoEffect(IPR_MM_STAT,
 158                 (((Opcode(machInst) & 0x3f) << 11) |
 159                  ((Ra(machInst) & 0x1f) << 6) |
 160                  (flags & 0x3f)));
 161
 162             // set VA_FORM register with faulting formatted address
 163             tc->setMiscRegNoEffect(IPR_VA_FORM,
 164                 tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
 165         }
 166     }
 167
 168     AlphaFault::invoke(tc);
 169 }
 170
 171 void
 172 ItbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
 173 {
 174     if (FullSystem) {
 175         if (!tc->misspeculating()) {
 176             tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
 177             tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
 178                 tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
 179         }
 180     }
 181
 182     AlphaFault::invoke(tc);
 183 }
 184
 185 void
 186 ItbPageFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
 187 {
 188     if (FullSystem) {
 189         ItbFault::invoke(tc);
 190         return;
 191     }
 192
 193     Process *p = tc->getProcessPtr();
 194     TlbEntry entry;
 195     bool success = p->pTable->lookup(pc, entry);
 196     if (!success) {
 197         panic("Tried to execute unmapped address %#x.\n", pc);
 198     } else {
 199         VAddr vaddr(pc);
 200         tc->getITBPtr()->insert(vaddr.page(), entry);
 201     }
 202 }
 203
 204 void
 205 NDtbMissFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
 206 {
 207     if (FullSystem) {
 208         DtbFault::invoke(tc, inst);
 209         return;
 210     }
 211
 212     Process *p = tc->getProcessPtr();
 213     TlbEntry entry;
 214     bool success = p->pTable->lookup(vaddr, entry);
 215     if (!success) {
 216         if (p->fixupStackFault(vaddr))
 217             success = p->pTable->lookup(vaddr, entry);
 218     }
 219     if (!success) {
 220         panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
 221     } else {
 222         tc->getDTBPtr()->insert(vaddr.page(), entry);
 223     }
 224 }
 225
 226 } // namespace AlphaISA
 227