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32 #include "arch/alpha/faults.hh"
33 #include "cpu/thread_context.hh"
34 #include "cpu/base.hh"
35 #include "base/trace.hh"
37 #include "arch/alpha/ev5.hh"
43 FaultName
MachineCheckFault::_name
= "mchk";
44 FaultVect
MachineCheckFault::_vect
= 0x0401;
45 FaultStat
MachineCheckFault::_count
;
47 FaultName
AlignmentFault::_name
= "unalign";
48 FaultVect
AlignmentFault::_vect
= 0x0301;
49 FaultStat
AlignmentFault::_count
;
51 FaultName
ResetFault::_name
= "reset";
52 FaultVect
ResetFault::_vect
= 0x0001;
53 FaultStat
ResetFault::_count
;
55 FaultName
ArithmeticFault::_name
= "arith";
56 FaultVect
ArithmeticFault::_vect
= 0x0501;
57 FaultStat
ArithmeticFault::_count
;
59 FaultName
InterruptFault::_name
= "interrupt";
60 FaultVect
InterruptFault::_vect
= 0x0101;
61 FaultStat
InterruptFault::_count
;
63 FaultName
NDtbMissFault::_name
= "dtb_miss_single";
64 FaultVect
NDtbMissFault::_vect
= 0x0201;
65 FaultStat
NDtbMissFault::_count
;
67 FaultName
PDtbMissFault::_name
= "dtb_miss_double";
68 FaultVect
PDtbMissFault::_vect
= 0x0281;
69 FaultStat
PDtbMissFault::_count
;
71 FaultName
DtbPageFault::_name
= "dfault";
72 FaultVect
DtbPageFault::_vect
= 0x0381;
73 FaultStat
DtbPageFault::_count
;
75 FaultName
DtbAcvFault::_name
= "dfault";
76 FaultVect
DtbAcvFault::_vect
= 0x0381;
77 FaultStat
DtbAcvFault::_count
;
79 FaultName
DtbAlignmentFault::_name
= "unalign";
80 FaultVect
DtbAlignmentFault::_vect
= 0x0301;
81 FaultStat
DtbAlignmentFault::_count
;
83 FaultName
ItbMissFault::_name
= "itbmiss";
84 FaultVect
ItbMissFault::_vect
= 0x0181;
85 FaultStat
ItbMissFault::_count
;
87 FaultName
ItbPageFault::_name
= "itbmiss";
88 FaultVect
ItbPageFault::_vect
= 0x0181;
89 FaultStat
ItbPageFault::_count
;
91 FaultName
ItbAcvFault::_name
= "iaccvio";
92 FaultVect
ItbAcvFault::_vect
= 0x0081;
93 FaultStat
ItbAcvFault::_count
;
95 FaultName
UnimplementedOpcodeFault::_name
= "opdec";
96 FaultVect
UnimplementedOpcodeFault::_vect
= 0x0481;
97 FaultStat
UnimplementedOpcodeFault::_count
;
99 FaultName
FloatEnableFault::_name
= "fen";
100 FaultVect
FloatEnableFault::_vect
= 0x0581;
101 FaultStat
FloatEnableFault::_count
;
103 FaultName
PalFault::_name
= "pal";
104 FaultVect
PalFault::_vect
= 0x2001;
105 FaultStat
PalFault::_count
;
107 FaultName
IntegerOverflowFault::_name
= "intover";
108 FaultVect
IntegerOverflowFault::_vect
= 0x0501;
109 FaultStat
IntegerOverflowFault::_count
;
113 void AlphaFault::invoke(ThreadContext
* tc
)
115 FaultBase::invoke(tc
);
118 // exception restart address
119 if (setRestartAddress() || !tc
->inPalMode())
120 tc
->setMiscReg(AlphaISA::IPR_EXC_ADDR
, tc
->readPC());
122 if (skipFaultingInstruction()) {
123 // traps... skip faulting instruction.
124 tc
->setMiscReg(AlphaISA::IPR_EXC_ADDR
,
125 tc
->readMiscReg(AlphaISA::IPR_EXC_ADDR
) + 4);
128 tc
->setPC(tc
->readMiscReg(AlphaISA::IPR_PAL_BASE
) + vect());
129 tc
->setNextPC(tc
->readPC() + sizeof(MachInst
));
132 void ArithmeticFault::invoke(ThreadContext
* tc
)
134 FaultBase::invoke(tc
);
135 panic("Arithmetic traps are unimplemented!");
138 void DtbFault::invoke(ThreadContext
* tc
)
140 // Set fault address and flags. Even though we're modeling an
141 // EV5, we use the EV6 technique of not latching fault registers
142 // on VPTE loads (instead of locking the registers until IPR_VA is
143 // read, like the EV5). The EV6 approach is cleaner and seems to
144 // work with EV5 PAL code, but not the other way around.
145 if (!tc
->misspeculating()
146 && !(reqFlags
& VPTE
) && !(reqFlags
& NO_FAULT
)) {
147 // set VA register with faulting address
148 tc
->setMiscReg(AlphaISA::IPR_VA
, vaddr
);
150 // set MM_STAT register flags
151 tc
->setMiscReg(AlphaISA::IPR_MM_STAT
,
152 (((EV5::Opcode(tc
->getInst()) & 0x3f) << 11)
153 | ((EV5::Ra(tc
->getInst()) & 0x1f) << 6)
156 // set VA_FORM register with faulting formatted address
157 tc
->setMiscReg(AlphaISA::IPR_VA_FORM
,
158 tc
->readMiscReg(AlphaISA::IPR_MVPTBR
) | (vaddr
.vpn() << 3));
161 AlphaFault::invoke(tc
);
164 void ItbFault::invoke(ThreadContext
* tc
)
166 if (!tc
->misspeculating()) {
167 tc
->setMiscReg(AlphaISA::IPR_ITB_TAG
, pc
);
168 tc
->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM
,
169 tc
->readMiscReg(AlphaISA::IPR_IVPTBR
) |
170 (AlphaISA::VAddr(pc
).vpn() << 3));
173 AlphaFault::invoke(tc
);
178 } // namespace AlphaISA