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32 #include "arch/alpha/ev5.hh"
33 #include "arch/alpha/faults.hh"
34 #include "arch/alpha/tlb.hh"
35 #include "cpu/thread_context.hh"
36 #include "cpu/base.hh"
37 #include "base/trace.hh"
40 #include "sim/process.hh"
41 #include "mem/page_table.hh"
46 FaultName
MachineCheckFault::_name
= "mchk";
47 FaultVect
MachineCheckFault::_vect
= 0x0401;
48 FaultStat
MachineCheckFault::_count
;
50 FaultName
AlignmentFault::_name
= "unalign";
51 FaultVect
AlignmentFault::_vect
= 0x0301;
52 FaultStat
AlignmentFault::_count
;
54 FaultName
ResetFault::_name
= "reset";
55 FaultVect
ResetFault::_vect
= 0x0001;
56 FaultStat
ResetFault::_count
;
58 FaultName
ArithmeticFault::_name
= "arith";
59 FaultVect
ArithmeticFault::_vect
= 0x0501;
60 FaultStat
ArithmeticFault::_count
;
62 FaultName
InterruptFault::_name
= "interrupt";
63 FaultVect
InterruptFault::_vect
= 0x0101;
64 FaultStat
InterruptFault::_count
;
66 FaultName
NDtbMissFault::_name
= "dtb_miss_single";
67 FaultVect
NDtbMissFault::_vect
= 0x0201;
68 FaultStat
NDtbMissFault::_count
;
70 FaultName
PDtbMissFault::_name
= "dtb_miss_double";
71 FaultVect
PDtbMissFault::_vect
= 0x0281;
72 FaultStat
PDtbMissFault::_count
;
74 FaultName
DtbPageFault::_name
= "dfault";
75 FaultVect
DtbPageFault::_vect
= 0x0381;
76 FaultStat
DtbPageFault::_count
;
78 FaultName
DtbAcvFault::_name
= "dfault";
79 FaultVect
DtbAcvFault::_vect
= 0x0381;
80 FaultStat
DtbAcvFault::_count
;
82 FaultName
DtbAlignmentFault::_name
= "unalign";
83 FaultVect
DtbAlignmentFault::_vect
= 0x0301;
84 FaultStat
DtbAlignmentFault::_count
;
86 FaultName
ItbPageFault::_name
= "itbmiss";
87 FaultVect
ItbPageFault::_vect
= 0x0181;
88 FaultStat
ItbPageFault::_count
;
90 FaultName
ItbAcvFault::_name
= "iaccvio";
91 FaultVect
ItbAcvFault::_vect
= 0x0081;
92 FaultStat
ItbAcvFault::_count
;
94 FaultName
UnimplementedOpcodeFault::_name
= "opdec";
95 FaultVect
UnimplementedOpcodeFault::_vect
= 0x0481;
96 FaultStat
UnimplementedOpcodeFault::_count
;
98 FaultName
FloatEnableFault::_name
= "fen";
99 FaultVect
FloatEnableFault::_vect
= 0x0581;
100 FaultStat
FloatEnableFault::_count
;
102 FaultName
PalFault::_name
= "pal";
103 FaultVect
PalFault::_vect
= 0x2001;
104 FaultStat
PalFault::_count
;
106 FaultName
IntegerOverflowFault::_name
= "intover";
107 FaultVect
IntegerOverflowFault::_vect
= 0x0501;
108 FaultStat
IntegerOverflowFault::_count
;
113 AlphaFault::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
115 FaultBase::invoke(tc
);
118 // exception restart address
119 if (setRestartAddress() || !(tc
->readPC() & 0x3))
120 tc
->setMiscRegNoEffect(IPR_EXC_ADDR
, tc
->readPC());
122 if (skipFaultingInstruction()) {
123 // traps... skip faulting instruction.
124 tc
->setMiscRegNoEffect(IPR_EXC_ADDR
,
125 tc
->readMiscRegNoEffect(IPR_EXC_ADDR
) + 4);
128 tc
->setPC(tc
->readMiscRegNoEffect(IPR_PAL_BASE
) + vect());
129 tc
->setNextPC(tc
->readPC() + sizeof(MachInst
));
133 ArithmeticFault::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
135 FaultBase::invoke(tc
);
136 panic("Arithmetic traps are unimplemented!");
140 DtbFault::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
142 // Set fault address and flags. Even though we're modeling an
143 // EV5, we use the EV6 technique of not latching fault registers
144 // on VPTE loads (instead of locking the registers until IPR_VA is
145 // read, like the EV5). The EV6 approach is cleaner and seems to
146 // work with EV5 PAL code, but not the other way around.
147 if (!tc
->misspeculating() &&
148 reqFlags
.noneSet(Request::VPTE
| Request::PREFETCH
)) {
149 // set VA register with faulting address
150 tc
->setMiscRegNoEffect(IPR_VA
, vaddr
);
152 // set MM_STAT register flags
153 MachInst machInst
= inst
->machInst
;
154 tc
->setMiscRegNoEffect(IPR_MM_STAT
,
155 (((Opcode(machInst
) & 0x3f) << 11) |
156 ((Ra(machInst
) & 0x1f) << 6) |
159 // set VA_FORM register with faulting formatted address
160 tc
->setMiscRegNoEffect(IPR_VA_FORM
,
161 tc
->readMiscRegNoEffect(IPR_MVPTBR
) | (vaddr
.vpn() << 3));
164 AlphaFault::invoke(tc
);
168 ItbFault::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
170 if (!tc
->misspeculating()) {
171 tc
->setMiscRegNoEffect(IPR_ITB_TAG
, pc
);
172 tc
->setMiscRegNoEffect(IPR_IFAULT_VA_FORM
,
173 tc
->readMiscRegNoEffect(IPR_IVPTBR
) | (VAddr(pc
).vpn() << 3));
176 AlphaFault::invoke(tc
);
182 ItbPageFault::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
184 Process
*p
= tc
->getProcessPtr();
186 bool success
= p
->pTable
->lookup(pc
, entry
);
188 panic("Tried to execute unmapped address %#x.\n", pc
);
191 tc
->getITBPtr()->insert(vaddr
.page(), entry
);
196 NDtbMissFault::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
198 Process
*p
= tc
->getProcessPtr();
200 bool success
= p
->pTable
->lookup(vaddr
, entry
);
202 p
->checkAndAllocNextPage(vaddr
);
203 success
= p
->pTable
->lookup(vaddr
, entry
);
206 panic("Tried to access unmapped address %#x.\n", (Addr
)vaddr
);
208 tc
->getDTBPtr()->insert(vaddr
.page(), entry
);
214 } // namespace AlphaISA