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32 #include "arch/alpha/ev5.hh"
33 #include "arch/alpha/faults.hh"
34 #include "arch/alpha/tlb.hh"
35 #include "cpu/thread_context.hh"
36 #include "cpu/base.hh"
37 #include "base/trace.hh"
39 #include "sim/process.hh"
40 #include "mem/page_table.hh"
45 FaultName
MachineCheckFault::_name
= "mchk";
46 FaultVect
MachineCheckFault::_vect
= 0x0401;
47 FaultStat
MachineCheckFault::_count
;
49 FaultName
AlignmentFault::_name
= "unalign";
50 FaultVect
AlignmentFault::_vect
= 0x0301;
51 FaultStat
AlignmentFault::_count
;
53 FaultName
ResetFault::_name
= "reset";
54 FaultVect
ResetFault::_vect
= 0x0001;
55 FaultStat
ResetFault::_count
;
57 FaultName
ArithmeticFault::_name
= "arith";
58 FaultVect
ArithmeticFault::_vect
= 0x0501;
59 FaultStat
ArithmeticFault::_count
;
61 FaultName
InterruptFault::_name
= "interrupt";
62 FaultVect
InterruptFault::_vect
= 0x0101;
63 FaultStat
InterruptFault::_count
;
65 FaultName
NDtbMissFault::_name
= "dtb_miss_single";
66 FaultVect
NDtbMissFault::_vect
= 0x0201;
67 FaultStat
NDtbMissFault::_count
;
69 FaultName
PDtbMissFault::_name
= "dtb_miss_double";
70 FaultVect
PDtbMissFault::_vect
= 0x0281;
71 FaultStat
PDtbMissFault::_count
;
73 FaultName
DtbPageFault::_name
= "dfault";
74 FaultVect
DtbPageFault::_vect
= 0x0381;
75 FaultStat
DtbPageFault::_count
;
77 FaultName
DtbAcvFault::_name
= "dfault";
78 FaultVect
DtbAcvFault::_vect
= 0x0381;
79 FaultStat
DtbAcvFault::_count
;
81 FaultName
DtbAlignmentFault::_name
= "unalign";
82 FaultVect
DtbAlignmentFault::_vect
= 0x0301;
83 FaultStat
DtbAlignmentFault::_count
;
85 FaultName
ItbPageFault::_name
= "itbmiss";
86 FaultVect
ItbPageFault::_vect
= 0x0181;
87 FaultStat
ItbPageFault::_count
;
89 FaultName
ItbAcvFault::_name
= "iaccvio";
90 FaultVect
ItbAcvFault::_vect
= 0x0081;
91 FaultStat
ItbAcvFault::_count
;
93 FaultName
UnimplementedOpcodeFault::_name
= "opdec";
94 FaultVect
UnimplementedOpcodeFault::_vect
= 0x0481;
95 FaultStat
UnimplementedOpcodeFault::_count
;
97 FaultName
FloatEnableFault::_name
= "fen";
98 FaultVect
FloatEnableFault::_vect
= 0x0581;
99 FaultStat
FloatEnableFault::_count
;
101 FaultName
PalFault::_name
= "pal";
102 FaultVect
PalFault::_vect
= 0x2001;
103 FaultStat
PalFault::_count
;
105 FaultName
IntegerOverflowFault::_name
= "intover";
106 FaultVect
IntegerOverflowFault::_vect
= 0x0501;
107 FaultStat
IntegerOverflowFault::_count
;
112 AlphaFault::invoke(ThreadContext
*tc
)
114 FaultBase::invoke(tc
);
117 // exception restart address
118 if (setRestartAddress() || !(tc
->readPC() & 0x3))
119 tc
->setMiscRegNoEffect(IPR_EXC_ADDR
, tc
->readPC());
121 if (skipFaultingInstruction()) {
122 // traps... skip faulting instruction.
123 tc
->setMiscRegNoEffect(IPR_EXC_ADDR
,
124 tc
->readMiscRegNoEffect(IPR_EXC_ADDR
) + 4);
127 tc
->setPC(tc
->readMiscRegNoEffect(IPR_PAL_BASE
) + vect());
128 tc
->setNextPC(tc
->readPC() + sizeof(MachInst
));
132 ArithmeticFault::invoke(ThreadContext
*tc
)
134 FaultBase::invoke(tc
);
135 panic("Arithmetic traps are unimplemented!");
139 DtbFault::invoke(ThreadContext
*tc
)
141 // Set fault address and flags. Even though we're modeling an
142 // EV5, we use the EV6 technique of not latching fault registers
143 // on VPTE loads (instead of locking the registers until IPR_VA is
144 // read, like the EV5). The EV6 approach is cleaner and seems to
145 // work with EV5 PAL code, but not the other way around.
146 if (!tc
->misspeculating() &&
147 reqFlags
.noneSet(Request::VPTE
|Request::NO_FAULT
)) {
148 // set VA register with faulting address
149 tc
->setMiscRegNoEffect(IPR_VA
, vaddr
);
151 // set MM_STAT register flags
152 tc
->setMiscRegNoEffect(IPR_MM_STAT
,
153 (((Opcode(tc
->getInst()) & 0x3f) << 11) |
154 ((Ra(tc
->getInst()) & 0x1f) << 6) |
157 // set VA_FORM register with faulting formatted address
158 tc
->setMiscRegNoEffect(IPR_VA_FORM
,
159 tc
->readMiscRegNoEffect(IPR_MVPTBR
) | (vaddr
.vpn() << 3));
162 AlphaFault::invoke(tc
);
166 ItbFault::invoke(ThreadContext
*tc
)
168 if (!tc
->misspeculating()) {
169 tc
->setMiscRegNoEffect(IPR_ITB_TAG
, pc
);
170 tc
->setMiscRegNoEffect(IPR_IFAULT_VA_FORM
,
171 tc
->readMiscRegNoEffect(IPR_IVPTBR
) | (VAddr(pc
).vpn() << 3));
174 AlphaFault::invoke(tc
);
180 ItbPageFault::invoke(ThreadContext
*tc
)
182 Process
*p
= tc
->getProcessPtr();
184 bool success
= p
->pTable
->lookup(pc
, entry
);
186 panic("Tried to execute unmapped address %#x.\n", pc
);
189 tc
->getITBPtr()->insert(vaddr
.page(), entry
);
194 NDtbMissFault::invoke(ThreadContext
*tc
)
196 Process
*p
= tc
->getProcessPtr();
198 bool success
= p
->pTable
->lookup(vaddr
, entry
);
200 p
->checkAndAllocNextPage(vaddr
);
201 success
= p
->pTable
->lookup(vaddr
, entry
);
204 panic("Tried to access unmapped address %#x.\n", (Addr
)vaddr
);
206 tc
->getDTBPtr()->insert(vaddr
.page(), entry
);
212 } // namespace AlphaISA