src/arch/alpha/faults.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Kevin Lim
  30  */
  31
  32 #include "arch/alpha/ev5.hh"
  33 #include "arch/alpha/faults.hh"
  34 #include "arch/alpha/tlb.hh"
  35 #include "cpu/thread_context.hh"
  36 #include "cpu/base.hh"
  37 #include "base/trace.hh"
  38 #if !FULL_SYSTEM
  39 #include "sim/process.hh"
  40 #include "mem/page_table.hh"
  41 #endif
  42
  43 namespace AlphaISA {
  44
  45 FaultName MachineCheckFault::_name = "mchk";
  46 FaultVect MachineCheckFault::_vect = 0x0401;
  47 FaultStat MachineCheckFault::_count;
  48
  49 FaultName AlignmentFault::_name = "unalign";
  50 FaultVect AlignmentFault::_vect = 0x0301;
  51 FaultStat AlignmentFault::_count;
  52
  53 FaultName ResetFault::_name = "reset";
  54 FaultVect ResetFault::_vect = 0x0001;
  55 FaultStat ResetFault::_count;
  56
  57 FaultName ArithmeticFault::_name = "arith";
  58 FaultVect ArithmeticFault::_vect = 0x0501;
  59 FaultStat ArithmeticFault::_count;
  60
  61 FaultName InterruptFault::_name = "interrupt";
  62 FaultVect InterruptFault::_vect = 0x0101;
  63 FaultStat InterruptFault::_count;
  64
  65 FaultName NDtbMissFault::_name = "dtb_miss_single";
  66 FaultVect NDtbMissFault::_vect = 0x0201;
  67 FaultStat NDtbMissFault::_count;
  68
  69 FaultName PDtbMissFault::_name = "dtb_miss_double";
  70 FaultVect PDtbMissFault::_vect = 0x0281;
  71 FaultStat PDtbMissFault::_count;
  72
  73 FaultName DtbPageFault::_name = "dfault";
  74 FaultVect DtbPageFault::_vect = 0x0381;
  75 FaultStat DtbPageFault::_count;
  76
  77 FaultName DtbAcvFault::_name = "dfault";
  78 FaultVect DtbAcvFault::_vect = 0x0381;
  79 FaultStat DtbAcvFault::_count;
  80
  81 FaultName DtbAlignmentFault::_name = "unalign";
  82 FaultVect DtbAlignmentFault::_vect = 0x0301;
  83 FaultStat DtbAlignmentFault::_count;
  84
  85 FaultName ItbPageFault::_name = "itbmiss";
  86 FaultVect ItbPageFault::_vect = 0x0181;
  87 FaultStat ItbPageFault::_count;
  88
  89 FaultName ItbAcvFault::_name = "iaccvio";
  90 FaultVect ItbAcvFault::_vect = 0x0081;
  91 FaultStat ItbAcvFault::_count;
  92
  93 FaultName UnimplementedOpcodeFault::_name = "opdec";
  94 FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
  95 FaultStat UnimplementedOpcodeFault::_count;
  96
  97 FaultName FloatEnableFault::_name = "fen";
  98 FaultVect FloatEnableFault::_vect = 0x0581;
  99 FaultStat FloatEnableFault::_count;
 100
 101 FaultName PalFault::_name = "pal";
 102 FaultVect PalFault::_vect = 0x2001;
 103 FaultStat PalFault::_count;
 104
 105 FaultName IntegerOverflowFault::_name = "intover";
 106 FaultVect IntegerOverflowFault::_vect = 0x0501;
 107 FaultStat IntegerOverflowFault::_count;
 108
 109 #if FULL_SYSTEM
 110
 111 void
 112 AlphaFault::invoke(ThreadContext *tc)
 113 {
 114     FaultBase::invoke(tc);
 115     countStat()++;
 116
 117     // exception restart address
 118     if (setRestartAddress() || !(tc->readPC() & 0x3))
 119         tc->setMiscRegNoEffect(IPR_EXC_ADDR, tc->readPC());
 120
 121     if (skipFaultingInstruction()) {
 122         // traps...  skip faulting instruction.
 123         tc->setMiscRegNoEffect(IPR_EXC_ADDR,
 124                    tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4);
 125     }
 126
 127     tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect());
 128     tc->setNextPC(tc->readPC() + sizeof(MachInst));
 129 }
 130
 131 void
 132 ArithmeticFault::invoke(ThreadContext *tc)
 133 {
 134     FaultBase::invoke(tc);
 135     panic("Arithmetic traps are unimplemented!");
 136 }
 137
 138 void
 139 DtbFault::invoke(ThreadContext *tc)
 140 {
 141     // Set fault address and flags.  Even though we're modeling an
 142     // EV5, we use the EV6 technique of not latching fault registers
 143     // on VPTE loads (instead of locking the registers until IPR_VA is
 144     // read, like the EV5).  The EV6 approach is cleaner and seems to
 145     // work with EV5 PAL code, but not the other way around.
 146     if (!tc->misspeculating() &&
 147         reqFlags.noneSet(Request::VPTE|Request::NO_FAULT)) {
 148         // set VA register with faulting address
 149         tc->setMiscRegNoEffect(IPR_VA, vaddr);
 150
 151         // set MM_STAT register flags
 152         tc->setMiscRegNoEffect(IPR_MM_STAT,
 153             (((Opcode(tc->getInst()) & 0x3f) << 11) |
 154              ((Ra(tc->getInst()) & 0x1f) << 6) |
 155              (flags & 0x3f)));
 156
 157         // set VA_FORM register with faulting formatted address
 158         tc->setMiscRegNoEffect(IPR_VA_FORM,
 159             tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
 160     }
 161
 162     AlphaFault::invoke(tc);
 163 }
 164
 165 void
 166 ItbFault::invoke(ThreadContext *tc)
 167 {
 168     if (!tc->misspeculating()) {
 169         tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
 170         tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
 171             tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
 172     }
 173
 174     AlphaFault::invoke(tc);
 175 }
 176
 177 #else
 178
 179 void
 180 ItbPageFault::invoke(ThreadContext *tc)
 181 {
 182     Process *p = tc->getProcessPtr();
 183     TlbEntry entry;
 184     bool success = p->pTable->lookup(pc, entry);
 185     if (!success) {
 186         panic("Tried to execute unmapped address %#x.\n", pc);
 187     } else {
 188         VAddr vaddr(pc);
 189         tc->getITBPtr()->insert(vaddr.page(), entry);
 190     }
 191 }
 192
 193 void
 194 NDtbMissFault::invoke(ThreadContext *tc)
 195 {
 196     Process *p = tc->getProcessPtr();
 197     TlbEntry entry;
 198     bool success = p->pTable->lookup(vaddr, entry);
 199     if (!success) {
 200         p->checkAndAllocNextPage(vaddr);
 201         success = p->pTable->lookup(vaddr, entry);
 202     }
 203     if (!success) {
 204         panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
 205     } else {
 206         tc->getDTBPtr()->insert(vaddr.page(), entry);
 207     }
 208 }
 209
 210 #endif
 211
 212 } // namespace AlphaISA
 213