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32 #include "arch/alpha/faults.hh"
33 #include "cpu/thread_context.hh"
34 #include "cpu/base.hh"
35 #include "base/trace.hh"
37 #include "arch/alpha/ev5.hh"
39 #include "sim/process.hh"
40 #include "mem/page_table.hh"
46 FaultName
MachineCheckFault::_name
= "mchk";
47 FaultVect
MachineCheckFault::_vect
= 0x0401;
48 FaultStat
MachineCheckFault::_count
;
50 FaultName
AlignmentFault::_name
= "unalign";
51 FaultVect
AlignmentFault::_vect
= 0x0301;
52 FaultStat
AlignmentFault::_count
;
54 FaultName
ResetFault::_name
= "reset";
55 FaultVect
ResetFault::_vect
= 0x0001;
56 FaultStat
ResetFault::_count
;
58 FaultName
ArithmeticFault::_name
= "arith";
59 FaultVect
ArithmeticFault::_vect
= 0x0501;
60 FaultStat
ArithmeticFault::_count
;
62 FaultName
InterruptFault::_name
= "interrupt";
63 FaultVect
InterruptFault::_vect
= 0x0101;
64 FaultStat
InterruptFault::_count
;
66 FaultName
NDtbMissFault::_name
= "dtb_miss_single";
67 FaultVect
NDtbMissFault::_vect
= 0x0201;
68 FaultStat
NDtbMissFault::_count
;
70 FaultName
PDtbMissFault::_name
= "dtb_miss_double";
71 FaultVect
PDtbMissFault::_vect
= 0x0281;
72 FaultStat
PDtbMissFault::_count
;
74 FaultName
DtbPageFault::_name
= "dfault";
75 FaultVect
DtbPageFault::_vect
= 0x0381;
76 FaultStat
DtbPageFault::_count
;
78 FaultName
DtbAcvFault::_name
= "dfault";
79 FaultVect
DtbAcvFault::_vect
= 0x0381;
80 FaultStat
DtbAcvFault::_count
;
82 FaultName
DtbAlignmentFault::_name
= "unalign";
83 FaultVect
DtbAlignmentFault::_vect
= 0x0301;
84 FaultStat
DtbAlignmentFault::_count
;
86 FaultName
ItbMissFault::_name
= "itbmiss";
87 FaultVect
ItbMissFault::_vect
= 0x0181;
88 FaultStat
ItbMissFault::_count
;
90 FaultName
ItbPageFault::_name
= "itbmiss";
91 FaultVect
ItbPageFault::_vect
= 0x0181;
92 FaultStat
ItbPageFault::_count
;
94 FaultName
ItbAcvFault::_name
= "iaccvio";
95 FaultVect
ItbAcvFault::_vect
= 0x0081;
96 FaultStat
ItbAcvFault::_count
;
98 FaultName
UnimplementedOpcodeFault::_name
= "opdec";
99 FaultVect
UnimplementedOpcodeFault::_vect
= 0x0481;
100 FaultStat
UnimplementedOpcodeFault::_count
;
102 FaultName
FloatEnableFault::_name
= "fen";
103 FaultVect
FloatEnableFault::_vect
= 0x0581;
104 FaultStat
FloatEnableFault::_count
;
106 FaultName
PalFault::_name
= "pal";
107 FaultVect
PalFault::_vect
= 0x2001;
108 FaultStat
PalFault::_count
;
110 FaultName
IntegerOverflowFault::_name
= "intover";
111 FaultVect
IntegerOverflowFault::_vect
= 0x0501;
112 FaultStat
IntegerOverflowFault::_count
;
116 void AlphaFault::invoke(ThreadContext
* tc
)
118 FaultBase::invoke(tc
);
121 // exception restart address
122 if (setRestartAddress() || !(tc
->readPC() & 0x3))
123 tc
->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR
, tc
->readPC());
125 if (skipFaultingInstruction()) {
126 // traps... skip faulting instruction.
127 tc
->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR
,
128 tc
->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR
) + 4);
131 tc
->setPC(tc
->readMiscRegNoEffect(AlphaISA::IPR_PAL_BASE
) + vect());
132 tc
->setNextPC(tc
->readPC() + sizeof(MachInst
));
135 void ArithmeticFault::invoke(ThreadContext
* tc
)
137 FaultBase::invoke(tc
);
138 panic("Arithmetic traps are unimplemented!");
141 void DtbFault::invoke(ThreadContext
* tc
)
143 // Set fault address and flags. Even though we're modeling an
144 // EV5, we use the EV6 technique of not latching fault registers
145 // on VPTE loads (instead of locking the registers until IPR_VA is
146 // read, like the EV5). The EV6 approach is cleaner and seems to
147 // work with EV5 PAL code, but not the other way around.
148 if (!tc
->misspeculating()
149 && !(reqFlags
& VPTE
) && !(reqFlags
& NO_FAULT
)) {
150 // set VA register with faulting address
151 tc
->setMiscRegNoEffect(AlphaISA::IPR_VA
, vaddr
);
153 // set MM_STAT register flags
154 tc
->setMiscRegNoEffect(AlphaISA::IPR_MM_STAT
,
155 (((EV5::Opcode(tc
->getInst()) & 0x3f) << 11)
156 | ((EV5::Ra(tc
->getInst()) & 0x1f) << 6)
159 // set VA_FORM register with faulting formatted address
160 tc
->setMiscRegNoEffect(AlphaISA::IPR_VA_FORM
,
161 tc
->readMiscRegNoEffect(AlphaISA::IPR_MVPTBR
) | (vaddr
.vpn() << 3));
164 AlphaFault::invoke(tc
);
167 void ItbFault::invoke(ThreadContext
* tc
)
169 if (!tc
->misspeculating()) {
170 tc
->setMiscRegNoEffect(AlphaISA::IPR_ITB_TAG
, pc
);
171 tc
->setMiscRegNoEffect(AlphaISA::IPR_IFAULT_VA_FORM
,
172 tc
->readMiscRegNoEffect(AlphaISA::IPR_IVPTBR
) |
173 (AlphaISA::VAddr(pc
).vpn() << 3));
176 AlphaFault::invoke(tc
);
181 } // namespace AlphaISA