src/arch/alpha/faults.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Kevin Lim
  30  */
  31
  32 #include "arch/alpha/ev5.hh"
  33 #include "arch/alpha/faults.hh"
  34 #include "arch/alpha/tlb.hh"
  35 #include "cpu/thread_context.hh"
  36 #include "cpu/base.hh"
  37 #include "base/trace.hh"
  38 #if !FULL_SYSTEM
  39 #include "sim/process.hh"
  40 #include "mem/page_table.hh"
  41 #endif
  42
  43 namespace AlphaISA
  44 {
  45
  46 FaultName MachineCheckFault::_name = "mchk";
  47 FaultVect MachineCheckFault::_vect = 0x0401;
  48 FaultStat MachineCheckFault::_count;
  49
  50 FaultName AlignmentFault::_name = "unalign";
  51 FaultVect AlignmentFault::_vect = 0x0301;
  52 FaultStat AlignmentFault::_count;
  53
  54 FaultName ResetFault::_name = "reset";
  55 FaultVect ResetFault::_vect = 0x0001;
  56 FaultStat ResetFault::_count;
  57
  58 FaultName ArithmeticFault::_name = "arith";
  59 FaultVect ArithmeticFault::_vect = 0x0501;
  60 FaultStat ArithmeticFault::_count;
  61
  62 FaultName InterruptFault::_name = "interrupt";
  63 FaultVect InterruptFault::_vect = 0x0101;
  64 FaultStat InterruptFault::_count;
  65
  66 FaultName NDtbMissFault::_name = "dtb_miss_single";
  67 FaultVect NDtbMissFault::_vect = 0x0201;
  68 FaultStat NDtbMissFault::_count;
  69
  70 FaultName PDtbMissFault::_name = "dtb_miss_double";
  71 FaultVect PDtbMissFault::_vect = 0x0281;
  72 FaultStat PDtbMissFault::_count;
  73
  74 FaultName DtbPageFault::_name = "dfault";
  75 FaultVect DtbPageFault::_vect = 0x0381;
  76 FaultStat DtbPageFault::_count;
  77
  78 FaultName DtbAcvFault::_name = "dfault";
  79 FaultVect DtbAcvFault::_vect = 0x0381;
  80 FaultStat DtbAcvFault::_count;
  81
  82 FaultName DtbAlignmentFault::_name = "unalign";
  83 FaultVect DtbAlignmentFault::_vect = 0x0301;
  84 FaultStat DtbAlignmentFault::_count;
  85
  86 FaultName ItbPageFault::_name = "itbmiss";
  87 FaultVect ItbPageFault::_vect = 0x0181;
  88 FaultStat ItbPageFault::_count;
  89
  90 FaultName ItbAcvFault::_name = "iaccvio";
  91 FaultVect ItbAcvFault::_vect = 0x0081;
  92 FaultStat ItbAcvFault::_count;
  93
  94 FaultName UnimplementedOpcodeFault::_name = "opdec";
  95 FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
  96 FaultStat UnimplementedOpcodeFault::_count;
  97
  98 FaultName FloatEnableFault::_name = "fen";
  99 FaultVect FloatEnableFault::_vect = 0x0581;
 100 FaultStat FloatEnableFault::_count;
 101
 102 FaultName PalFault::_name = "pal";
 103 FaultVect PalFault::_vect = 0x2001;
 104 FaultStat PalFault::_count;
 105
 106 FaultName IntegerOverflowFault::_name = "intover";
 107 FaultVect IntegerOverflowFault::_vect = 0x0501;
 108 FaultStat IntegerOverflowFault::_count;
 109
 110 #if FULL_SYSTEM
 111
 112 void AlphaFault::invoke(ThreadContext * tc)
 113 {
 114     FaultBase::invoke(tc);
 115     countStat()++;
 116
 117     // exception restart address
 118     if (setRestartAddress() || !(tc->readPC() & 0x3))
 119         tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, tc->readPC());
 120
 121     if (skipFaultingInstruction()) {
 122         // traps...  skip faulting instruction.
 123         tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
 124                    tc->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR) + 4);
 125     }
 126
 127     tc->setPC(tc->readMiscRegNoEffect(AlphaISA::IPR_PAL_BASE) + vect());
 128     tc->setNextPC(tc->readPC() + sizeof(MachInst));
 129 }
 130
 131 void ArithmeticFault::invoke(ThreadContext * tc)
 132 {
 133     FaultBase::invoke(tc);
 134     panic("Arithmetic traps are unimplemented!");
 135 }
 136
 137 void DtbFault::invoke(ThreadContext * tc)
 138 {
 139     // Set fault address and flags.  Even though we're modeling an
 140     // EV5, we use the EV6 technique of not latching fault registers
 141     // on VPTE loads (instead of locking the registers until IPR_VA is
 142     // read, like the EV5).  The EV6 approach is cleaner and seems to
 143     // work with EV5 PAL code, but not the other way around.
 144     if (!tc->misspeculating()
 145         && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
 146         // set VA register with faulting address
 147         tc->setMiscRegNoEffect(AlphaISA::IPR_VA, vaddr);
 148
 149         // set MM_STAT register flags
 150         tc->setMiscRegNoEffect(AlphaISA::IPR_MM_STAT,
 151             (((EV5::Opcode(tc->getInst()) & 0x3f) << 11)
 152              | ((EV5::Ra(tc->getInst()) & 0x1f) << 6)
 153              | (flags & 0x3f)));
 154
 155         // set VA_FORM register with faulting formatted address
 156         tc->setMiscRegNoEffect(AlphaISA::IPR_VA_FORM,
 157             tc->readMiscRegNoEffect(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
 158     }
 159
 160     AlphaFault::invoke(tc);
 161 }
 162
 163 void ItbFault::invoke(ThreadContext * tc)
 164 {
 165     if (!tc->misspeculating()) {
 166         tc->setMiscRegNoEffect(AlphaISA::IPR_ITB_TAG, pc);
 167         tc->setMiscRegNoEffect(AlphaISA::IPR_IFAULT_VA_FORM,
 168                        tc->readMiscRegNoEffect(AlphaISA::IPR_IVPTBR) |
 169                        (AlphaISA::VAddr(pc).vpn() << 3));
 170     }
 171
 172     AlphaFault::invoke(tc);
 173 }
 174
 175 #else
 176
 177 void ItbPageFault::invoke(ThreadContext * tc)
 178 {
 179     Process *p = tc->getProcessPtr();
 180     TlbEntry entry;
 181     bool success = p->pTable->lookup(pc, entry);
 182     if(!success) {
 183         panic("Tried to execute unmapped address %#x.\n", pc);
 184     } else {
 185         VAddr vaddr(pc);
 186         tc->getITBPtr()->insert(vaddr.page(), entry);
 187     }
 188 }
 189
 190 void NDtbMissFault::invoke(ThreadContext * tc)
 191 {
 192     Process *p = tc->getProcessPtr();
 193     TlbEntry entry;
 194     bool success = p->pTable->lookup(vaddr, entry);
 195     if(!success) {
 196         p->checkAndAllocNextPage(vaddr);
 197         success = p->pTable->lookup(vaddr, entry);
 198     }
 199     if(!success) {
 200         panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
 201     } else {
 202         tc->getDTBPtr()->insert(vaddr.page(), entry);
 203     }
 204 }
 205
 206 #endif
 207
 208 } // namespace AlphaISA
 209