src/arch/alpha/faults.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Kevin Lim
  30  */
  31
  32 #include "arch/alpha/faults.hh"
  33 #include "cpu/exec_context.hh"
  34 #include "cpu/base.hh"
  35 #include "base/trace.hh"
  36 #if FULL_SYSTEM
  37 #include "arch/alpha/ev5.hh"
  38 #endif
  39
  40 namespace AlphaISA
  41 {
  42
  43 FaultName MachineCheckFault::_name = "mchk";
  44 FaultVect MachineCheckFault::_vect = 0x0401;
  45 FaultStat MachineCheckFault::_count;
  46
  47 FaultName AlignmentFault::_name = "unalign";
  48 FaultVect AlignmentFault::_vect = 0x0301;
  49 FaultStat AlignmentFault::_count;
  50
  51 FaultName ResetFault::_name = "reset";
  52 FaultVect ResetFault::_vect = 0x0001;
  53 FaultStat ResetFault::_count;
  54
  55 FaultName ArithmeticFault::_name = "arith";
  56 FaultVect ArithmeticFault::_vect = 0x0501;
  57 FaultStat ArithmeticFault::_count;
  58
  59 FaultName InterruptFault::_name = "interrupt";
  60 FaultVect InterruptFault::_vect = 0x0101;
  61 FaultStat InterruptFault::_count;
  62
  63 FaultName NDtbMissFault::_name = "dtb_miss_single";
  64 FaultVect NDtbMissFault::_vect = 0x0201;
  65 FaultStat NDtbMissFault::_count;
  66
  67 FaultName PDtbMissFault::_name = "dtb_miss_double";
  68 FaultVect PDtbMissFault::_vect = 0x0281;
  69 FaultStat PDtbMissFault::_count;
  70
  71 FaultName DtbPageFault::_name = "dfault";
  72 FaultVect DtbPageFault::_vect = 0x0381;
  73 FaultStat DtbPageFault::_count;
  74
  75 FaultName DtbAcvFault::_name = "dfault";
  76 FaultVect DtbAcvFault::_vect = 0x0381;
  77 FaultStat DtbAcvFault::_count;
  78
  79 FaultName DtbAlignmentFault::_name = "unalign";
  80 FaultVect DtbAlignmentFault::_vect = 0x0301;
  81 FaultStat DtbAlignmentFault::_count;
  82
  83 FaultName ItbMissFault::_name = "itbmiss";
  84 FaultVect ItbMissFault::_vect = 0x0181;
  85 FaultStat ItbMissFault::_count;
  86
  87 FaultName ItbPageFault::_name = "itbmiss";
  88 FaultVect ItbPageFault::_vect = 0x0181;
  89 FaultStat ItbPageFault::_count;
  90
  91 FaultName ItbAcvFault::_name = "iaccvio";
  92 FaultVect ItbAcvFault::_vect = 0x0081;
  93 FaultStat ItbAcvFault::_count;
  94
  95 FaultName UnimplementedOpcodeFault::_name = "opdec";
  96 FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
  97 FaultStat UnimplementedOpcodeFault::_count;
  98
  99 FaultName FloatEnableFault::_name = "fen";
 100 FaultVect FloatEnableFault::_vect = 0x0581;
 101 FaultStat FloatEnableFault::_count;
 102
 103 FaultName PalFault::_name = "pal";
 104 FaultVect PalFault::_vect = 0x2001;
 105 FaultStat PalFault::_count;
 106
 107 FaultName IntegerOverflowFault::_name = "intover";
 108 FaultVect IntegerOverflowFault::_vect = 0x0501;
 109 FaultStat IntegerOverflowFault::_count;
 110
 111 #if FULL_SYSTEM
 112
 113 void AlphaFault::invoke(ExecContext * xc)
 114 {
 115     FaultBase::invoke(xc);
 116     countStat()++;
 117
 118     // exception restart address
 119     if (setRestartAddress() || !xc->inPalMode())
 120         xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->readPC());
 121
 122     if (skipFaultingInstruction()) {
 123         // traps...  skip faulting instruction.
 124         xc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
 125                    xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
 126     }
 127
 128     xc->setPC(xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect());
 129     xc->setNextPC(xc->readPC() + sizeof(MachInst));
 130 }
 131
 132 void ArithmeticFault::invoke(ExecContext * xc)
 133 {
 134     FaultBase::invoke(xc);
 135     panic("Arithmetic traps are unimplemented!");
 136 }
 137
 138 void DtbFault::invoke(ExecContext * xc)
 139 {
 140     // Set fault address and flags.  Even though we're modeling an
 141     // EV5, we use the EV6 technique of not latching fault registers
 142     // on VPTE loads (instead of locking the registers until IPR_VA is
 143     // read, like the EV5).  The EV6 approach is cleaner and seems to
 144     // work with EV5 PAL code, but not the other way around.
 145     if (!xc->misspeculating()
 146         && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
 147         // set VA register with faulting address
 148         xc->setMiscReg(AlphaISA::IPR_VA, vaddr);
 149
 150         // set MM_STAT register flags
 151         xc->setMiscReg(AlphaISA::IPR_MM_STAT,
 152             (((EV5::Opcode(xc->getInst()) & 0x3f) << 11)
 153              | ((EV5::Ra(xc->getInst()) & 0x1f) << 6)
 154              | (flags & 0x3f)));
 155
 156         // set VA_FORM register with faulting formatted address
 157         xc->setMiscReg(AlphaISA::IPR_VA_FORM,
 158             xc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
 159     }
 160
 161     AlphaFault::invoke(xc);
 162 }
 163
 164 void ItbFault::invoke(ExecContext * xc)
 165 {
 166     if (!xc->misspeculating()) {
 167         xc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc);
 168         xc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM,
 169                        xc->readMiscReg(AlphaISA::IPR_IVPTBR) |
 170                        (AlphaISA::VAddr(pc).vpn() << 3));
 171     }
 172
 173     AlphaFault::invoke(xc);
 174 }
 175
 176 #endif
 177
 178 } // namespace AlphaISA
 179